[INFO] fetching crate mspm0l130x 0.1.5... [INFO] building mspm0l130x-0.1.5 against try#d79d87d4c0f7f0d0785ad6e493cf8cf718ed89a6 for pr-146237-1 [INFO] extracting crate mspm0l130x 0.1.5 into /workspace/builds/worker-4-tc2/source [INFO] started tweaking crates.io crate mspm0l130x 0.1.5 [INFO] finished tweaking crates.io crate mspm0l130x 0.1.5 [INFO] tweaked toml for crates.io crate mspm0l130x 0.1.5 written to /workspace/builds/worker-4-tc2/source/Cargo.toml [INFO] validating manifest of crates.io crate mspm0l130x 0.1.5 on toolchain d79d87d4c0f7f0d0785ad6e493cf8cf718ed89a6 [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+d79d87d4c0f7f0d0785ad6e493cf8cf718ed89a6" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }` [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+d79d87d4c0f7f0d0785ad6e493cf8cf718ed89a6" "generate-lockfile" "--manifest-path" "Cargo.toml", kill_on_drop: false }` [INFO] [stderr] Updating crates.io index [INFO] [stderr] Locking 28 packages to latest compatible versions [INFO] [stderr] Adding cortex-m v0.6.7 (available: v0.7.7) [INFO] [stderr] Adding cortex-m-rt v0.6.15 (available: v0.7.5) [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+d79d87d4c0f7f0d0785ad6e493cf8cf718ed89a6" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }` [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-4-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-4-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:e90291280db7d1fac5b66fc6dad9f9662629e7365a55743daf9bdf73ebc4ea79" "/opt/rustwide/cargo-home/bin/cargo" "+d79d87d4c0f7f0d0785ad6e493cf8cf718ed89a6" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }` [INFO] [stdout] ee667fcd99722994a1a4c4cb7ef7bce6756f0c08822edd64321bf9d8897879ce [INFO] running `Command { std: "docker" "start" "-a" "ee667fcd99722994a1a4c4cb7ef7bce6756f0c08822edd64321bf9d8897879ce", kill_on_drop: false }` [INFO] running `Command { std: "docker" "inspect" "ee667fcd99722994a1a4c4cb7ef7bce6756f0c08822edd64321bf9d8897879ce", kill_on_drop: false }` [INFO] running `Command { std: "docker" "rm" "-f" "ee667fcd99722994a1a4c4cb7ef7bce6756f0c08822edd64321bf9d8897879ce", kill_on_drop: false }` [INFO] [stdout] ee667fcd99722994a1a4c4cb7ef7bce6756f0c08822edd64321bf9d8897879ce [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-4-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-4-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:e90291280db7d1fac5b66fc6dad9f9662629e7365a55743daf9bdf73ebc4ea79" "/opt/rustwide/cargo-home/bin/cargo" "+d79d87d4c0f7f0d0785ad6e493cf8cf718ed89a6" "build" "--frozen" "--message-format=json", kill_on_drop: false }` [INFO] [stdout] 8c5b392622fb148763de7779c023646904b781e3405666392fa0095e43a0f8d0 [INFO] running `Command { std: "docker" "start" "-a" "8c5b392622fb148763de7779c023646904b781e3405666392fa0095e43a0f8d0", kill_on_drop: false }` [INFO] [stderr] Compiling bare-metal v0.2.5 [INFO] [stderr] Compiling generic-array v0.14.7 [INFO] [stderr] Compiling cortex-m v0.7.7 [INFO] [stderr] Compiling nb v1.1.0 [INFO] [stderr] Compiling generic-array v0.13.3 [INFO] [stderr] Compiling generic-array v0.12.4 [INFO] [stderr] Compiling void v1.0.2 [INFO] [stderr] Compiling vcell v0.1.3 [INFO] [stderr] Compiling cortex-m v0.6.7 [INFO] [stderr] Compiling bitfield v0.13.2 [INFO] [stderr] Compiling mspm0l130x v0.1.5 (/opt/rustwide/workdir) [INFO] [stderr] Compiling volatile-register v0.2.2 [INFO] [stderr] Compiling nb v0.1.3 [INFO] [stderr] Compiling embedded-hal v0.2.7 [INFO] [stderr] Compiling as-slice v0.1.5 [INFO] [stderr] Compiling aligned v0.3.5 [INFO] [stdout] warning: unexpected `cfg` condition value: `critical-section` [INFO] [stdout] --> src/lib.rs:2:42742 [INFO] [stdout] | [INFO] [stdout] 2 | ...c = r" Returns all the peripherals *once*."] # [cfg (feature = "critical-section")] # [inline] pub fn take () -> Option < Self > { cri... [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: expected values for `feature` are: `cortex-m-rt` and `rt` [INFO] [stdout] = help: consider adding `critical-section` as a feature in `Cargo.toml` [INFO] [stdout] = note: see for more information about checking conditional configuration [INFO] [stdout] = note: `#[warn(unexpected_cfgs)]` on by default [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/pwren.rs:1:2941 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] = note: `#[warn(mismatched_lifetime_syntaxes)]` on by default [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W <'_, PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/pwren.rs:1:3131 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W <'_, PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/rstctl.rs:1:3243 [INFO] [stdout] | [INFO] [stdout] 1 | ...fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W <'_, RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/rstctl.rs:1:3464 [INFO] [stdout] | [INFO] [stdout] 1 | ... rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W <'_, RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/pwren.rs:1:2941 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W <'_, PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/pwren.rs:1:3131 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W <'_, PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/rstctl.rs:1:3243 [INFO] [stdout] | [INFO] [stdout] 1 | ...fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W <'_, RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/rstctl.rs:1:3464 [INFO] [stdout] | [INFO] [stdout] 1 | ... rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W <'_, RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/rstctl.rs:1:3649 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W <'_, RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/clkovr.rs:10:111 [INFO] [stdout] | [INFO] [stdout] 10 | ...pub fn clkovr_override (& mut self) -> CLKOVR_OVERRIDE_W < CLKOVR_SPEC , 0 > { CLKOVR_OVERRIDE_W :: new (self) } # [doc = "Bit 1 - If ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 10 | to override the automatic peripheral clock request"] # [inline (always)] # [must_use] pub fn clkovr_override (& mut self) -> CLKOVR_OVERRIDE_W <'_, CLKOVR_SPEC , 0 > { CLKOVR_OVERRIDE_W :: new (self) } # [doc = "Bit 1 - If \\[OVERRIDE\\] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/clkovr.rs:11:159 [INFO] [stdout] | [INFO] [stdout] 11 | ...pub fn clkovr_run_stop (& mut self) -> CLKOVR_RUN_STOP_W < CLKOVR_SPEC , 1 > { CLKOVR_RUN_STOP_W :: new (self) } # [doc = r" Writes ra... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 11 | is enabled, this register is used to manually control the peripheral's clock request to the system"] # [inline (always)] # [must_use] pub fn clkovr_run_stop (& mut self) -> CLKOVR_RUN_STOP_W <'_, CLKOVR_SPEC , 1 > { CLKOVR_RUN_STOP_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Override\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkovr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkovr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKOVR_SPEC ; impl crate :: RegisterSpec for CLKOVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkovr::R`](R) reader structure"] impl crate :: Readable for CLKOVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkovr::W`](W) writer structure"] impl crate :: Writable for CLKOVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKOVR to value 0"] impl crate :: Resettable for CLKOVR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/rstctl.rs:1:3649 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W <'_, RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clkcfg.rs:1:3453 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKCFG` reader"] pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"] pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"] CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"] CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)] fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"] CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)] fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"] pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"] # [inline (always)] pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] # [must_use] pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W <'_, CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"] # [inline (always)] # [must_use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"] impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"] impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"] impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/pwrctl.rs:1:2896 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn pwrctl_auto_off (& mut self) -> PWRCTL_AUTO_OFF_W < PWRCTL_SPEC , 0 > { PWRCTL_AUTO_OFF_W :: new (self) } # [doc = r" Writes ra... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWRCTL` reader"] pub type R = crate :: R < PWRCTL_SPEC > ; # [doc = "Register `PWRCTL` writer"] pub type W = crate :: W < PWRCTL_SPEC > ; # [doc = "Field `PWRCTL_AUTO_OFF` reader - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] pub type PWRCTL_AUTO_OFF_R = crate :: BitReader < PWRCTL_AUTO_OFF_A > ; # [doc = "When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWRCTL_AUTO_OFF_A { # [doc = "0: DISABLE"] PWRCTL_AUTO_OFF_DISABLE = 0 , # [doc = "1: ENABLE"] PWRCTL_AUTO_OFF_ENABLE = 1 , } impl From < PWRCTL_AUTO_OFF_A > for bool { # [inline (always)] fn from (variant : PWRCTL_AUTO_OFF_A) -> Self { variant as u8 != 0 } } impl PWRCTL_AUTO_OFF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWRCTL_AUTO_OFF_A { match self . bits { false => PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE , true => PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwrctl_auto_off_disable (& self) -> bool { * self == PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwrctl_auto_off_enable (& self) -> bool { * self == PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE } } # [doc = "Field `PWRCTL_AUTO_OFF` writer - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] pub type PWRCTL_AUTO_OFF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWRCTL_AUTO_OFF_A > ; impl < 'a , REG , const O : u8 > PWRCTL_AUTO_OFF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwrctl_auto_off_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwrctl_auto_off_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE) } } impl R { # [doc = "Bit 0 - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] # [inline (always)] pub fn pwrctl_auto_off (& self) -> PWRCTL_AUTO_OFF_R { PWRCTL_AUTO_OFF_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."] # [inline (always)] # [must_use] pub fn pwrctl_auto_off (& mut self) -> PWRCTL_AUTO_OFF_W <'_, PWRCTL_SPEC , 0 > { PWRCTL_AUTO_OFF_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwrctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWRCTL_SPEC ; impl crate :: RegisterSpec for PWRCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwrctl::R`](R) reader structure"] impl crate :: Readable for PWRCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwrctl::W`](W) writer structure"] impl crate :: Writable for PWRCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWRCTL to value 0"] impl crate :: Resettable for PWRCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/ctl.rs:1:1892 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn ctl_enable (& mut self) -> CTL_ENABLE_W < CTL_SPEC , 0 > { CTL_ENABLE_W :: new (self) } # [doc = r" Writes raw bits to... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL` reader"] pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"] pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_ENABLE` reader - OAxn Enable."] pub type CTL_ENABLE_R = crate :: BitReader < CTL_ENABLE_A > ; # [doc = "OAxn Enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_ENABLE_A { # [doc = "0: OFF"] CTL_ENABLE_OFF = 0 , # [doc = "1: ON"] CTL_ENABLE_ON = 1 , } impl From < CTL_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_ENABLE_A { match self . bits { false => CTL_ENABLE_A :: CTL_ENABLE_OFF , true => CTL_ENABLE_A :: CTL_ENABLE_ON , } } # [doc = "OFF"] # [inline (always)] pub fn is_ctl_enable_off (& self) -> bool { * self == CTL_ENABLE_A :: CTL_ENABLE_OFF } # [doc = "ON"] # [inline (always)] pub fn is_ctl_enable_on (& self) -> bool { * self == CTL_ENABLE_A :: CTL_ENABLE_ON } } # [doc = "Field `CTL_ENABLE` writer - OAxn Enable."] pub type CTL_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"] # [inline (always)] pub fn ctl_enable_off (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ENABLE_A :: CTL_ENABLE_OFF) } # [doc = "ON"] # [inline (always)] pub fn ctl_enable_on (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ENABLE_A :: CTL_ENABLE_ON) } } impl R { # [doc = "Bit 0 - OAxn Enable."] # [inline (always)] pub fn ctl_enable (& self) -> CTL_ENABLE_R { CTL_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - OAxn Enable."] # [inline (always)] # [must_use] pub fn ctl_enable (& mut self) -> CTL_ENABLE_W <'_, CTL_SPEC , 0 > { CTL_ENABLE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"] impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0"] impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clkcfg.rs:1:3657 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKCFG` reader"] pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"] pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"] CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"] CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)] fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"] CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)] fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"] pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"] # [inline (always)] pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"] # [inline (always)] # [must_use] pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"] # [inline (always)] # [must_use] pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W <'_, CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"] impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"] impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"] impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfgbase.rs:1:4840 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn cfgbase_gbw (& mut self) -> CFGBASE_GBW_W < CFGBASE_SPEC , 0 > { CFGBASE_GBW_W :: new (self) } # [doc = "Bit 2 - Rail-to-... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGBASE` reader"] pub type R = crate :: R < CFGBASE_SPEC > ; # [doc = "Register `CFGBASE` writer"] pub type W = crate :: W < CFGBASE_SPEC > ; # [doc = "Field `CFGBASE_GBW` reader - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_R = crate :: BitReader < CFGBASE_GBW_A > ; # [doc = "Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_GBW_A { # [doc = "0: LOWGAIN"] CFGBASE_GBW_LOWGAIN = 0 , # [doc = "1: HIGHGAIN"] CFGBASE_GBW_HIGHGAIN = 1 , } impl From < CFGBASE_GBW_A > for bool { # [inline (always)] fn from (variant : CFGBASE_GBW_A) -> Self { variant as u8 != 0 } } impl CFGBASE_GBW_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_GBW_A { match self . bits { false => CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN , true => CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN , } } # [doc = "LOWGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_lowgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN } # [doc = "HIGHGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_highgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN } } # [doc = "Field `CFGBASE_GBW` writer - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_GBW_A > ; impl < 'a , REG , const O : u8 > CFGBASE_GBW_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOWGAIN"] # [inline (always)] pub fn cfgbase_gbw_lowgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN) } # [doc = "HIGHGAIN"] # [inline (always)] pub fn cfgbase_gbw_highgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN) } } # [doc = "Field `CFGBASE_RRI` reader - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_R = crate :: BitReader < CFGBASE_RRI_A > ; # [doc = "Rail-to-rail input enable. Can only be modified when STAT.BUSY=0\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_RRI_A { # [doc = "0: OFF"] CFGBASE_RRI_OFF = 0 , # [doc = "1: ON"] CFGBASE_RRI_ON = 1 , } impl From < CFGBASE_RRI_A > for bool { # [inline (always)] fn from (variant : CFGBASE_RRI_A) -> Self { variant as u8 != 0 } } impl CFGBASE_RRI_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_RRI_A { match self . bits { false => CFGBASE_RRI_A :: CFGBASE_RRI_OFF , true => CFGBASE_RRI_A :: CFGBASE_RRI_ON , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfgbase_rri_off (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfgbase_rri_on (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_ON } } # [doc = "Field `CFGBASE_RRI` writer - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_RRI_A > ; impl < 'a , REG , const O : u8 > CFGBASE_RRI_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"] # [inline (always)] pub fn cfgbase_rri_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfgbase_rri_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_ON) } } impl R { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] pub fn cfgbase_gbw (& self) -> CFGBASE_GBW_R { CFGBASE_GBW_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] pub fn cfgbase_rri (& self) -> CFGBASE_RRI_R { CFGBASE_RRI_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] # [must_use] pub fn cfgbase_gbw (& mut self) -> CFGBASE_GBW_W <'_, CFGBASE_SPEC , 0 > { CFGBASE_GBW_W :: new (self) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] # [must_use] pub fn cfgbase_rri (& mut self) -> CFGBASE_RRI_W < CFGBASE_SPEC , 2 > { CFGBASE_RRI_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Base Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgbase::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgbase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFGBASE_SPEC ; impl crate :: RegisterSpec for CFGBASE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgbase::R`](R) reader structure"] impl crate :: Readable for CFGBASE_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgbase::W`](W) writer structure"] impl crate :: Writable for CFGBASE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFGBASE to value 0"] impl crate :: Resettable for CFGBASE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clkdiv.rs:1:4791 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bi... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKDIV` reader"] pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"] pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"] CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"] CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"] CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"] CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"] CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"] CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"] CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"] CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)] fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"] # [inline (always)] pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"] # [inline (always)] pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"] # [inline (always)] pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"] # [inline (always)] pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"] # [inline (always)] pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"] # [inline (always)] pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"] # [inline (always)] pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"] # [inline (always)] pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] # [must_use] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W <'_, CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"] impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"] impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"] impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clksel.rs:1:6426 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - S... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W <'_, CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfgbase.rs:1:5060 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn cfgbase_rri (& mut self) -> CFGBASE_RRI_W < CFGBASE_SPEC , 2 > { CFGBASE_RRI_W :: new (self) } # [doc = r" Writes raw bit... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGBASE` reader"] pub type R = crate :: R < CFGBASE_SPEC > ; # [doc = "Register `CFGBASE` writer"] pub type W = crate :: W < CFGBASE_SPEC > ; # [doc = "Field `CFGBASE_GBW` reader - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_R = crate :: BitReader < CFGBASE_GBW_A > ; # [doc = "Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_GBW_A { # [doc = "0: LOWGAIN"] CFGBASE_GBW_LOWGAIN = 0 , # [doc = "1: HIGHGAIN"] CFGBASE_GBW_HIGHGAIN = 1 , } impl From < CFGBASE_GBW_A > for bool { # [inline (always)] fn from (variant : CFGBASE_GBW_A) -> Self { variant as u8 != 0 } } impl CFGBASE_GBW_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_GBW_A { match self . bits { false => CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN , true => CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN , } } # [doc = "LOWGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_lowgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN } # [doc = "HIGHGAIN"] # [inline (always)] pub fn is_cfgbase_gbw_highgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN } } # [doc = "Field `CFGBASE_GBW` writer - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] pub type CFGBASE_GBW_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_GBW_A > ; impl < 'a , REG , const O : u8 > CFGBASE_GBW_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOWGAIN"] # [inline (always)] pub fn cfgbase_gbw_lowgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN) } # [doc = "HIGHGAIN"] # [inline (always)] pub fn cfgbase_gbw_highgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN) } } # [doc = "Field `CFGBASE_RRI` reader - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_R = crate :: BitReader < CFGBASE_RRI_A > ; # [doc = "Rail-to-rail input enable. Can only be modified when STAT.BUSY=0\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFGBASE_RRI_A { # [doc = "0: OFF"] CFGBASE_RRI_OFF = 0 , # [doc = "1: ON"] CFGBASE_RRI_ON = 1 , } impl From < CFGBASE_RRI_A > for bool { # [inline (always)] fn from (variant : CFGBASE_RRI_A) -> Self { variant as u8 != 0 } } impl CFGBASE_RRI_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFGBASE_RRI_A { match self . bits { false => CFGBASE_RRI_A :: CFGBASE_RRI_OFF , true => CFGBASE_RRI_A :: CFGBASE_RRI_ON , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfgbase_rri_off (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfgbase_rri_on (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_ON } } # [doc = "Field `CFGBASE_RRI` writer - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] pub type CFGBASE_RRI_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_RRI_A > ; impl < 'a , REG , const O : u8 > CFGBASE_RRI_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"] # [inline (always)] pub fn cfgbase_rri_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfgbase_rri_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_ON) } } impl R { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] pub fn cfgbase_gbw (& self) -> CFGBASE_GBW_R { CFGBASE_GBW_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] pub fn cfgbase_rri (& self) -> CFGBASE_RRI_R { CFGBASE_RRI_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."] # [inline (always)] # [must_use] pub fn cfgbase_gbw (& mut self) -> CFGBASE_GBW_W < CFGBASE_SPEC , 0 > { CFGBASE_GBW_W :: new (self) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"] # [inline (always)] # [must_use] pub fn cfgbase_rri (& mut self) -> CFGBASE_RRI_W <'_, CFGBASE_SPEC , 2 > { CFGBASE_RRI_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Base Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgbase::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgbase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFGBASE_SPEC ; impl crate :: RegisterSpec for CFGBASE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgbase::R`](R) reader structure"] impl crate :: Readable for CFGBASE_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgbase::W`](W) writer structure"] impl crate :: Writable for CFGBASE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFGBASE to value 0"] impl crate :: Resettable for CFGBASE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfg.rs:1:16556 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output p... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W <'_, CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clksel.rs:1:6636 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - S... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W <'_, CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/clksel.rs:1:6849 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W <'_, CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfg.rs:1:16718 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W <'_, CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/int_group0_iset.rs:1:1312 [INFO] [stdout] | [INFO] [stdout] 1 | ..._group0_iset_int (& mut self) -> INT_GROUP0_ISET_INT_W < INT_GROUP0_ISET_SPEC , 0 > { INT_GROUP0_ISET_INT_W :: new (self) } # [doc = r... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_GROUP0_ISET` writer"] pub type W = crate :: W < INT_GROUP0_ISET_SPEC > ; # [doc = "Sets INT in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_GROUP0_ISET_INT_AW { # [doc = "0: NO_EFFECT"] INT_GROUP0_ISET_INT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_GROUP0_ISET_INT_SET = 1 , } impl From < INT_GROUP0_ISET_INT_AW > for bool { # [inline (always)] fn from (variant : INT_GROUP0_ISET_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP0_ISET_INT` writer - Sets INT in RIS register"] pub type INT_GROUP0_ISET_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP0_ISET_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP0_ISET_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_group0_iset_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ISET_INT_AW :: INT_GROUP0_ISET_INT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_group0_iset_int_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ISET_INT_AW :: INT_GROUP0_ISET_INT_SET) } } impl W { # [doc = "Bit 0 - Sets INT in RIS register"] # [inline (always)] # [must_use] pub fn int_group0_iset_int (& mut self) -> INT_GROUP0_ISET_INT_W <'_, INT_GROUP0_ISET_SPEC , 0 > { INT_GROUP0_ISET_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_GROUP0_ISET_SPEC ; impl crate :: RegisterSpec for INT_GROUP0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group0_iset::W`](W) writer structure"] impl crate :: Writable for INT_GROUP0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP0_ISET to value 0"] impl crate :: Resettable for INT_GROUP0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfg.rs:1:16972 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W <'_, CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/int_group0_iclr.rs:1:1318 [INFO] [stdout] | [INFO] [stdout] 1 | ..._group0_iclr_int (& mut self) -> INT_GROUP0_ICLR_INT_W < INT_GROUP0_ICLR_SPEC , 0 > { INT_GROUP0_ICLR_INT_W :: new (self) } # [doc = r... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_GROUP0_ICLR` writer"] pub type W = crate :: W < INT_GROUP0_ICLR_SPEC > ; # [doc = "Clears INT in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_GROUP0_ICLR_INT_AW { # [doc = "0: NO_EFFECT"] INT_GROUP0_ICLR_INT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_GROUP0_ICLR_INT_CLR = 1 , } impl From < INT_GROUP0_ICLR_INT_AW > for bool { # [inline (always)] fn from (variant : INT_GROUP0_ICLR_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP0_ICLR_INT` writer - Clears INT in RIS register"] pub type INT_GROUP0_ICLR_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP0_ICLR_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP0_ICLR_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_group0_iclr_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ICLR_INT_AW :: INT_GROUP0_ICLR_INT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_group0_iclr_int_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ICLR_INT_AW :: INT_GROUP0_ICLR_INT_CLR) } } impl W { # [doc = "Bit 0 - Clears INT in RIS register"] # [inline (always)] # [must_use] pub fn int_group0_iclr_int (& mut self) -> INT_GROUP0_ICLR_INT_W <'_, INT_GROUP0_ICLR_SPEC , 0 > { INT_GROUP0_ICLR_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_GROUP0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_GROUP0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group0_iclr::W`](W) writer structure"] impl crate :: Writable for INT_GROUP0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP0_ICLR to value 0"] impl crate :: Resettable for INT_GROUP0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/int_group1_iset.rs:1:1312 [INFO] [stdout] | [INFO] [stdout] 1 | ..._group1_iset_int (& mut self) -> INT_GROUP1_ISET_INT_W < INT_GROUP1_ISET_SPEC , 0 > { INT_GROUP1_ISET_INT_W :: new (self) } # [doc = r... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_GROUP1_ISET` writer"] pub type W = crate :: W < INT_GROUP1_ISET_SPEC > ; # [doc = "Sets INT in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_GROUP1_ISET_INT_AW { # [doc = "0: NO_EFFECT"] INT_GROUP1_ISET_INT_NO_EFFECT = 0 , # [doc = "1: SET"] INT_GROUP1_ISET_INT_SET = 1 , } impl From < INT_GROUP1_ISET_INT_AW > for bool { # [inline (always)] fn from (variant : INT_GROUP1_ISET_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP1_ISET_INT` writer - Sets INT in RIS register"] pub type INT_GROUP1_ISET_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP1_ISET_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP1_ISET_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_group1_iset_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ISET_INT_AW :: INT_GROUP1_ISET_INT_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_group1_iset_int_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ISET_INT_AW :: INT_GROUP1_ISET_INT_SET) } } impl W { # [doc = "Bit 0 - Sets INT in RIS register"] # [inline (always)] # [must_use] pub fn int_group1_iset_int (& mut self) -> INT_GROUP1_ISET_INT_W <'_, INT_GROUP1_ISET_SPEC , 0 > { INT_GROUP1_ISET_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_GROUP1_ISET_SPEC ; impl crate :: RegisterSpec for INT_GROUP1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group1_iset::W`](W) writer structure"] impl crate :: Writable for INT_GROUP1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP1_ISET to value 0"] impl crate :: Resettable for INT_GROUP1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/int_group1_iclr.rs:1:1318 [INFO] [stdout] | [INFO] [stdout] 1 | ..._group1_iclr_int (& mut self) -> INT_GROUP1_ICLR_INT_W < INT_GROUP1_ICLR_SPEC , 0 > { INT_GROUP1_ICLR_INT_W :: new (self) } # [doc = r... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_GROUP1_ICLR` writer"] pub type W = crate :: W < INT_GROUP1_ICLR_SPEC > ; # [doc = "Clears INT in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_GROUP1_ICLR_INT_AW { # [doc = "0: NO_EFFECT"] INT_GROUP1_ICLR_INT_NO_EFFECT = 0 , # [doc = "1: CLR"] INT_GROUP1_ICLR_INT_CLR = 1 , } impl From < INT_GROUP1_ICLR_INT_AW > for bool { # [inline (always)] fn from (variant : INT_GROUP1_ICLR_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP1_ICLR_INT` writer - Clears INT in RIS register"] pub type INT_GROUP1_ICLR_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP1_ICLR_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP1_ICLR_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_group1_iclr_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ICLR_INT_AW :: INT_GROUP1_ICLR_INT_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn int_group1_iclr_int_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ICLR_INT_AW :: INT_GROUP1_ICLR_INT_CLR) } } impl W { # [doc = "Bit 0 - Clears INT in RIS register"] # [inline (always)] # [must_use] pub fn int_group1_iclr_int (& mut self) -> INT_GROUP1_ICLR_INT_W <'_, INT_GROUP1_ICLR_SPEC , 0 > { INT_GROUP1_ICLR_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_GROUP1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_GROUP1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group1_iclr::W`](W) writer structure"] impl crate :: Writable for INT_GROUP1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP1_ICLR to value 0"] impl crate :: Resettable for INT_GROUP1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/pdbgctl.rs:5:247 [INFO] [stdout] | [INFO] [stdout] 5 | ...se] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft ha... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 5 | is set to 'STOP'"] # [inline (always)] pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"] # [inline (always)] # [must_use] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W <'_, PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/clksel.rs:1:6426 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - S... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W <'_, CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/pdbgctl.rs:6:74 [INFO] [stdout] | [INFO] [stdout] 6 | ...se] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bi... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 6 | is set to 'STOP'"] # [inline (always)] # [must_use] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W <'_, PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"] impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"] impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"] impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfg.rs:1:17222 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux s... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W <'_, CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/ctl.rs:1:7350 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn ctl_prefetch (& mut self) -> CTL_PREFETCH_W < CTL_SPEC , 0 > { CTL_PREFETCH_W :: new (self) } # [doc = "Bit 1 - Used to e... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL` reader"] pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"] pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_PREFETCH` reader - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_R = crate :: BitReader < CTL_PREFETCH_A > ; # [doc = "Used to enable/disable instruction prefetch to Flash.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_PREFETCH_A { # [doc = "0: DISABLE"] CTL_PREFETCH_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_PREFETCH_ENABLE = 1 , } impl From < CTL_PREFETCH_A > for bool { # [inline (always)] fn from (variant : CTL_PREFETCH_A) -> Self { variant as u8 != 0 } } impl CTL_PREFETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_PREFETCH_A { match self . bits { false => CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE , true => CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_prefetch_disable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_prefetch_enable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE } } # [doc = "Field `CTL_PREFETCH` writer - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_PREFETCH_A > ; impl < 'a , REG , const O : u8 > CTL_PREFETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_prefetch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_prefetch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE) } } # [doc = "Field `CTL_ICACHE` reader - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_R = crate :: BitReader < CTL_ICACHE_A > ; # [doc = "Used to enable/disable Instruction caching on flash access.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_ICACHE_A { # [doc = "0: DISABLE"] CTL_ICACHE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_ICACHE_ENABLE = 1 , } impl From < CTL_ICACHE_A > for bool { # [inline (always)] fn from (variant : CTL_ICACHE_A) -> Self { variant as u8 != 0 } } impl CTL_ICACHE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_ICACHE_A { match self . bits { false => CTL_ICACHE_A :: CTL_ICACHE_DISABLE , true => CTL_ICACHE_A :: CTL_ICACHE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_icache_disable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_icache_enable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_ENABLE } } # [doc = "Field `CTL_ICACHE` writer - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ICACHE_A > ; impl < 'a , REG , const O : u8 > CTL_ICACHE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_icache_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_icache_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_ENABLE) } } # [doc = "Field `CTL_LITEN` reader - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_R = crate :: BitReader < CTL_LITEN_A > ; # [doc = "Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_LITEN_A { # [doc = "0: DISABLE"] CTL_LITEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_LITEN_ENABLE = 1 , } impl From < CTL_LITEN_A > for bool { # [inline (always)] fn from (variant : CTL_LITEN_A) -> Self { variant as u8 != 0 } } impl CTL_LITEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_LITEN_A { match self . bits { false => CTL_LITEN_A :: CTL_LITEN_DISABLE , true => CTL_LITEN_A :: CTL_LITEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_liten_disable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_liten_enable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_ENABLE } } # [doc = "Field `CTL_LITEN` writer - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_LITEN_A > ; impl < 'a , REG , const O : u8 > CTL_LITEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_liten_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_liten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_ENABLE) } } impl R { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] pub fn ctl_prefetch (& self) -> CTL_PREFETCH_R { CTL_PREFETCH_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] pub fn ctl_icache (& self) -> CTL_ICACHE_R { CTL_ICACHE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] pub fn ctl_liten (& self) -> CTL_LITEN_R { CTL_LITEN_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] # [must_use] pub fn ctl_prefetch (& mut self) -> CTL_PREFETCH_W <'_, CTL_SPEC , 0 > { CTL_PREFETCH_W :: new (self) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] # [must_use] pub fn ctl_icache (& mut self) -> CTL_ICACHE_W < CTL_SPEC , 1 > { CTL_ICACHE_W :: new (self) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] # [must_use] pub fn ctl_liten (& mut self) -> CTL_LITEN_W < CTL_SPEC , 2 > { CTL_LITEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Prefetch/Cache control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"] impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0x07"] impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x07 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/iset.rs:1:1165 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn iset_inttim (& mut self) -> ISET_INTTIM_W < ISET_SPEC , 0 > { ISET_INTTIM_W :: new (self) } # [doc = r" Writes raw bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ISET` writer"] pub type W = crate :: W < ISET_SPEC > ; # [doc = "Interval Timer Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ISET_INTTIM_AW { # [doc = "0: NO_EFFECT"] ISET_INTTIM_NO_EFFECT = 0 , # [doc = "1: SET"] ISET_INTTIM_SET = 1 , } impl From < ISET_INTTIM_AW > for bool { # [inline (always)] fn from (variant : ISET_INTTIM_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_INTTIM` writer - Interval Timer Interrupt."] pub type ISET_INTTIM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_INTTIM_AW > ; impl < 'a , REG , const O : u8 > ISET_INTTIM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iset_inttim_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_INTTIM_AW :: ISET_INTTIM_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn iset_inttim_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_INTTIM_AW :: ISET_INTTIM_SET) } } impl W { # [doc = "Bit 0 - Interval Timer Interrupt."] # [inline (always)] # [must_use] pub fn iset_inttim (& mut self) -> ISET_INTTIM_W <'_, ISET_SPEC , 0 > { ISET_INTTIM_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"] impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"] impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/ctl.rs:1:7562 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn ctl_icache (& mut self) -> CTL_ICACHE_W < CTL_SPEC , 1 > { CTL_ICACHE_W :: new (self) } # [doc = "Bit 2 - Literal cach... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL` reader"] pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"] pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_PREFETCH` reader - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_R = crate :: BitReader < CTL_PREFETCH_A > ; # [doc = "Used to enable/disable instruction prefetch to Flash.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_PREFETCH_A { # [doc = "0: DISABLE"] CTL_PREFETCH_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_PREFETCH_ENABLE = 1 , } impl From < CTL_PREFETCH_A > for bool { # [inline (always)] fn from (variant : CTL_PREFETCH_A) -> Self { variant as u8 != 0 } } impl CTL_PREFETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_PREFETCH_A { match self . bits { false => CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE , true => CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_prefetch_disable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_prefetch_enable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE } } # [doc = "Field `CTL_PREFETCH` writer - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_PREFETCH_A > ; impl < 'a , REG , const O : u8 > CTL_PREFETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_prefetch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_prefetch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE) } } # [doc = "Field `CTL_ICACHE` reader - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_R = crate :: BitReader < CTL_ICACHE_A > ; # [doc = "Used to enable/disable Instruction caching on flash access.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_ICACHE_A { # [doc = "0: DISABLE"] CTL_ICACHE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_ICACHE_ENABLE = 1 , } impl From < CTL_ICACHE_A > for bool { # [inline (always)] fn from (variant : CTL_ICACHE_A) -> Self { variant as u8 != 0 } } impl CTL_ICACHE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_ICACHE_A { match self . bits { false => CTL_ICACHE_A :: CTL_ICACHE_DISABLE , true => CTL_ICACHE_A :: CTL_ICACHE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_icache_disable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_icache_enable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_ENABLE } } # [doc = "Field `CTL_ICACHE` writer - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ICACHE_A > ; impl < 'a , REG , const O : u8 > CTL_ICACHE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_icache_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_icache_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_ENABLE) } } # [doc = "Field `CTL_LITEN` reader - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_R = crate :: BitReader < CTL_LITEN_A > ; # [doc = "Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_LITEN_A { # [doc = "0: DISABLE"] CTL_LITEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_LITEN_ENABLE = 1 , } impl From < CTL_LITEN_A > for bool { # [inline (always)] fn from (variant : CTL_LITEN_A) -> Self { variant as u8 != 0 } } impl CTL_LITEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_LITEN_A { match self . bits { false => CTL_LITEN_A :: CTL_LITEN_DISABLE , true => CTL_LITEN_A :: CTL_LITEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_liten_disable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_liten_enable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_ENABLE } } # [doc = "Field `CTL_LITEN` writer - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_LITEN_A > ; impl < 'a , REG , const O : u8 > CTL_LITEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_liten_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_liten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_ENABLE) } } impl R { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] pub fn ctl_prefetch (& self) -> CTL_PREFETCH_R { CTL_PREFETCH_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] pub fn ctl_icache (& self) -> CTL_ICACHE_R { CTL_ICACHE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] pub fn ctl_liten (& self) -> CTL_LITEN_R { CTL_LITEN_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] # [must_use] pub fn ctl_prefetch (& mut self) -> CTL_PREFETCH_W < CTL_SPEC , 0 > { CTL_PREFETCH_W :: new (self) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] # [must_use] pub fn ctl_icache (& mut self) -> CTL_ICACHE_W <'_, CTL_SPEC , 1 > { CTL_ICACHE_W :: new (self) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] # [must_use] pub fn ctl_liten (& mut self) -> CTL_LITEN_W < CTL_SPEC , 2 > { CTL_LITEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Prefetch/Cache control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"] impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0x07"] impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x07 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/iclr.rs:1:1165 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn iclr_inttim (& mut self) -> ICLR_INTTIM_W < ICLR_SPEC , 0 > { ICLR_INTTIM_W :: new (self) } # [doc = r" Writes raw bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ICLR` writer"] pub type W = crate :: W < ICLR_SPEC > ; # [doc = "Interval Timer Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ICLR_INTTIM_AW { # [doc = "0: NO_EFFECT"] ICLR_INTTIM_NO_EFFECT = 0 , # [doc = "1: CLR"] ICLR_INTTIM_CLR = 1 , } impl From < ICLR_INTTIM_AW > for bool { # [inline (always)] fn from (variant : ICLR_INTTIM_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_INTTIM` writer - Interval Timer Interrupt."] pub type ICLR_INTTIM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_INTTIM_AW > ; impl < 'a , REG , const O : u8 > ICLR_INTTIM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iclr_inttim_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_INTTIM_AW :: ICLR_INTTIM_NO_EFFECT) } # [doc = "CLR"] # [inline (always)] pub fn iclr_inttim_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_INTTIM_AW :: ICLR_INTTIM_CLR) } } impl W { # [doc = "Bit 0 - Interval Timer Interrupt."] # [inline (always)] # [must_use] pub fn iclr_inttim (& mut self) -> ICLR_INTTIM_W <'_, ICLR_SPEC , 0 > { ICLR_INTTIM_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"] impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"] impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/clksel.rs:1:6636 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - S... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W <'_, CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:40498 [INFO] [stdout] | [INFO] [stdout] 1 | ...t0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W <'_, INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/cpuss/ctl.rs:1:8102 [INFO] [stdout] | [INFO] [stdout] 1 | ...[must_use] pub fn ctl_liten (& mut self) -> CTL_LITEN_W < CTL_SPEC , 2 > { CTL_LITEN_W :: new (self) } # [doc = r" Writes raw bits to ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL` reader"] pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"] pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_PREFETCH` reader - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_R = crate :: BitReader < CTL_PREFETCH_A > ; # [doc = "Used to enable/disable instruction prefetch to Flash.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_PREFETCH_A { # [doc = "0: DISABLE"] CTL_PREFETCH_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_PREFETCH_ENABLE = 1 , } impl From < CTL_PREFETCH_A > for bool { # [inline (always)] fn from (variant : CTL_PREFETCH_A) -> Self { variant as u8 != 0 } } impl CTL_PREFETCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_PREFETCH_A { match self . bits { false => CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE , true => CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_prefetch_disable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_prefetch_enable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE } } # [doc = "Field `CTL_PREFETCH` writer - Used to enable/disable instruction prefetch to Flash."] pub type CTL_PREFETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_PREFETCH_A > ; impl < 'a , REG , const O : u8 > CTL_PREFETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_prefetch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_prefetch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE) } } # [doc = "Field `CTL_ICACHE` reader - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_R = crate :: BitReader < CTL_ICACHE_A > ; # [doc = "Used to enable/disable Instruction caching on flash access.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_ICACHE_A { # [doc = "0: DISABLE"] CTL_ICACHE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_ICACHE_ENABLE = 1 , } impl From < CTL_ICACHE_A > for bool { # [inline (always)] fn from (variant : CTL_ICACHE_A) -> Self { variant as u8 != 0 } } impl CTL_ICACHE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_ICACHE_A { match self . bits { false => CTL_ICACHE_A :: CTL_ICACHE_DISABLE , true => CTL_ICACHE_A :: CTL_ICACHE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_icache_disable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_icache_enable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_ENABLE } } # [doc = "Field `CTL_ICACHE` writer - Used to enable/disable Instruction caching on flash access."] pub type CTL_ICACHE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ICACHE_A > ; impl < 'a , REG , const O : u8 > CTL_ICACHE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_icache_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_icache_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_ENABLE) } } # [doc = "Field `CTL_LITEN` reader - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_R = crate :: BitReader < CTL_LITEN_A > ; # [doc = "Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL_LITEN_A { # [doc = "0: DISABLE"] CTL_LITEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL_LITEN_ENABLE = 1 , } impl From < CTL_LITEN_A > for bool { # [inline (always)] fn from (variant : CTL_LITEN_A) -> Self { variant as u8 != 0 } } impl CTL_LITEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL_LITEN_A { match self . bits { false => CTL_LITEN_A :: CTL_LITEN_DISABLE , true => CTL_LITEN_A :: CTL_LITEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl_liten_disable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl_liten_enable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_ENABLE } } # [doc = "Field `CTL_LITEN` writer - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] pub type CTL_LITEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_LITEN_A > ; impl < 'a , REG , const O : u8 > CTL_LITEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl_liten_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl_liten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_ENABLE) } } impl R { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] pub fn ctl_prefetch (& self) -> CTL_PREFETCH_R { CTL_PREFETCH_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] pub fn ctl_icache (& self) -> CTL_ICACHE_R { CTL_ICACHE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] pub fn ctl_liten (& self) -> CTL_LITEN_R { CTL_LITEN_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."] # [inline (always)] # [must_use] pub fn ctl_prefetch (& mut self) -> CTL_PREFETCH_W < CTL_SPEC , 0 > { CTL_PREFETCH_W :: new (self) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."] # [inline (always)] # [must_use] pub fn ctl_icache (& mut self) -> CTL_ICACHE_W < CTL_SPEC , 1 > { CTL_ICACHE_W :: new (self) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"] # [inline (always)] # [must_use] pub fn ctl_liten (& mut self) -> CTL_LITEN_W <'_, CTL_SPEC , 2 > { CTL_LITEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Prefetch/Cache control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"] impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0x07"] impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x07 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/clksel.rs:1:6849 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W <'_, CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfg.rs:1:17465 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain sett... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W <'_, CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/wwdtctl0.rs:1:23079 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn wwdtctl0_clkdiv (& mut self) -> WWDTCTL0_CLKDIV_W < WWDTCTL0_SPEC , 0 > { WWDTCTL0_CLKDIV_W :: new (self) } # [doc = "Bits 4:6 -... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `WWDTCTL0` reader"] pub type R = crate :: R < WWDTCTL0_SPEC > ; # [doc = "Register `WWDTCTL0` writer"] pub type W = crate :: W < WWDTCTL0_SPEC > ; # [doc = "Field `WWDTCTL0_CLKDIV` reader - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_R = crate :: FieldReader ; # [doc = "Field `WWDTCTL0_CLKDIV` writer - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `WWDTCTL0_PER` reader - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_R = crate :: FieldReader < WWDTCTL0_PER_A > ; # [doc = "Timer Period of the WWDT. These bits select the total watchdog timer count.\n\nValue on reset: 4"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_PER_A { # [doc = "0: EN_25"] WWDTCTL0_PER_EN_25 = 0 , # [doc = "1: EN_21"] WWDTCTL0_PER_EN_21 = 1 , # [doc = "2: EN_18"] WWDTCTL0_PER_EN_18 = 2 , # [doc = "3: EN_15"] WWDTCTL0_PER_EN_15 = 3 , # [doc = "4: EN_12"] WWDTCTL0_PER_EN_12 = 4 , # [doc = "5: EN_10"] WWDTCTL0_PER_EN_10 = 5 , # [doc = "6: EN_8"] WWDTCTL0_PER_EN_8 = 6 , # [doc = "7: EN_6"] WWDTCTL0_PER_EN_6 = 7 , } impl From < WWDTCTL0_PER_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_PER_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_PER_A { type Ux = u8 ; } impl WWDTCTL0_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_PER_A { match self . bits { 0 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 , 1 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 , 2 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 , 3 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 , 4 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 , 5 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 , 6 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 , 7 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 , _ => unreachable ! () , } } # [doc = "EN_25"] # [inline (always)] pub fn is_wwdtctl0_per_en_25 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 } # [doc = "EN_21"] # [inline (always)] pub fn is_wwdtctl0_per_en_21 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 } # [doc = "EN_18"] # [inline (always)] pub fn is_wwdtctl0_per_en_18 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 } # [doc = "EN_15"] # [inline (always)] pub fn is_wwdtctl0_per_en_15 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 } # [doc = "EN_12"] # [inline (always)] pub fn is_wwdtctl0_per_en_12 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 } # [doc = "EN_10"] # [inline (always)] pub fn is_wwdtctl0_per_en_10 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 } # [doc = "EN_8"] # [inline (always)] pub fn is_wwdtctl0_per_en_8 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 } # [doc = "EN_6"] # [inline (always)] pub fn is_wwdtctl0_per_en_6 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 } } # [doc = "Field `WWDTCTL0_PER` writer - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_PER_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "EN_25"] # [inline (always)] pub fn wwdtctl0_per_en_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25) } # [doc = "EN_21"] # [inline (always)] pub fn wwdtctl0_per_en_21 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21) } # [doc = "EN_18"] # [inline (always)] pub fn wwdtctl0_per_en_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18) } # [doc = "EN_15"] # [inline (always)] pub fn wwdtctl0_per_en_15 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15) } # [doc = "EN_12"] # [inline (always)] pub fn wwdtctl0_per_en_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12) } # [doc = "EN_10"] # [inline (always)] pub fn wwdtctl0_per_en_10 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10) } # [doc = "EN_8"] # [inline (always)] pub fn wwdtctl0_per_en_8 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8) } # [doc = "EN_6"] # [inline (always)] pub fn wwdtctl0_per_en_6 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6) } } # [doc = "Field `WWDTCTL0_WINDOW0` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_R = crate :: FieldReader < WWDTCTL0_WINDOW0_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW0_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW0_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW0_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW0_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW0_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW0_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW0_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW0_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW0_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW0_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW0_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW0_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW0_A { match self . bits { 0 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 , 1 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 , 2 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 , 3 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 , 4 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 , 5 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 , 6 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 , 7 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window0_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window0_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window0_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window0_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window0_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window0_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window0_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window0_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW0` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW0_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window0_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window0_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window0_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window0_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window0_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window0_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window0_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window0_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87) } } # [doc = "Field `WWDTCTL0_WINDOW1` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_R = crate :: FieldReader < WWDTCTL0_WINDOW1_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW1_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW1_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW1_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW1_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW1_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW1_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW1_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW1_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW1_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW1_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW1_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW1_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW1_A { match self . bits { 0 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 , 1 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 , 2 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 , 3 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 , 4 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 , 5 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 , 6 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 , 7 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window1_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window1_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window1_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window1_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window1_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window1_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window1_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window1_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW1` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW1_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window1_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window1_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window1_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window1_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window1_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window1_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window1_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window1_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87) } } # [doc = "Field `WWDTCTL0_MODE` reader - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_R = crate :: BitReader < WWDTCTL0_MODE_A > ; # [doc = "Window Watchdog Timer Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_MODE_A { # [doc = "0: WINDOW"] WWDTCTL0_MODE_WINDOW = 0 , # [doc = "1: INTERVAL"] WWDTCTL0_MODE_INTERVAL = 1 , } impl From < WWDTCTL0_MODE_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_MODE_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_MODE_A { match self . bits { false => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW , true => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL , } } # [doc = "WINDOW"] # [inline (always)] pub fn is_wwdtctl0_mode_window (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW } # [doc = "INTERVAL"] # [inline (always)] pub fn is_wwdtctl0_mode_interval (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL } } # [doc = "Field `WWDTCTL0_MODE` writer - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_MODE_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "WINDOW"] # [inline (always)] pub fn wwdtctl0_mode_window (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW) } # [doc = "INTERVAL"] # [inline (always)] pub fn wwdtctl0_mode_interval (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL) } } # [doc = "Field `WWDTCTL0_STISM` reader - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_R = crate :: BitReader < WWDTCTL0_STISM_A > ; # [doc = "Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_STISM_A { # [doc = "0: CONT"] WWDTCTL0_STISM_CONT = 0 , # [doc = "1: STOP"] WWDTCTL0_STISM_STOP = 1 , } impl From < WWDTCTL0_STISM_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_STISM_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_STISM_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_STISM_A { match self . bits { false => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT , true => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP , } } # [doc = "CONT"] # [inline (always)] pub fn is_wwdtctl0_stism_cont (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT } # [doc = "STOP"] # [inline (always)] pub fn is_wwdtctl0_stism_stop (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP } } # [doc = "Field `WWDTCTL0_STISM` writer - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_STISM_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_STISM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONT"] # [inline (always)] pub fn wwdtctl0_stism_cont (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT) } # [doc = "STOP"] # [inline (always)] pub fn wwdtctl0_stism_stop (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP) } } # [doc = "Field `WWDTCTL0_KEY` reader - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_R = crate :: FieldReader < WWDTCTL0_KEY_A > ; # [doc = "KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_KEY_A { # [doc = "201: _TO_UNLOCK_W_"] WWDTCTL0_KEY_UNLOCK_W = 201 , } impl From < WWDTCTL0_KEY_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_KEY_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_KEY_A { type Ux = u8 ; } impl WWDTCTL0_KEY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < WWDTCTL0_KEY_A > { match self . bits { 201 => Some (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) , _ => None , } } # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn is_wwdtctl0_key_unlock_w (& self) -> bool { * self == WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W } } # [doc = "Field `WWDTCTL0_KEY` writer - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , WWDTCTL0_KEY_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn wwdtctl0_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) } } impl R { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] pub fn wwdtctl0_clkdiv (& self) -> WWDTCTL0_CLKDIV_R { WWDTCTL0_CLKDIV_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] pub fn wwdtctl0_per (& self) -> WWDTCTL0_PER_R { WWDTCTL0_PER_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window0 (& self) -> WWDTCTL0_WINDOW0_R { WWDTCTL0_WINDOW0_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window1 (& self) -> WWDTCTL0_WINDOW1_R { WWDTCTL0_WINDOW1_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] pub fn wwdtctl0_mode (& self) -> WWDTCTL0_MODE_R { WWDTCTL0_MODE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] pub fn wwdtctl0_stism (& self) -> WWDTCTL0_STISM_R { WWDTCTL0_STISM_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] pub fn wwdtctl0_key (& self) -> WWDTCTL0_KEY_R { WWDTCTL0_KEY_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_clkdiv (& mut self) -> WWDTCTL0_CLKDIV_W <'_, WWDTCTL0_SPEC , 0 > { WWDTCTL0_CLKDIV_W :: new (self) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] # [must_use] pub fn wwdtctl0_per (& mut self) -> WWDTCTL0_PER_W < WWDTCTL0_SPEC , 4 > { WWDTCTL0_PER_W :: new (self) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window0 (& mut self) -> WWDTCTL0_WINDOW0_W < WWDTCTL0_SPEC , 8 > { WWDTCTL0_WINDOW0_W :: new (self) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window1 (& mut self) -> WWDTCTL0_WINDOW1_W < WWDTCTL0_SPEC , 12 > { WWDTCTL0_WINDOW1_W :: new (self) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] # [must_use] pub fn wwdtctl0_mode (& mut self) -> WWDTCTL0_MODE_W < WWDTCTL0_SPEC , 16 > { WWDTCTL0_MODE_W :: new (self) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] # [must_use] pub fn wwdtctl0_stism (& mut self) -> WWDTCTL0_STISM_W < WWDTCTL0_SPEC , 17 > { WWDTCTL0_STISM_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_key (& mut self) -> WWDTCTL0_KEY_W < WWDTCTL0_SPEC , 24 > { WWDTCTL0_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WWDTCTL0_SPEC ; impl crate :: RegisterSpec for WWDTCTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtctl0::R`](R) reader structure"] impl crate :: Readable for WWDTCTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtctl0::W`](W) writer structure"] impl crate :: Writable for WWDTCTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCTL0 to value 0x43"] impl crate :: Resettable for WWDTCTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x43 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/fsub_0.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FSUB_0` reader"] pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"] pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"] FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)] fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W <'_, FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"] impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"] impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"] impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:40733 [INFO] [stdout] | [INFO] [stdout] 1 | ..._imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W <'_, INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/pdbgctl.rs:5:247 [INFO] [stdout] | [INFO] [stdout] 5 | ...se] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft ha... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 5 | is set to 'STOP'"] # [inline (always)] pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"] # [inline (always)] # [must_use] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W <'_, PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/fsub_1.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W < FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FSUB_1` reader"] pub type R = crate :: R < FSUB_1_SPEC > ; # [doc = "Register `FSUB_1` writer"] pub type W = crate :: W < FSUB_1_SPEC > ; # [doc = "Field `FSUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_1_CHANID_R = crate :: FieldReader < FSUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FSUB_1_CHANID_A { # [doc = "0: UNCONNECTED"] FSUB_1_CHANID_UNCONNECTED = 0 , } impl From < FSUB_1_CHANID_A > for u8 { # [inline (always)] fn from (variant : FSUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_1_CHANID_A { type Ux = u8 ; } impl FSUB_1_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FSUB_1_CHANID_A > { match self . bits { 0 => Some (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fsub_1_chanid_unconnected (& self) -> bool { * self == FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fsub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fsub_1_chanid (& self) -> FSUB_1_CHANID_R { FSUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W <'_, FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FSUB_1_SPEC ; impl crate :: RegisterSpec for FSUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_1::R`](R) reader structure"] impl crate :: Readable for FSUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_1::W`](W) writer structure"] impl crate :: Writable for FSUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_1 to value 0"] impl crate :: Resettable for FSUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/fpub_0.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fpub_0_chanid (& mut self) -> FPUB_0_CHANID_W < FPUB_0_SPEC , 0 > { FPUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FPUB_0` reader"] pub type R = crate :: R < FPUB_0_SPEC > ; # [doc = "Register `FPUB_0` writer"] pub type W = crate :: W < FPUB_0_SPEC > ; # [doc = "Field `FPUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_0_CHANID_R = crate :: FieldReader < FPUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FPUB_0_CHANID_A { # [doc = "0: UNCONNECTED"] FPUB_0_CHANID_UNCONNECTED = 0 , } impl From < FPUB_0_CHANID_A > for u8 { # [inline (always)] fn from (variant : FPUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_0_CHANID_A { type Ux = u8 ; } impl FPUB_0_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FPUB_0_CHANID_A > { match self . bits { 0 => Some (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fpub_0_chanid_unconnected (& self) -> bool { * self == FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fpub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fpub_0_chanid (& self) -> FPUB_0_CHANID_R { FPUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fpub_0_chanid (& mut self) -> FPUB_0_CHANID_W <'_, FPUB_0_SPEC , 0 > { FPUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FPUB_0_SPEC ; impl crate :: RegisterSpec for FPUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_0::R`](R) reader structure"] impl crate :: Readable for FPUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_0::W`](W) writer structure"] impl crate :: Writable for FPUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_0 to value 0"] impl crate :: Resettable for FPUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/ctl0.rs:1:36931 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W <'_, CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/pdbgctl.rs:6:74 [INFO] [stdout] | [INFO] [stdout] 6 | ...se] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bi... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 6 | is set to 'STOP'"] # [inline (always)] # [must_use] pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W <'_, PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"] impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"] impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"] impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/fpub_1.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W < FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FPUB_1` reader"] pub type R = crate :: R < FPUB_1_SPEC > ; # [doc = "Register `FPUB_1` writer"] pub type W = crate :: W < FPUB_1_SPEC > ; # [doc = "Field `FPUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_1_CHANID_R = crate :: FieldReader < FPUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FPUB_1_CHANID_A { # [doc = "0: UNCONNECTED"] FPUB_1_CHANID_UNCONNECTED = 0 , } impl From < FPUB_1_CHANID_A > for u8 { # [inline (always)] fn from (variant : FPUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_1_CHANID_A { type Ux = u8 ; } impl FPUB_1_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FPUB_1_CHANID_A > { match self . bits { 0 => Some (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fpub_1_chanid_unconnected (& self) -> bool { * self == FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fpub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fpub_1_chanid (& self) -> FPUB_1_CHANID_R { FPUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W <'_, FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FPUB_1_SPEC ; impl crate :: RegisterSpec for FPUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_1::R`](R) reader structure"] impl crate :: Readable for FPUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_1::W`](W) writer structure"] impl crate :: Writable for FPUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_1 to value 0"] impl crate :: Resettable for FPUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/pwren.rs:1:2941 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W <'_, PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/wwdtctl0.rs:1:23323 [INFO] [stdout] | [INFO] [stdout] 1 | ...se] pub fn wwdtctl0_per (& mut self) -> WWDTCTL0_PER_W < WWDTCTL0_SPEC , 4 > { WWDTCTL0_PER_W :: new (self) } # [doc = "Bits 8:10 - Cl... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `WWDTCTL0` reader"] pub type R = crate :: R < WWDTCTL0_SPEC > ; # [doc = "Register `WWDTCTL0` writer"] pub type W = crate :: W < WWDTCTL0_SPEC > ; # [doc = "Field `WWDTCTL0_CLKDIV` reader - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_R = crate :: FieldReader ; # [doc = "Field `WWDTCTL0_CLKDIV` writer - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `WWDTCTL0_PER` reader - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_R = crate :: FieldReader < WWDTCTL0_PER_A > ; # [doc = "Timer Period of the WWDT. These bits select the total watchdog timer count.\n\nValue on reset: 4"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_PER_A { # [doc = "0: EN_25"] WWDTCTL0_PER_EN_25 = 0 , # [doc = "1: EN_21"] WWDTCTL0_PER_EN_21 = 1 , # [doc = "2: EN_18"] WWDTCTL0_PER_EN_18 = 2 , # [doc = "3: EN_15"] WWDTCTL0_PER_EN_15 = 3 , # [doc = "4: EN_12"] WWDTCTL0_PER_EN_12 = 4 , # [doc = "5: EN_10"] WWDTCTL0_PER_EN_10 = 5 , # [doc = "6: EN_8"] WWDTCTL0_PER_EN_8 = 6 , # [doc = "7: EN_6"] WWDTCTL0_PER_EN_6 = 7 , } impl From < WWDTCTL0_PER_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_PER_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_PER_A { type Ux = u8 ; } impl WWDTCTL0_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_PER_A { match self . bits { 0 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 , 1 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 , 2 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 , 3 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 , 4 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 , 5 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 , 6 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 , 7 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 , _ => unreachable ! () , } } # [doc = "EN_25"] # [inline (always)] pub fn is_wwdtctl0_per_en_25 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 } # [doc = "EN_21"] # [inline (always)] pub fn is_wwdtctl0_per_en_21 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 } # [doc = "EN_18"] # [inline (always)] pub fn is_wwdtctl0_per_en_18 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 } # [doc = "EN_15"] # [inline (always)] pub fn is_wwdtctl0_per_en_15 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 } # [doc = "EN_12"] # [inline (always)] pub fn is_wwdtctl0_per_en_12 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 } # [doc = "EN_10"] # [inline (always)] pub fn is_wwdtctl0_per_en_10 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 } # [doc = "EN_8"] # [inline (always)] pub fn is_wwdtctl0_per_en_8 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 } # [doc = "EN_6"] # [inline (always)] pub fn is_wwdtctl0_per_en_6 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 } } # [doc = "Field `WWDTCTL0_PER` writer - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_PER_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "EN_25"] # [inline (always)] pub fn wwdtctl0_per_en_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25) } # [doc = "EN_21"] # [inline (always)] pub fn wwdtctl0_per_en_21 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21) } # [doc = "EN_18"] # [inline (always)] pub fn wwdtctl0_per_en_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18) } # [doc = "EN_15"] # [inline (always)] pub fn wwdtctl0_per_en_15 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15) } # [doc = "EN_12"] # [inline (always)] pub fn wwdtctl0_per_en_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12) } # [doc = "EN_10"] # [inline (always)] pub fn wwdtctl0_per_en_10 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10) } # [doc = "EN_8"] # [inline (always)] pub fn wwdtctl0_per_en_8 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8) } # [doc = "EN_6"] # [inline (always)] pub fn wwdtctl0_per_en_6 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6) } } # [doc = "Field `WWDTCTL0_WINDOW0` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_R = crate :: FieldReader < WWDTCTL0_WINDOW0_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW0_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW0_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW0_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW0_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW0_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW0_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW0_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW0_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW0_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW0_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW0_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW0_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW0_A { match self . bits { 0 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 , 1 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 , 2 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 , 3 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 , 4 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 , 5 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 , 6 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 , 7 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window0_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window0_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window0_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window0_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window0_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window0_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window0_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window0_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW0` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW0_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window0_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window0_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window0_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window0_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window0_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window0_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window0_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window0_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87) } } # [doc = "Field `WWDTCTL0_WINDOW1` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_R = crate :: FieldReader < WWDTCTL0_WINDOW1_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW1_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW1_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW1_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW1_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW1_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW1_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW1_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW1_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW1_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW1_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW1_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW1_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW1_A { match self . bits { 0 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 , 1 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 , 2 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 , 3 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 , 4 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 , 5 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 , 6 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 , 7 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window1_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window1_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window1_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window1_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window1_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window1_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window1_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window1_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW1` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW1_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window1_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window1_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window1_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window1_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window1_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window1_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window1_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window1_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87) } } # [doc = "Field `WWDTCTL0_MODE` reader - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_R = crate :: BitReader < WWDTCTL0_MODE_A > ; # [doc = "Window Watchdog Timer Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_MODE_A { # [doc = "0: WINDOW"] WWDTCTL0_MODE_WINDOW = 0 , # [doc = "1: INTERVAL"] WWDTCTL0_MODE_INTERVAL = 1 , } impl From < WWDTCTL0_MODE_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_MODE_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_MODE_A { match self . bits { false => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW , true => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL , } } # [doc = "WINDOW"] # [inline (always)] pub fn is_wwdtctl0_mode_window (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW } # [doc = "INTERVAL"] # [inline (always)] pub fn is_wwdtctl0_mode_interval (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL } } # [doc = "Field `WWDTCTL0_MODE` writer - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_MODE_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "WINDOW"] # [inline (always)] pub fn wwdtctl0_mode_window (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW) } # [doc = "INTERVAL"] # [inline (always)] pub fn wwdtctl0_mode_interval (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL) } } # [doc = "Field `WWDTCTL0_STISM` reader - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_R = crate :: BitReader < WWDTCTL0_STISM_A > ; # [doc = "Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_STISM_A { # [doc = "0: CONT"] WWDTCTL0_STISM_CONT = 0 , # [doc = "1: STOP"] WWDTCTL0_STISM_STOP = 1 , } impl From < WWDTCTL0_STISM_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_STISM_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_STISM_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_STISM_A { match self . bits { false => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT , true => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP , } } # [doc = "CONT"] # [inline (always)] pub fn is_wwdtctl0_stism_cont (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT } # [doc = "STOP"] # [inline (always)] pub fn is_wwdtctl0_stism_stop (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP } } # [doc = "Field `WWDTCTL0_STISM` writer - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_STISM_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_STISM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONT"] # [inline (always)] pub fn wwdtctl0_stism_cont (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT) } # [doc = "STOP"] # [inline (always)] pub fn wwdtctl0_stism_stop (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP) } } # [doc = "Field `WWDTCTL0_KEY` reader - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_R = crate :: FieldReader < WWDTCTL0_KEY_A > ; # [doc = "KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_KEY_A { # [doc = "201: _TO_UNLOCK_W_"] WWDTCTL0_KEY_UNLOCK_W = 201 , } impl From < WWDTCTL0_KEY_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_KEY_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_KEY_A { type Ux = u8 ; } impl WWDTCTL0_KEY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < WWDTCTL0_KEY_A > { match self . bits { 201 => Some (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) , _ => None , } } # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn is_wwdtctl0_key_unlock_w (& self) -> bool { * self == WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W } } # [doc = "Field `WWDTCTL0_KEY` writer - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , WWDTCTL0_KEY_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn wwdtctl0_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) } } impl R { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] pub fn wwdtctl0_clkdiv (& self) -> WWDTCTL0_CLKDIV_R { WWDTCTL0_CLKDIV_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] pub fn wwdtctl0_per (& self) -> WWDTCTL0_PER_R { WWDTCTL0_PER_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window0 (& self) -> WWDTCTL0_WINDOW0_R { WWDTCTL0_WINDOW0_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window1 (& self) -> WWDTCTL0_WINDOW1_R { WWDTCTL0_WINDOW1_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] pub fn wwdtctl0_mode (& self) -> WWDTCTL0_MODE_R { WWDTCTL0_MODE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] pub fn wwdtctl0_stism (& self) -> WWDTCTL0_STISM_R { WWDTCTL0_STISM_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] pub fn wwdtctl0_key (& self) -> WWDTCTL0_KEY_R { WWDTCTL0_KEY_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_clkdiv (& mut self) -> WWDTCTL0_CLKDIV_W < WWDTCTL0_SPEC , 0 > { WWDTCTL0_CLKDIV_W :: new (self) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] # [must_use] pub fn wwdtctl0_per (& mut self) -> WWDTCTL0_PER_W <'_, WWDTCTL0_SPEC , 4 > { WWDTCTL0_PER_W :: new (self) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window0 (& mut self) -> WWDTCTL0_WINDOW0_W < WWDTCTL0_SPEC , 8 > { WWDTCTL0_WINDOW0_W :: new (self) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window1 (& mut self) -> WWDTCTL0_WINDOW1_W < WWDTCTL0_SPEC , 12 > { WWDTCTL0_WINDOW1_W :: new (self) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] # [must_use] pub fn wwdtctl0_mode (& mut self) -> WWDTCTL0_MODE_W < WWDTCTL0_SPEC , 16 > { WWDTCTL0_MODE_W :: new (self) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] # [must_use] pub fn wwdtctl0_stism (& mut self) -> WWDTCTL0_STISM_W < WWDTCTL0_SPEC , 17 > { WWDTCTL0_STISM_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_key (& mut self) -> WWDTCTL0_KEY_W < WWDTCTL0_SPEC , 24 > { WWDTCTL0_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WWDTCTL0_SPEC ; impl crate :: RegisterSpec for WWDTCTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtctl0::R`](R) reader structure"] impl crate :: Readable for WWDTCTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtctl0::W`](W) writer structure"] impl crate :: Writable for WWDTCTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCTL0 to value 0x43"] impl crate :: Resettable for WWDTCTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x43 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/ctl0.rs:1:37102 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive E... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W <'_, CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:40969 [INFO] [stdout] | [INFO] [stdout] 1 | ..._imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W <'_, INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:33981 [INFO] [stdout] | [INFO] [stdout] 1 | ...t0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W <'_, INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/wwdtctl0.rs:1:23641 [INFO] [stdout] | [INFO] [stdout] 1 | ...b fn wwdtctl0_window0 (& mut self) -> WWDTCTL0_WINDOW0_W < WWDTCTL0_SPEC , 8 > { WWDTCTL0_WINDOW0_W :: new (self) } # [doc = "Bits 12:... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `WWDTCTL0` reader"] pub type R = crate :: R < WWDTCTL0_SPEC > ; # [doc = "Register `WWDTCTL0` writer"] pub type W = crate :: W < WWDTCTL0_SPEC > ; # [doc = "Field `WWDTCTL0_CLKDIV` reader - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_R = crate :: FieldReader ; # [doc = "Field `WWDTCTL0_CLKDIV` writer - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `WWDTCTL0_PER` reader - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_R = crate :: FieldReader < WWDTCTL0_PER_A > ; # [doc = "Timer Period of the WWDT. These bits select the total watchdog timer count.\n\nValue on reset: 4"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_PER_A { # [doc = "0: EN_25"] WWDTCTL0_PER_EN_25 = 0 , # [doc = "1: EN_21"] WWDTCTL0_PER_EN_21 = 1 , # [doc = "2: EN_18"] WWDTCTL0_PER_EN_18 = 2 , # [doc = "3: EN_15"] WWDTCTL0_PER_EN_15 = 3 , # [doc = "4: EN_12"] WWDTCTL0_PER_EN_12 = 4 , # [doc = "5: EN_10"] WWDTCTL0_PER_EN_10 = 5 , # [doc = "6: EN_8"] WWDTCTL0_PER_EN_8 = 6 , # [doc = "7: EN_6"] WWDTCTL0_PER_EN_6 = 7 , } impl From < WWDTCTL0_PER_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_PER_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_PER_A { type Ux = u8 ; } impl WWDTCTL0_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_PER_A { match self . bits { 0 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 , 1 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 , 2 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 , 3 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 , 4 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 , 5 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 , 6 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 , 7 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 , _ => unreachable ! () , } } # [doc = "EN_25"] # [inline (always)] pub fn is_wwdtctl0_per_en_25 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 } # [doc = "EN_21"] # [inline (always)] pub fn is_wwdtctl0_per_en_21 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 } # [doc = "EN_18"] # [inline (always)] pub fn is_wwdtctl0_per_en_18 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 } # [doc = "EN_15"] # [inline (always)] pub fn is_wwdtctl0_per_en_15 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 } # [doc = "EN_12"] # [inline (always)] pub fn is_wwdtctl0_per_en_12 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 } # [doc = "EN_10"] # [inline (always)] pub fn is_wwdtctl0_per_en_10 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 } # [doc = "EN_8"] # [inline (always)] pub fn is_wwdtctl0_per_en_8 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 } # [doc = "EN_6"] # [inline (always)] pub fn is_wwdtctl0_per_en_6 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 } } # [doc = "Field `WWDTCTL0_PER` writer - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_PER_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "EN_25"] # [inline (always)] pub fn wwdtctl0_per_en_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25) } # [doc = "EN_21"] # [inline (always)] pub fn wwdtctl0_per_en_21 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21) } # [doc = "EN_18"] # [inline (always)] pub fn wwdtctl0_per_en_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18) } # [doc = "EN_15"] # [inline (always)] pub fn wwdtctl0_per_en_15 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15) } # [doc = "EN_12"] # [inline (always)] pub fn wwdtctl0_per_en_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12) } # [doc = "EN_10"] # [inline (always)] pub fn wwdtctl0_per_en_10 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10) } # [doc = "EN_8"] # [inline (always)] pub fn wwdtctl0_per_en_8 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8) } # [doc = "EN_6"] # [inline (always)] pub fn wwdtctl0_per_en_6 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6) } } # [doc = "Field `WWDTCTL0_WINDOW0` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_R = crate :: FieldReader < WWDTCTL0_WINDOW0_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW0_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW0_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW0_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW0_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW0_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW0_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW0_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW0_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW0_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW0_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW0_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW0_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW0_A { match self . bits { 0 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 , 1 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 , 2 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 , 3 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 , 4 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 , 5 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 , 6 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 , 7 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window0_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window0_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window0_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window0_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window0_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window0_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window0_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window0_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW0` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW0_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window0_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window0_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window0_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window0_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window0_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window0_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window0_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window0_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87) } } # [doc = "Field `WWDTCTL0_WINDOW1` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_R = crate :: FieldReader < WWDTCTL0_WINDOW1_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW1_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW1_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW1_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW1_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW1_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW1_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW1_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW1_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW1_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW1_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW1_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW1_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW1_A { match self . bits { 0 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 , 1 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 , 2 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 , 3 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 , 4 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 , 5 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 , 6 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 , 7 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window1_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window1_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window1_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window1_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window1_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window1_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window1_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window1_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW1` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW1_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window1_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window1_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window1_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window1_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window1_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window1_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window1_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window1_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87) } } # [doc = "Field `WWDTCTL0_MODE` reader - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_R = crate :: BitReader < WWDTCTL0_MODE_A > ; # [doc = "Window Watchdog Timer Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_MODE_A { # [doc = "0: WINDOW"] WWDTCTL0_MODE_WINDOW = 0 , # [doc = "1: INTERVAL"] WWDTCTL0_MODE_INTERVAL = 1 , } impl From < WWDTCTL0_MODE_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_MODE_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_MODE_A { match self . bits { false => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW , true => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL , } } # [doc = "WINDOW"] # [inline (always)] pub fn is_wwdtctl0_mode_window (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW } # [doc = "INTERVAL"] # [inline (always)] pub fn is_wwdtctl0_mode_interval (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL } } # [doc = "Field `WWDTCTL0_MODE` writer - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_MODE_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "WINDOW"] # [inline (always)] pub fn wwdtctl0_mode_window (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW) } # [doc = "INTERVAL"] # [inline (always)] pub fn wwdtctl0_mode_interval (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL) } } # [doc = "Field `WWDTCTL0_STISM` reader - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_R = crate :: BitReader < WWDTCTL0_STISM_A > ; # [doc = "Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_STISM_A { # [doc = "0: CONT"] WWDTCTL0_STISM_CONT = 0 , # [doc = "1: STOP"] WWDTCTL0_STISM_STOP = 1 , } impl From < WWDTCTL0_STISM_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_STISM_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_STISM_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_STISM_A { match self . bits { false => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT , true => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP , } } # [doc = "CONT"] # [inline (always)] pub fn is_wwdtctl0_stism_cont (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT } # [doc = "STOP"] # [inline (always)] pub fn is_wwdtctl0_stism_stop (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP } } # [doc = "Field `WWDTCTL0_STISM` writer - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_STISM_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_STISM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONT"] # [inline (always)] pub fn wwdtctl0_stism_cont (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT) } # [doc = "STOP"] # [inline (always)] pub fn wwdtctl0_stism_stop (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP) } } # [doc = "Field `WWDTCTL0_KEY` reader - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_R = crate :: FieldReader < WWDTCTL0_KEY_A > ; # [doc = "KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_KEY_A { # [doc = "201: _TO_UNLOCK_W_"] WWDTCTL0_KEY_UNLOCK_W = 201 , } impl From < WWDTCTL0_KEY_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_KEY_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_KEY_A { type Ux = u8 ; } impl WWDTCTL0_KEY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < WWDTCTL0_KEY_A > { match self . bits { 201 => Some (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) , _ => None , } } # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn is_wwdtctl0_key_unlock_w (& self) -> bool { * self == WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W } } # [doc = "Field `WWDTCTL0_KEY` writer - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , WWDTCTL0_KEY_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn wwdtctl0_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) } } impl R { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] pub fn wwdtctl0_clkdiv (& self) -> WWDTCTL0_CLKDIV_R { WWDTCTL0_CLKDIV_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] pub fn wwdtctl0_per (& self) -> WWDTCTL0_PER_R { WWDTCTL0_PER_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window0 (& self) -> WWDTCTL0_WINDOW0_R { WWDTCTL0_WINDOW0_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window1 (& self) -> WWDTCTL0_WINDOW1_R { WWDTCTL0_WINDOW1_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] pub fn wwdtctl0_mode (& self) -> WWDTCTL0_MODE_R { WWDTCTL0_MODE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] pub fn wwdtctl0_stism (& self) -> WWDTCTL0_STISM_R { WWDTCTL0_STISM_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] pub fn wwdtctl0_key (& self) -> WWDTCTL0_KEY_R { WWDTCTL0_KEY_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_clkdiv (& mut self) -> WWDTCTL0_CLKDIV_W < WWDTCTL0_SPEC , 0 > { WWDTCTL0_CLKDIV_W :: new (self) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] # [must_use] pub fn wwdtctl0_per (& mut self) -> WWDTCTL0_PER_W < WWDTCTL0_SPEC , 4 > { WWDTCTL0_PER_W :: new (self) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window0 (& mut self) -> WWDTCTL0_WINDOW0_W <'_, WWDTCTL0_SPEC , 8 > { WWDTCTL0_WINDOW0_W :: new (self) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window1 (& mut self) -> WWDTCTL0_WINDOW1_W < WWDTCTL0_SPEC , 12 > { WWDTCTL0_WINDOW1_W :: new (self) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] # [must_use] pub fn wwdtctl0_mode (& mut self) -> WWDTCTL0_MODE_W < WWDTCTL0_SPEC , 16 > { WWDTCTL0_MODE_W :: new (self) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] # [must_use] pub fn wwdtctl0_stism (& mut self) -> WWDTCTL0_STISM_W < WWDTCTL0_SPEC , 17 > { WWDTCTL0_STISM_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_key (& mut self) -> WWDTCTL0_KEY_W < WWDTCTL0_SPEC , 24 > { WWDTCTL0_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WWDTCTL0_SPEC ; impl crate :: RegisterSpec for WWDTCTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtctl0::R`](R) reader structure"] impl crate :: Readable for WWDTCTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtctl0::W`](W) writer structure"] impl crate :: Writable for WWDTCTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCTL0 to value 0x43"] impl crate :: Resettable for WWDTCTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x43 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:41204 [INFO] [stdout] | [INFO] [stdout] 1 | ..._imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W <'_, INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/pwren.rs:1:3131 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W <'_, PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/opa0/cfg.rs:1:17669 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to t... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFG` reader"] pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"] pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."] pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_CHOP_A { # [doc = "0: OFF"] CFG_CHOP_OFF = 0 , # [doc = "1: ON"] CFG_CHOP_ON = 1 , # [doc = "2: AVGON"] CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)] fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"] # [inline (always)] pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"] # [inline (always)] pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"] # [inline (always)] pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."] pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"] # [inline (always)] pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"] # [inline (always)] pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"] # [inline (always)] pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"] pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"] CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"] CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)] fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"] pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_PSEL_A { # [doc = "0: NC"] CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"] CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"] CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"] CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"] CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"] CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"] CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"] # [inline (always)] pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"] # [inline (always)] pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"] # [inline (always)] pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"] # [inline (always)] pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"] # [inline (always)] pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"] # [inline (always)] pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_NSEL_A { # [doc = "0: NC"] CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"] CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"] CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"] CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"] CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"] CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"] CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"] # [inline (always)] pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"] # [inline (always)] pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"] # [inline (always)] pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"] # [inline (always)] pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"] # [inline (always)] pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"] # [inline (always)] pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"] # [inline (always)] pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"] # [inline (always)] pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"] # [inline (always)] pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"] # [inline (always)] pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"] # [inline (always)] pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"] # [inline (always)] pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CFG_MSEL_A { # [doc = "0: NC"] CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"] CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"] CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"] CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"] CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)] fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"] # [inline (always)] pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"] # [inline (always)] pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"] # [inline (always)] pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"] # [inline (always)] pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"] # [inline (always)] pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"] # [inline (always)] pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"] # [inline (always)] pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"] # [inline (always)] pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"] # [inline (always)] pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"] # [inline (always)] pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."] pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."] # [inline (always)] # [must_use] pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"] # [inline (always)] # [must_use] pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."] # [inline (always)] # [must_use] pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."] # [inline (always)] # [must_use] pub fn cfg_gain (& mut self) -> CFG_GAIN_W <'_, CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"] impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"] impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:34216 [INFO] [stdout] | [INFO] [stdout] 1 | ..._imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W <'_, INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/wwdtctl0.rs:1:23968 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn wwdtctl0_window1 (& mut self) -> WWDTCTL0_WINDOW1_W < WWDTCTL0_SPEC , 12 > { WWDTCTL0_WINDOW1_W :: new (self) } # [doc = "Bit 16 -... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `WWDTCTL0` reader"] pub type R = crate :: R < WWDTCTL0_SPEC > ; # [doc = "Register `WWDTCTL0` writer"] pub type W = crate :: W < WWDTCTL0_SPEC > ; # [doc = "Field `WWDTCTL0_CLKDIV` reader - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_R = crate :: FieldReader ; # [doc = "Field `WWDTCTL0_CLKDIV` writer - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `WWDTCTL0_PER` reader - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_R = crate :: FieldReader < WWDTCTL0_PER_A > ; # [doc = "Timer Period of the WWDT. These bits select the total watchdog timer count.\n\nValue on reset: 4"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_PER_A { # [doc = "0: EN_25"] WWDTCTL0_PER_EN_25 = 0 , # [doc = "1: EN_21"] WWDTCTL0_PER_EN_21 = 1 , # [doc = "2: EN_18"] WWDTCTL0_PER_EN_18 = 2 , # [doc = "3: EN_15"] WWDTCTL0_PER_EN_15 = 3 , # [doc = "4: EN_12"] WWDTCTL0_PER_EN_12 = 4 , # [doc = "5: EN_10"] WWDTCTL0_PER_EN_10 = 5 , # [doc = "6: EN_8"] WWDTCTL0_PER_EN_8 = 6 , # [doc = "7: EN_6"] WWDTCTL0_PER_EN_6 = 7 , } impl From < WWDTCTL0_PER_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_PER_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_PER_A { type Ux = u8 ; } impl WWDTCTL0_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_PER_A { match self . bits { 0 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 , 1 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 , 2 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 , 3 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 , 4 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 , 5 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 , 6 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 , 7 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 , _ => unreachable ! () , } } # [doc = "EN_25"] # [inline (always)] pub fn is_wwdtctl0_per_en_25 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 } # [doc = "EN_21"] # [inline (always)] pub fn is_wwdtctl0_per_en_21 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 } # [doc = "EN_18"] # [inline (always)] pub fn is_wwdtctl0_per_en_18 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 } # [doc = "EN_15"] # [inline (always)] pub fn is_wwdtctl0_per_en_15 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 } # [doc = "EN_12"] # [inline (always)] pub fn is_wwdtctl0_per_en_12 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 } # [doc = "EN_10"] # [inline (always)] pub fn is_wwdtctl0_per_en_10 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 } # [doc = "EN_8"] # [inline (always)] pub fn is_wwdtctl0_per_en_8 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 } # [doc = "EN_6"] # [inline (always)] pub fn is_wwdtctl0_per_en_6 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 } } # [doc = "Field `WWDTCTL0_PER` writer - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_PER_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "EN_25"] # [inline (always)] pub fn wwdtctl0_per_en_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25) } # [doc = "EN_21"] # [inline (always)] pub fn wwdtctl0_per_en_21 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21) } # [doc = "EN_18"] # [inline (always)] pub fn wwdtctl0_per_en_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18) } # [doc = "EN_15"] # [inline (always)] pub fn wwdtctl0_per_en_15 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15) } # [doc = "EN_12"] # [inline (always)] pub fn wwdtctl0_per_en_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12) } # [doc = "EN_10"] # [inline (always)] pub fn wwdtctl0_per_en_10 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10) } # [doc = "EN_8"] # [inline (always)] pub fn wwdtctl0_per_en_8 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8) } # [doc = "EN_6"] # [inline (always)] pub fn wwdtctl0_per_en_6 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6) } } # [doc = "Field `WWDTCTL0_WINDOW0` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_R = crate :: FieldReader < WWDTCTL0_WINDOW0_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW0_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW0_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW0_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW0_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW0_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW0_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW0_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW0_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW0_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW0_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW0_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW0_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW0_A { match self . bits { 0 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 , 1 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 , 2 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 , 3 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 , 4 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 , 5 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 , 6 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 , 7 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window0_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window0_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window0_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window0_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window0_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window0_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window0_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window0_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW0` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW0_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window0_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window0_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window0_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window0_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window0_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window0_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window0_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window0_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87) } } # [doc = "Field `WWDTCTL0_WINDOW1` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_R = crate :: FieldReader < WWDTCTL0_WINDOW1_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW1_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW1_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW1_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW1_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW1_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW1_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW1_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW1_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW1_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW1_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW1_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW1_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW1_A { match self . bits { 0 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 , 1 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 , 2 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 , 3 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 , 4 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 , 5 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 , 6 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 , 7 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window1_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window1_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window1_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window1_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window1_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window1_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window1_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window1_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW1` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW1_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window1_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window1_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window1_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window1_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window1_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window1_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window1_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window1_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87) } } # [doc = "Field `WWDTCTL0_MODE` reader - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_R = crate :: BitReader < WWDTCTL0_MODE_A > ; # [doc = "Window Watchdog Timer Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_MODE_A { # [doc = "0: WINDOW"] WWDTCTL0_MODE_WINDOW = 0 , # [doc = "1: INTERVAL"] WWDTCTL0_MODE_INTERVAL = 1 , } impl From < WWDTCTL0_MODE_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_MODE_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_MODE_A { match self . bits { false => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW , true => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL , } } # [doc = "WINDOW"] # [inline (always)] pub fn is_wwdtctl0_mode_window (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW } # [doc = "INTERVAL"] # [inline (always)] pub fn is_wwdtctl0_mode_interval (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL } } # [doc = "Field `WWDTCTL0_MODE` writer - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_MODE_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "WINDOW"] # [inline (always)] pub fn wwdtctl0_mode_window (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW) } # [doc = "INTERVAL"] # [inline (always)] pub fn wwdtctl0_mode_interval (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL) } } # [doc = "Field `WWDTCTL0_STISM` reader - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_R = crate :: BitReader < WWDTCTL0_STISM_A > ; # [doc = "Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_STISM_A { # [doc = "0: CONT"] WWDTCTL0_STISM_CONT = 0 , # [doc = "1: STOP"] WWDTCTL0_STISM_STOP = 1 , } impl From < WWDTCTL0_STISM_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_STISM_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_STISM_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_STISM_A { match self . bits { false => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT , true => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP , } } # [doc = "CONT"] # [inline (always)] pub fn is_wwdtctl0_stism_cont (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT } # [doc = "STOP"] # [inline (always)] pub fn is_wwdtctl0_stism_stop (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP } } # [doc = "Field `WWDTCTL0_STISM` writer - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_STISM_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_STISM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONT"] # [inline (always)] pub fn wwdtctl0_stism_cont (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT) } # [doc = "STOP"] # [inline (always)] pub fn wwdtctl0_stism_stop (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP) } } # [doc = "Field `WWDTCTL0_KEY` reader - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_R = crate :: FieldReader < WWDTCTL0_KEY_A > ; # [doc = "KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_KEY_A { # [doc = "201: _TO_UNLOCK_W_"] WWDTCTL0_KEY_UNLOCK_W = 201 , } impl From < WWDTCTL0_KEY_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_KEY_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_KEY_A { type Ux = u8 ; } impl WWDTCTL0_KEY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < WWDTCTL0_KEY_A > { match self . bits { 201 => Some (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) , _ => None , } } # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn is_wwdtctl0_key_unlock_w (& self) -> bool { * self == WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W } } # [doc = "Field `WWDTCTL0_KEY` writer - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , WWDTCTL0_KEY_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn wwdtctl0_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) } } impl R { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] pub fn wwdtctl0_clkdiv (& self) -> WWDTCTL0_CLKDIV_R { WWDTCTL0_CLKDIV_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] pub fn wwdtctl0_per (& self) -> WWDTCTL0_PER_R { WWDTCTL0_PER_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window0 (& self) -> WWDTCTL0_WINDOW0_R { WWDTCTL0_WINDOW0_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window1 (& self) -> WWDTCTL0_WINDOW1_R { WWDTCTL0_WINDOW1_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] pub fn wwdtctl0_mode (& self) -> WWDTCTL0_MODE_R { WWDTCTL0_MODE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] pub fn wwdtctl0_stism (& self) -> WWDTCTL0_STISM_R { WWDTCTL0_STISM_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] pub fn wwdtctl0_key (& self) -> WWDTCTL0_KEY_R { WWDTCTL0_KEY_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_clkdiv (& mut self) -> WWDTCTL0_CLKDIV_W < WWDTCTL0_SPEC , 0 > { WWDTCTL0_CLKDIV_W :: new (self) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] # [must_use] pub fn wwdtctl0_per (& mut self) -> WWDTCTL0_PER_W < WWDTCTL0_SPEC , 4 > { WWDTCTL0_PER_W :: new (self) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window0 (& mut self) -> WWDTCTL0_WINDOW0_W < WWDTCTL0_SPEC , 8 > { WWDTCTL0_WINDOW0_W :: new (self) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window1 (& mut self) -> WWDTCTL0_WINDOW1_W <'_, WWDTCTL0_SPEC , 12 > { WWDTCTL0_WINDOW1_W :: new (self) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] # [must_use] pub fn wwdtctl0_mode (& mut self) -> WWDTCTL0_MODE_W < WWDTCTL0_SPEC , 16 > { WWDTCTL0_MODE_W :: new (self) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] # [must_use] pub fn wwdtctl0_stism (& mut self) -> WWDTCTL0_STISM_W < WWDTCTL0_SPEC , 17 > { WWDTCTL0_STISM_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_key (& mut self) -> WWDTCTL0_KEY_W < WWDTCTL0_SPEC , 24 > { WWDTCTL0_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WWDTCTL0_SPEC ; impl crate :: RegisterSpec for WWDTCTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtctl0::R`](R) reader structure"] impl crate :: Readable for WWDTCTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtctl0::W`](W) writer structure"] impl crate :: Writable for WWDTCTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCTL0 to value 0x43"] impl crate :: Resettable for WWDTCTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x43 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:41449 [INFO] [stdout] | [INFO] [stdout] 1 | ..._imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W <'_, INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:34452 [INFO] [stdout] | [INFO] [stdout] 1 | ..._imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W <'_, INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/rstctl.rs:1:3243 [INFO] [stdout] | [INFO] [stdout] 1 | ...fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W <'_, RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/wwdtctl0.rs:1:24165 [INFO] [stdout] | [INFO] [stdout] 1 | ...] pub fn wwdtctl0_mode (& mut self) -> WWDTCTL0_MODE_W < WWDTCTL0_SPEC , 16 > { WWDTCTL0_MODE_W :: new (self) } # [doc = "Bit 17 - Sto... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `WWDTCTL0` reader"] pub type R = crate :: R < WWDTCTL0_SPEC > ; # [doc = "Register `WWDTCTL0` writer"] pub type W = crate :: W < WWDTCTL0_SPEC > ; # [doc = "Field `WWDTCTL0_CLKDIV` reader - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_R = crate :: FieldReader ; # [doc = "Field `WWDTCTL0_CLKDIV` writer - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `WWDTCTL0_PER` reader - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_R = crate :: FieldReader < WWDTCTL0_PER_A > ; # [doc = "Timer Period of the WWDT. These bits select the total watchdog timer count.\n\nValue on reset: 4"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_PER_A { # [doc = "0: EN_25"] WWDTCTL0_PER_EN_25 = 0 , # [doc = "1: EN_21"] WWDTCTL0_PER_EN_21 = 1 , # [doc = "2: EN_18"] WWDTCTL0_PER_EN_18 = 2 , # [doc = "3: EN_15"] WWDTCTL0_PER_EN_15 = 3 , # [doc = "4: EN_12"] WWDTCTL0_PER_EN_12 = 4 , # [doc = "5: EN_10"] WWDTCTL0_PER_EN_10 = 5 , # [doc = "6: EN_8"] WWDTCTL0_PER_EN_8 = 6 , # [doc = "7: EN_6"] WWDTCTL0_PER_EN_6 = 7 , } impl From < WWDTCTL0_PER_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_PER_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_PER_A { type Ux = u8 ; } impl WWDTCTL0_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_PER_A { match self . bits { 0 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 , 1 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 , 2 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 , 3 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 , 4 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 , 5 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 , 6 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 , 7 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 , _ => unreachable ! () , } } # [doc = "EN_25"] # [inline (always)] pub fn is_wwdtctl0_per_en_25 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 } # [doc = "EN_21"] # [inline (always)] pub fn is_wwdtctl0_per_en_21 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 } # [doc = "EN_18"] # [inline (always)] pub fn is_wwdtctl0_per_en_18 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 } # [doc = "EN_15"] # [inline (always)] pub fn is_wwdtctl0_per_en_15 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 } # [doc = "EN_12"] # [inline (always)] pub fn is_wwdtctl0_per_en_12 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 } # [doc = "EN_10"] # [inline (always)] pub fn is_wwdtctl0_per_en_10 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 } # [doc = "EN_8"] # [inline (always)] pub fn is_wwdtctl0_per_en_8 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 } # [doc = "EN_6"] # [inline (always)] pub fn is_wwdtctl0_per_en_6 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 } } # [doc = "Field `WWDTCTL0_PER` writer - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_PER_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "EN_25"] # [inline (always)] pub fn wwdtctl0_per_en_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25) } # [doc = "EN_21"] # [inline (always)] pub fn wwdtctl0_per_en_21 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21) } # [doc = "EN_18"] # [inline (always)] pub fn wwdtctl0_per_en_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18) } # [doc = "EN_15"] # [inline (always)] pub fn wwdtctl0_per_en_15 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15) } # [doc = "EN_12"] # [inline (always)] pub fn wwdtctl0_per_en_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12) } # [doc = "EN_10"] # [inline (always)] pub fn wwdtctl0_per_en_10 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10) } # [doc = "EN_8"] # [inline (always)] pub fn wwdtctl0_per_en_8 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8) } # [doc = "EN_6"] # [inline (always)] pub fn wwdtctl0_per_en_6 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6) } } # [doc = "Field `WWDTCTL0_WINDOW0` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_R = crate :: FieldReader < WWDTCTL0_WINDOW0_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW0_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW0_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW0_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW0_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW0_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW0_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW0_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW0_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW0_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW0_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW0_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW0_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW0_A { match self . bits { 0 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 , 1 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 , 2 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 , 3 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 , 4 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 , 5 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 , 6 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 , 7 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window0_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window0_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window0_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window0_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window0_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window0_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window0_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window0_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW0` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW0_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window0_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window0_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window0_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window0_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window0_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window0_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window0_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window0_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87) } } # [doc = "Field `WWDTCTL0_WINDOW1` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_R = crate :: FieldReader < WWDTCTL0_WINDOW1_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW1_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW1_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW1_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW1_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW1_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW1_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW1_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW1_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW1_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW1_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW1_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW1_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW1_A { match self . bits { 0 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 , 1 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 , 2 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 , 3 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 , 4 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 , 5 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 , 6 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 , 7 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window1_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window1_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window1_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window1_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window1_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window1_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window1_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window1_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW1` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW1_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window1_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window1_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window1_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window1_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window1_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window1_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window1_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window1_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87) } } # [doc = "Field `WWDTCTL0_MODE` reader - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_R = crate :: BitReader < WWDTCTL0_MODE_A > ; # [doc = "Window Watchdog Timer Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_MODE_A { # [doc = "0: WINDOW"] WWDTCTL0_MODE_WINDOW = 0 , # [doc = "1: INTERVAL"] WWDTCTL0_MODE_INTERVAL = 1 , } impl From < WWDTCTL0_MODE_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_MODE_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_MODE_A { match self . bits { false => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW , true => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL , } } # [doc = "WINDOW"] # [inline (always)] pub fn is_wwdtctl0_mode_window (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW } # [doc = "INTERVAL"] # [inline (always)] pub fn is_wwdtctl0_mode_interval (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL } } # [doc = "Field `WWDTCTL0_MODE` writer - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_MODE_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "WINDOW"] # [inline (always)] pub fn wwdtctl0_mode_window (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW) } # [doc = "INTERVAL"] # [inline (always)] pub fn wwdtctl0_mode_interval (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL) } } # [doc = "Field `WWDTCTL0_STISM` reader - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_R = crate :: BitReader < WWDTCTL0_STISM_A > ; # [doc = "Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_STISM_A { # [doc = "0: CONT"] WWDTCTL0_STISM_CONT = 0 , # [doc = "1: STOP"] WWDTCTL0_STISM_STOP = 1 , } impl From < WWDTCTL0_STISM_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_STISM_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_STISM_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_STISM_A { match self . bits { false => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT , true => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP , } } # [doc = "CONT"] # [inline (always)] pub fn is_wwdtctl0_stism_cont (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT } # [doc = "STOP"] # [inline (always)] pub fn is_wwdtctl0_stism_stop (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP } } # [doc = "Field `WWDTCTL0_STISM` writer - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_STISM_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_STISM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONT"] # [inline (always)] pub fn wwdtctl0_stism_cont (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT) } # [doc = "STOP"] # [inline (always)] pub fn wwdtctl0_stism_stop (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP) } } # [doc = "Field `WWDTCTL0_KEY` reader - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_R = crate :: FieldReader < WWDTCTL0_KEY_A > ; # [doc = "KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_KEY_A { # [doc = "201: _TO_UNLOCK_W_"] WWDTCTL0_KEY_UNLOCK_W = 201 , } impl From < WWDTCTL0_KEY_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_KEY_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_KEY_A { type Ux = u8 ; } impl WWDTCTL0_KEY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < WWDTCTL0_KEY_A > { match self . bits { 201 => Some (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) , _ => None , } } # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn is_wwdtctl0_key_unlock_w (& self) -> bool { * self == WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W } } # [doc = "Field `WWDTCTL0_KEY` writer - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , WWDTCTL0_KEY_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn wwdtctl0_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) } } impl R { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] pub fn wwdtctl0_clkdiv (& self) -> WWDTCTL0_CLKDIV_R { WWDTCTL0_CLKDIV_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] pub fn wwdtctl0_per (& self) -> WWDTCTL0_PER_R { WWDTCTL0_PER_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window0 (& self) -> WWDTCTL0_WINDOW0_R { WWDTCTL0_WINDOW0_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window1 (& self) -> WWDTCTL0_WINDOW1_R { WWDTCTL0_WINDOW1_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] pub fn wwdtctl0_mode (& self) -> WWDTCTL0_MODE_R { WWDTCTL0_MODE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] pub fn wwdtctl0_stism (& self) -> WWDTCTL0_STISM_R { WWDTCTL0_STISM_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] pub fn wwdtctl0_key (& self) -> WWDTCTL0_KEY_R { WWDTCTL0_KEY_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_clkdiv (& mut self) -> WWDTCTL0_CLKDIV_W < WWDTCTL0_SPEC , 0 > { WWDTCTL0_CLKDIV_W :: new (self) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] # [must_use] pub fn wwdtctl0_per (& mut self) -> WWDTCTL0_PER_W < WWDTCTL0_SPEC , 4 > { WWDTCTL0_PER_W :: new (self) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window0 (& mut self) -> WWDTCTL0_WINDOW0_W < WWDTCTL0_SPEC , 8 > { WWDTCTL0_WINDOW0_W :: new (self) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window1 (& mut self) -> WWDTCTL0_WINDOW1_W < WWDTCTL0_SPEC , 12 > { WWDTCTL0_WINDOW1_W :: new (self) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] # [must_use] pub fn wwdtctl0_mode (& mut self) -> WWDTCTL0_MODE_W <'_, WWDTCTL0_SPEC , 16 > { WWDTCTL0_MODE_W :: new (self) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] # [must_use] pub fn wwdtctl0_stism (& mut self) -> WWDTCTL0_STISM_W < WWDTCTL0_SPEC , 17 > { WWDTCTL0_STISM_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_key (& mut self) -> WWDTCTL0_KEY_W < WWDTCTL0_SPEC , 24 > { WWDTCTL0_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WWDTCTL0_SPEC ; impl crate :: RegisterSpec for WWDTCTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtctl0::R`](R) reader structure"] impl crate :: Readable for WWDTCTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtctl0::W`](W) writer structure"] impl crate :: Writable for WWDTCTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCTL0 to value 0x43"] impl crate :: Resettable for WWDTCTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x43 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/ctl0.rs:1:37431 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W <'_, CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg1/fsub_0.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FSUB_0` reader"] pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"] pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"] FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)] fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W <'_, FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"] impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"] impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"] impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg1/fsub_1.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W < FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FSUB_1` reader"] pub type R = crate :: R < FSUB_1_SPEC > ; # [doc = "Register `FSUB_1` writer"] pub type W = crate :: W < FSUB_1_SPEC > ; # [doc = "Field `FSUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_1_CHANID_R = crate :: FieldReader < FSUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FSUB_1_CHANID_A { # [doc = "0: UNCONNECTED"] FSUB_1_CHANID_UNCONNECTED = 0 , } impl From < FSUB_1_CHANID_A > for u8 { # [inline (always)] fn from (variant : FSUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_1_CHANID_A { type Ux = u8 ; } impl FSUB_1_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FSUB_1_CHANID_A > { match self . bits { 0 => Some (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fsub_1_chanid_unconnected (& self) -> bool { * self == FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FSUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fsub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fsub_1_chanid (& self) -> FSUB_1_CHANID_R { FSUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W <'_, FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FSUB_1_SPEC ; impl crate :: RegisterSpec for FSUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_1::R`](R) reader structure"] impl crate :: Readable for FSUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_1::W`](W) writer structure"] impl crate :: Writable for FSUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_1 to value 0"] impl crate :: Resettable for FSUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/wwdtctl0.rs:1:24581 [INFO] [stdout] | [INFO] [stdout] 1 | ...pub fn wwdtctl0_stism (& mut self) -> WWDTCTL0_STISM_W < WWDTCTL0_SPEC , 17 > { WWDTCTL0_STISM_W :: new (self) } # [doc = "Bits 24:31 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `WWDTCTL0` reader"] pub type R = crate :: R < WWDTCTL0_SPEC > ; # [doc = "Register `WWDTCTL0` writer"] pub type W = crate :: W < WWDTCTL0_SPEC > ; # [doc = "Field `WWDTCTL0_CLKDIV` reader - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_R = crate :: FieldReader ; # [doc = "Field `WWDTCTL0_CLKDIV` writer - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `WWDTCTL0_PER` reader - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_R = crate :: FieldReader < WWDTCTL0_PER_A > ; # [doc = "Timer Period of the WWDT. These bits select the total watchdog timer count.\n\nValue on reset: 4"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_PER_A { # [doc = "0: EN_25"] WWDTCTL0_PER_EN_25 = 0 , # [doc = "1: EN_21"] WWDTCTL0_PER_EN_21 = 1 , # [doc = "2: EN_18"] WWDTCTL0_PER_EN_18 = 2 , # [doc = "3: EN_15"] WWDTCTL0_PER_EN_15 = 3 , # [doc = "4: EN_12"] WWDTCTL0_PER_EN_12 = 4 , # [doc = "5: EN_10"] WWDTCTL0_PER_EN_10 = 5 , # [doc = "6: EN_8"] WWDTCTL0_PER_EN_8 = 6 , # [doc = "7: EN_6"] WWDTCTL0_PER_EN_6 = 7 , } impl From < WWDTCTL0_PER_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_PER_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_PER_A { type Ux = u8 ; } impl WWDTCTL0_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_PER_A { match self . bits { 0 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 , 1 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 , 2 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 , 3 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 , 4 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 , 5 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 , 6 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 , 7 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 , _ => unreachable ! () , } } # [doc = "EN_25"] # [inline (always)] pub fn is_wwdtctl0_per_en_25 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 } # [doc = "EN_21"] # [inline (always)] pub fn is_wwdtctl0_per_en_21 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 } # [doc = "EN_18"] # [inline (always)] pub fn is_wwdtctl0_per_en_18 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 } # [doc = "EN_15"] # [inline (always)] pub fn is_wwdtctl0_per_en_15 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 } # [doc = "EN_12"] # [inline (always)] pub fn is_wwdtctl0_per_en_12 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 } # [doc = "EN_10"] # [inline (always)] pub fn is_wwdtctl0_per_en_10 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 } # [doc = "EN_8"] # [inline (always)] pub fn is_wwdtctl0_per_en_8 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 } # [doc = "EN_6"] # [inline (always)] pub fn is_wwdtctl0_per_en_6 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 } } # [doc = "Field `WWDTCTL0_PER` writer - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_PER_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "EN_25"] # [inline (always)] pub fn wwdtctl0_per_en_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25) } # [doc = "EN_21"] # [inline (always)] pub fn wwdtctl0_per_en_21 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21) } # [doc = "EN_18"] # [inline (always)] pub fn wwdtctl0_per_en_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18) } # [doc = "EN_15"] # [inline (always)] pub fn wwdtctl0_per_en_15 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15) } # [doc = "EN_12"] # [inline (always)] pub fn wwdtctl0_per_en_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12) } # [doc = "EN_10"] # [inline (always)] pub fn wwdtctl0_per_en_10 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10) } # [doc = "EN_8"] # [inline (always)] pub fn wwdtctl0_per_en_8 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8) } # [doc = "EN_6"] # [inline (always)] pub fn wwdtctl0_per_en_6 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6) } } # [doc = "Field `WWDTCTL0_WINDOW0` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_R = crate :: FieldReader < WWDTCTL0_WINDOW0_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW0_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW0_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW0_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW0_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW0_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW0_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW0_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW0_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW0_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW0_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW0_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW0_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW0_A { match self . bits { 0 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 , 1 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 , 2 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 , 3 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 , 4 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 , 5 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 , 6 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 , 7 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window0_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window0_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window0_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window0_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window0_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window0_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window0_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window0_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW0` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW0_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window0_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window0_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window0_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window0_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window0_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window0_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window0_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window0_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87) } } # [doc = "Field `WWDTCTL0_WINDOW1` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_R = crate :: FieldReader < WWDTCTL0_WINDOW1_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW1_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW1_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW1_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW1_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW1_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW1_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW1_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW1_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW1_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW1_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW1_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW1_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW1_A { match self . bits { 0 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 , 1 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 , 2 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 , 3 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 , 4 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 , 5 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 , 6 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 , 7 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window1_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window1_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window1_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window1_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window1_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window1_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window1_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window1_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW1` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW1_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window1_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window1_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window1_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window1_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window1_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window1_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window1_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window1_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87) } } # [doc = "Field `WWDTCTL0_MODE` reader - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_R = crate :: BitReader < WWDTCTL0_MODE_A > ; # [doc = "Window Watchdog Timer Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_MODE_A { # [doc = "0: WINDOW"] WWDTCTL0_MODE_WINDOW = 0 , # [doc = "1: INTERVAL"] WWDTCTL0_MODE_INTERVAL = 1 , } impl From < WWDTCTL0_MODE_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_MODE_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_MODE_A { match self . bits { false => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW , true => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL , } } # [doc = "WINDOW"] # [inline (always)] pub fn is_wwdtctl0_mode_window (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW } # [doc = "INTERVAL"] # [inline (always)] pub fn is_wwdtctl0_mode_interval (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL } } # [doc = "Field `WWDTCTL0_MODE` writer - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_MODE_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "WINDOW"] # [inline (always)] pub fn wwdtctl0_mode_window (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW) } # [doc = "INTERVAL"] # [inline (always)] pub fn wwdtctl0_mode_interval (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL) } } # [doc = "Field `WWDTCTL0_STISM` reader - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_R = crate :: BitReader < WWDTCTL0_STISM_A > ; # [doc = "Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_STISM_A { # [doc = "0: CONT"] WWDTCTL0_STISM_CONT = 0 , # [doc = "1: STOP"] WWDTCTL0_STISM_STOP = 1 , } impl From < WWDTCTL0_STISM_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_STISM_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_STISM_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_STISM_A { match self . bits { false => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT , true => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP , } } # [doc = "CONT"] # [inline (always)] pub fn is_wwdtctl0_stism_cont (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT } # [doc = "STOP"] # [inline (always)] pub fn is_wwdtctl0_stism_stop (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP } } # [doc = "Field `WWDTCTL0_STISM` writer - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_STISM_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_STISM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONT"] # [inline (always)] pub fn wwdtctl0_stism_cont (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT) } # [doc = "STOP"] # [inline (always)] pub fn wwdtctl0_stism_stop (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP) } } # [doc = "Field `WWDTCTL0_KEY` reader - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_R = crate :: FieldReader < WWDTCTL0_KEY_A > ; # [doc = "KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_KEY_A { # [doc = "201: _TO_UNLOCK_W_"] WWDTCTL0_KEY_UNLOCK_W = 201 , } impl From < WWDTCTL0_KEY_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_KEY_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_KEY_A { type Ux = u8 ; } impl WWDTCTL0_KEY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < WWDTCTL0_KEY_A > { match self . bits { 201 => Some (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) , _ => None , } } # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn is_wwdtctl0_key_unlock_w (& self) -> bool { * self == WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W } } # [doc = "Field `WWDTCTL0_KEY` writer - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , WWDTCTL0_KEY_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn wwdtctl0_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) } } impl R { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] pub fn wwdtctl0_clkdiv (& self) -> WWDTCTL0_CLKDIV_R { WWDTCTL0_CLKDIV_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] pub fn wwdtctl0_per (& self) -> WWDTCTL0_PER_R { WWDTCTL0_PER_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window0 (& self) -> WWDTCTL0_WINDOW0_R { WWDTCTL0_WINDOW0_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window1 (& self) -> WWDTCTL0_WINDOW1_R { WWDTCTL0_WINDOW1_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] pub fn wwdtctl0_mode (& self) -> WWDTCTL0_MODE_R { WWDTCTL0_MODE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] pub fn wwdtctl0_stism (& self) -> WWDTCTL0_STISM_R { WWDTCTL0_STISM_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] pub fn wwdtctl0_key (& self) -> WWDTCTL0_KEY_R { WWDTCTL0_KEY_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_clkdiv (& mut self) -> WWDTCTL0_CLKDIV_W < WWDTCTL0_SPEC , 0 > { WWDTCTL0_CLKDIV_W :: new (self) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] # [must_use] pub fn wwdtctl0_per (& mut self) -> WWDTCTL0_PER_W < WWDTCTL0_SPEC , 4 > { WWDTCTL0_PER_W :: new (self) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window0 (& mut self) -> WWDTCTL0_WINDOW0_W < WWDTCTL0_SPEC , 8 > { WWDTCTL0_WINDOW0_W :: new (self) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window1 (& mut self) -> WWDTCTL0_WINDOW1_W < WWDTCTL0_SPEC , 12 > { WWDTCTL0_WINDOW1_W :: new (self) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] # [must_use] pub fn wwdtctl0_mode (& mut self) -> WWDTCTL0_MODE_W < WWDTCTL0_SPEC , 16 > { WWDTCTL0_MODE_W :: new (self) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] # [must_use] pub fn wwdtctl0_stism (& mut self) -> WWDTCTL0_STISM_W <'_, WWDTCTL0_SPEC , 17 > { WWDTCTL0_STISM_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_key (& mut self) -> WWDTCTL0_KEY_W < WWDTCTL0_SPEC , 24 > { WWDTCTL0_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WWDTCTL0_SPEC ; impl crate :: RegisterSpec for WWDTCTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtctl0::R`](R) reader structure"] impl crate :: Readable for WWDTCTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtctl0::W`](W) writer structure"] impl crate :: Writable for WWDTCTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCTL0 to value 0x43"] impl crate :: Resettable for WWDTCTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x43 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:34687 [INFO] [stdout] | [INFO] [stdout] 1 | ..._imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W <'_, INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:41691 [INFO] [stdout] | [INFO] [stdout] 1 | ...nt0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W <'_, INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/rstctl.rs:1:3464 [INFO] [stdout] | [INFO] [stdout] 1 | ... rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W <'_, RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg1/fpub_0.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fpub_0_chanid (& mut self) -> FPUB_0_CHANID_W < FPUB_0_SPEC , 0 > { FPUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FPUB_0` reader"] pub type R = crate :: R < FPUB_0_SPEC > ; # [doc = "Register `FPUB_0` writer"] pub type W = crate :: W < FPUB_0_SPEC > ; # [doc = "Field `FPUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_0_CHANID_R = crate :: FieldReader < FPUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FPUB_0_CHANID_A { # [doc = "0: UNCONNECTED"] FPUB_0_CHANID_UNCONNECTED = 0 , } impl From < FPUB_0_CHANID_A > for u8 { # [inline (always)] fn from (variant : FPUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_0_CHANID_A { type Ux = u8 ; } impl FPUB_0_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FPUB_0_CHANID_A > { match self . bits { 0 => Some (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fpub_0_chanid_unconnected (& self) -> bool { * self == FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fpub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fpub_0_chanid (& self) -> FPUB_0_CHANID_R { FPUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fpub_0_chanid (& mut self) -> FPUB_0_CHANID_W <'_, FPUB_0_SPEC , 0 > { FPUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FPUB_0_SPEC ; impl crate :: RegisterSpec for FPUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_0::R`](R) reader structure"] impl crate :: Readable for FPUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_0::W`](W) writer structure"] impl crate :: Writable for FPUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_0 to value 0"] impl crate :: Resettable for FPUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:34932 [INFO] [stdout] | [INFO] [stdout] 1 | ..._imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W <'_, INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/wwdtctl0.rs:1:24896 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn wwdtctl0_key (& mut self) -> WWDTCTL0_KEY_W < WWDTCTL0_SPEC , 24 > { WWDTCTL0_KEY_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `WWDTCTL0` reader"] pub type R = crate :: R < WWDTCTL0_SPEC > ; # [doc = "Register `WWDTCTL0` writer"] pub type W = crate :: W < WWDTCTL0_SPEC > ; # [doc = "Field `WWDTCTL0_CLKDIV` reader - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_R = crate :: FieldReader ; # [doc = "Field `WWDTCTL0_CLKDIV` writer - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] pub type WWDTCTL0_CLKDIV_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `WWDTCTL0_PER` reader - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_R = crate :: FieldReader < WWDTCTL0_PER_A > ; # [doc = "Timer Period of the WWDT. These bits select the total watchdog timer count.\n\nValue on reset: 4"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_PER_A { # [doc = "0: EN_25"] WWDTCTL0_PER_EN_25 = 0 , # [doc = "1: EN_21"] WWDTCTL0_PER_EN_21 = 1 , # [doc = "2: EN_18"] WWDTCTL0_PER_EN_18 = 2 , # [doc = "3: EN_15"] WWDTCTL0_PER_EN_15 = 3 , # [doc = "4: EN_12"] WWDTCTL0_PER_EN_12 = 4 , # [doc = "5: EN_10"] WWDTCTL0_PER_EN_10 = 5 , # [doc = "6: EN_8"] WWDTCTL0_PER_EN_8 = 6 , # [doc = "7: EN_6"] WWDTCTL0_PER_EN_6 = 7 , } impl From < WWDTCTL0_PER_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_PER_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_PER_A { type Ux = u8 ; } impl WWDTCTL0_PER_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_PER_A { match self . bits { 0 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 , 1 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 , 2 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 , 3 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 , 4 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 , 5 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 , 6 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 , 7 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 , _ => unreachable ! () , } } # [doc = "EN_25"] # [inline (always)] pub fn is_wwdtctl0_per_en_25 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 } # [doc = "EN_21"] # [inline (always)] pub fn is_wwdtctl0_per_en_21 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 } # [doc = "EN_18"] # [inline (always)] pub fn is_wwdtctl0_per_en_18 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 } # [doc = "EN_15"] # [inline (always)] pub fn is_wwdtctl0_per_en_15 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 } # [doc = "EN_12"] # [inline (always)] pub fn is_wwdtctl0_per_en_12 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 } # [doc = "EN_10"] # [inline (always)] pub fn is_wwdtctl0_per_en_10 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 } # [doc = "EN_8"] # [inline (always)] pub fn is_wwdtctl0_per_en_8 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 } # [doc = "EN_6"] # [inline (always)] pub fn is_wwdtctl0_per_en_6 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 } } # [doc = "Field `WWDTCTL0_PER` writer - Timer Period of the WWDT. These bits select the total watchdog timer count."] pub type WWDTCTL0_PER_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_PER_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "EN_25"] # [inline (always)] pub fn wwdtctl0_per_en_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25) } # [doc = "EN_21"] # [inline (always)] pub fn wwdtctl0_per_en_21 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21) } # [doc = "EN_18"] # [inline (always)] pub fn wwdtctl0_per_en_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18) } # [doc = "EN_15"] # [inline (always)] pub fn wwdtctl0_per_en_15 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15) } # [doc = "EN_12"] # [inline (always)] pub fn wwdtctl0_per_en_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12) } # [doc = "EN_10"] # [inline (always)] pub fn wwdtctl0_per_en_10 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10) } # [doc = "EN_8"] # [inline (always)] pub fn wwdtctl0_per_en_8 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8) } # [doc = "EN_6"] # [inline (always)] pub fn wwdtctl0_per_en_6 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6) } } # [doc = "Field `WWDTCTL0_WINDOW0` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_R = crate :: FieldReader < WWDTCTL0_WINDOW0_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW0_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW0_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW0_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW0_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW0_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW0_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW0_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW0_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW0_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW0_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW0_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW0_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW0_A { match self . bits { 0 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 , 1 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 , 2 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 , 3 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 , 4 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 , 5 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 , 6 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 , 7 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window0_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window0_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window0_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window0_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window0_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window0_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window0_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window0_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW0` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW0_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW0_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window0_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window0_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window0_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window0_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window0_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window0_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window0_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window0_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87) } } # [doc = "Field `WWDTCTL0_WINDOW1` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_R = crate :: FieldReader < WWDTCTL0_WINDOW1_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_WINDOW1_A { # [doc = "0: SIZE_0"] WWDTCTL0_WINDOW1_SIZE_0 = 0 , # [doc = "1: SIZE_12"] WWDTCTL0_WINDOW1_SIZE_12 = 1 , # [doc = "2: SIZE_18"] WWDTCTL0_WINDOW1_SIZE_18 = 2 , # [doc = "3: SIZE_25"] WWDTCTL0_WINDOW1_SIZE_25 = 3 , # [doc = "4: SIZE_50"] WWDTCTL0_WINDOW1_SIZE_50 = 4 , # [doc = "5: SIZE_75"] WWDTCTL0_WINDOW1_SIZE_75 = 5 , # [doc = "6: SIZE_81"] WWDTCTL0_WINDOW1_SIZE_81 = 6 , # [doc = "7: SIZE_87"] WWDTCTL0_WINDOW1_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW1_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_WINDOW1_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW1_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_WINDOW1_A { match self . bits { 0 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 , 1 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 , 2 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 , 3 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 , 4 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 , 5 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 , 6 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 , 7 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"] # [inline (always)] pub fn is_wwdtctl0_window1_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 } # [doc = "SIZE_12"] # [inline (always)] pub fn is_wwdtctl0_window1_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 } # [doc = "SIZE_18"] # [inline (always)] pub fn is_wwdtctl0_window1_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 } # [doc = "SIZE_25"] # [inline (always)] pub fn is_wwdtctl0_window1_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 } # [doc = "SIZE_50"] # [inline (always)] pub fn is_wwdtctl0_window1_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 } # [doc = "SIZE_75"] # [inline (always)] pub fn is_wwdtctl0_window1_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 } # [doc = "SIZE_81"] # [inline (always)] pub fn is_wwdtctl0_window1_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 } # [doc = "SIZE_87"] # [inline (always)] pub fn is_wwdtctl0_window1_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW1` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] pub type WWDTCTL0_WINDOW1_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW1_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"] # [inline (always)] pub fn wwdtctl0_window1_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0) } # [doc = "SIZE_12"] # [inline (always)] pub fn wwdtctl0_window1_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12) } # [doc = "SIZE_18"] # [inline (always)] pub fn wwdtctl0_window1_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18) } # [doc = "SIZE_25"] # [inline (always)] pub fn wwdtctl0_window1_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25) } # [doc = "SIZE_50"] # [inline (always)] pub fn wwdtctl0_window1_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50) } # [doc = "SIZE_75"] # [inline (always)] pub fn wwdtctl0_window1_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75) } # [doc = "SIZE_81"] # [inline (always)] pub fn wwdtctl0_window1_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81) } # [doc = "SIZE_87"] # [inline (always)] pub fn wwdtctl0_window1_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87) } } # [doc = "Field `WWDTCTL0_MODE` reader - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_R = crate :: BitReader < WWDTCTL0_MODE_A > ; # [doc = "Window Watchdog Timer Mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_MODE_A { # [doc = "0: WINDOW"] WWDTCTL0_MODE_WINDOW = 0 , # [doc = "1: INTERVAL"] WWDTCTL0_MODE_INTERVAL = 1 , } impl From < WWDTCTL0_MODE_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_MODE_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_MODE_A { match self . bits { false => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW , true => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL , } } # [doc = "WINDOW"] # [inline (always)] pub fn is_wwdtctl0_mode_window (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW } # [doc = "INTERVAL"] # [inline (always)] pub fn is_wwdtctl0_mode_interval (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL } } # [doc = "Field `WWDTCTL0_MODE` writer - Window Watchdog Timer Mode"] pub type WWDTCTL0_MODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_MODE_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "WINDOW"] # [inline (always)] pub fn wwdtctl0_mode_window (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW) } # [doc = "INTERVAL"] # [inline (always)] pub fn wwdtctl0_mode_interval (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL) } } # [doc = "Field `WWDTCTL0_STISM` reader - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_R = crate :: BitReader < WWDTCTL0_STISM_A > ; # [doc = "Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL0_STISM_A { # [doc = "0: CONT"] WWDTCTL0_STISM_CONT = 0 , # [doc = "1: STOP"] WWDTCTL0_STISM_STOP = 1 , } impl From < WWDTCTL0_STISM_A > for bool { # [inline (always)] fn from (variant : WWDTCTL0_STISM_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_STISM_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL0_STISM_A { match self . bits { false => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT , true => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP , } } # [doc = "CONT"] # [inline (always)] pub fn is_wwdtctl0_stism_cont (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT } # [doc = "STOP"] # [inline (always)] pub fn is_wwdtctl0_stism_stop (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP } } # [doc = "Field `WWDTCTL0_STISM` writer - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] pub type WWDTCTL0_STISM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_STISM_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_STISM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONT"] # [inline (always)] pub fn wwdtctl0_stism_cont (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT) } # [doc = "STOP"] # [inline (always)] pub fn wwdtctl0_stism_stop (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP) } } # [doc = "Field `WWDTCTL0_KEY` reader - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_R = crate :: FieldReader < WWDTCTL0_KEY_A > ; # [doc = "KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL0_KEY_A { # [doc = "201: _TO_UNLOCK_W_"] WWDTCTL0_KEY_UNLOCK_W = 201 , } impl From < WWDTCTL0_KEY_A > for u8 { # [inline (always)] fn from (variant : WWDTCTL0_KEY_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_KEY_A { type Ux = u8 ; } impl WWDTCTL0_KEY_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < WWDTCTL0_KEY_A > { match self . bits { 201 => Some (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) , _ => None , } } # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn is_wwdtctl0_key_unlock_w (& self) -> bool { * self == WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W } } # [doc = "Field `WWDTCTL0_KEY` writer - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL0_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , WWDTCTL0_KEY_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn wwdtctl0_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) } } impl R { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] pub fn wwdtctl0_clkdiv (& self) -> WWDTCTL0_CLKDIV_R { WWDTCTL0_CLKDIV_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] pub fn wwdtctl0_per (& self) -> WWDTCTL0_PER_R { WWDTCTL0_PER_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window0 (& self) -> WWDTCTL0_WINDOW0_R { WWDTCTL0_WINDOW0_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] pub fn wwdtctl0_window1 (& self) -> WWDTCTL0_WINDOW1_R { WWDTCTL0_WINDOW1_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] pub fn wwdtctl0_mode (& self) -> WWDTCTL0_MODE_R { WWDTCTL0_MODE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] pub fn wwdtctl0_stism (& self) -> WWDTCTL0_STISM_R { WWDTCTL0_STISM_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] pub fn wwdtctl0_key (& self) -> WWDTCTL0_KEY_R { WWDTCTL0_KEY_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_clkdiv (& mut self) -> WWDTCTL0_CLKDIV_W < WWDTCTL0_SPEC , 0 > { WWDTCTL0_CLKDIV_W :: new (self) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."] # [inline (always)] # [must_use] pub fn wwdtctl0_per (& mut self) -> WWDTCTL0_PER_W < WWDTCTL0_SPEC , 4 > { WWDTCTL0_PER_W :: new (self) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window0 (& mut self) -> WWDTCTL0_WINDOW0_W < WWDTCTL0_SPEC , 8 > { WWDTCTL0_WINDOW0_W :: new (self) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."] # [inline (always)] # [must_use] pub fn wwdtctl0_window1 (& mut self) -> WWDTCTL0_WINDOW1_W < WWDTCTL0_SPEC , 12 > { WWDTCTL0_WINDOW1_W :: new (self) } # [doc = "Bit 16 - Window Watchdog Timer Mode"] # [inline (always)] # [must_use] pub fn wwdtctl0_mode (& mut self) -> WWDTCTL0_MODE_W < WWDTCTL0_SPEC , 16 > { WWDTCTL0_MODE_W :: new (self) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."] # [inline (always)] # [must_use] pub fn wwdtctl0_stism (& mut self) -> WWDTCTL0_STISM_W < WWDTCTL0_SPEC , 17 > { WWDTCTL0_STISM_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] # [must_use] pub fn wwdtctl0_key (& mut self) -> WWDTCTL0_KEY_W <'_, WWDTCTL0_SPEC , 24 > { WWDTCTL0_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WWDTCTL0_SPEC ; impl crate :: RegisterSpec for WWDTCTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtctl0::R`](R) reader structure"] impl crate :: Readable for WWDTCTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtctl0::W`](W) writer structure"] impl crate :: Writable for WWDTCTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCTL0 to value 0x43"] impl crate :: Resettable for WWDTCTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x43 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/rstctl.rs:1:3649 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W <'_, RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/ctl0.rs:1:37769 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Contro... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W <'_, CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg1/fpub_1.rs:1:2067 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W < FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FPUB_1` reader"] pub type R = crate :: R < FPUB_1_SPEC > ; # [doc = "Register `FPUB_1` writer"] pub type W = crate :: W < FPUB_1_SPEC > ; # [doc = "Field `FPUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_1_CHANID_R = crate :: FieldReader < FPUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum FPUB_1_CHANID_A { # [doc = "0: UNCONNECTED"] FPUB_1_CHANID_UNCONNECTED = 0 , } impl From < FPUB_1_CHANID_A > for u8 { # [inline (always)] fn from (variant : FPUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_1_CHANID_A { type Ux = u8 ; } impl FPUB_1_CHANID_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < FPUB_1_CHANID_A > { match self . bits { 0 => Some (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"] # [inline (always)] pub fn is_fpub_1_chanid_unconnected (& self) -> bool { * self == FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."] pub type FPUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"] # [inline (always)] pub fn fpub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] pub fn fpub_1_chanid (& self) -> FPUB_1_CHANID_R { FPUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."] # [inline (always)] # [must_use] pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W <'_, FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FPUB_1_SPEC ; impl crate :: RegisterSpec for FPUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_1::R`](R) reader structure"] impl crate :: Readable for FPUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_1::W`](W) writer structure"] impl crate :: Writable for FPUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_1 to value 0"] impl crate :: Resettable for FPUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:35174 [INFO] [stdout] | [INFO] [stdout] 1 | ...nt0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W <'_, INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:41929 [INFO] [stdout] | [INFO] [stdout] 1 | ...nt0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W <'_, INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/clkovr.rs:10:111 [INFO] [stdout] | [INFO] [stdout] 10 | ...pub fn clkovr_override (& mut self) -> CLKOVR_OVERRIDE_W < CLKOVR_SPEC , 0 > { CLKOVR_OVERRIDE_W :: new (self) } # [doc = "Bit 1 - If ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 10 | to override the automatic peripheral clock request"] # [inline (always)] # [must_use] pub fn clkovr_override (& mut self) -> CLKOVR_OVERRIDE_W <'_, CLKOVR_SPEC , 0 > { CLKOVR_OVERRIDE_W :: new (self) } # [doc = "Bit 1 - If \\[OVERRIDE\\] [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/clkovr.rs:11:159 [INFO] [stdout] | [INFO] [stdout] 11 | ...pub fn clkovr_run_stop (& mut self) -> CLKOVR_RUN_STOP_W < CLKOVR_SPEC , 1 > { CLKOVR_RUN_STOP_W :: new (self) } # [doc = r" Writes ra... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 11 | is enabled, this register is used to manually control the peripheral's clock request to the system"] # [inline (always)] # [must_use] pub fn clkovr_run_stop (& mut self) -> CLKOVR_RUN_STOP_W <'_, CLKOVR_SPEC , 1 > { CLKOVR_RUN_STOP_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Override\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkovr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkovr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKOVR_SPEC ; impl crate :: RegisterSpec for CLKOVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkovr::R`](R) reader structure"] impl crate :: Readable for CLKOVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkovr::W`](W) writer structure"] impl crate :: Writable for CLKOVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKOVR to value 0"] impl crate :: Resettable for CLKOVR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/wwdtctl1.rs:1:3291 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn wwdtctl1_winsel (& mut self) -> WWDTCTL1_WINSEL_W < WWDTCTL1_SPEC , 0 > { WWDTCTL1_WINSEL_W :: new (self) } # [doc = "Bits 24:31... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `WWDTCTL1` reader"] pub type R = crate :: R < WWDTCTL1_SPEC > ; # [doc = "Register `WWDTCTL1` writer"] pub type W = crate :: W < WWDTCTL1_SPEC > ; # [doc = "Field `WWDTCTL1_WINSEL` reader - Close Window Select"] pub type WWDTCTL1_WINSEL_R = crate :: BitReader < WWDTCTL1_WINSEL_A > ; # [doc = "Close Window Select\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL1_WINSEL_A { # [doc = "0: WIN0"] WWDTCTL1_WINSEL_WIN0 = 0 , # [doc = "1: WIN1"] WWDTCTL1_WINSEL_WIN1 = 1 , } impl From < WWDTCTL1_WINSEL_A > for bool { # [inline (always)] fn from (variant : WWDTCTL1_WINSEL_A) -> Self { variant as u8 != 0 } } impl WWDTCTL1_WINSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL1_WINSEL_A { match self . bits { false => WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN0 , true => WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN1 , } } # [doc = "WIN0"] # [inline (always)] pub fn is_wwdtctl1_winsel_win0 (& self) -> bool { * self == WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN0 } # [doc = "WIN1"] # [inline (always)] pub fn is_wwdtctl1_winsel_win1 (& self) -> bool { * self == WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN1 } } # [doc = "Field `WWDTCTL1_WINSEL` writer - Close Window Select"] pub type WWDTCTL1_WINSEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL1_WINSEL_A > ; impl < 'a , REG , const O : u8 > WWDTCTL1_WINSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "WIN0"] # [inline (always)] pub fn wwdtctl1_winsel_win0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN0) } # [doc = "WIN1"] # [inline (always)] pub fn wwdtctl1_winsel_win1 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN1) } } # [doc = "KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL1_KEY_AW { # [doc = "190: _TO_UNLOCK_W_"] WWDTCTL1_KEY_UNLOCK_W = 190 , } impl From < WWDTCTL1_KEY_AW > for u8 { # [inline (always)] fn from (variant : WWDTCTL1_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL1_KEY_AW { type Ux = u8 ; } # [doc = "Field `WWDTCTL1_KEY` writer - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL1_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , WWDTCTL1_KEY_AW > ; impl < 'a , REG , const O : u8 > WWDTCTL1_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn wwdtctl1_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL1_KEY_AW :: WWDTCTL1_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Close Window Select"] # [inline (always)] pub fn wwdtctl1_winsel (& self) -> WWDTCTL1_WINSEL_R { WWDTCTL1_WINSEL_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Close Window Select"] # [inline (always)] # [must_use] pub fn wwdtctl1_winsel (& mut self) -> WWDTCTL1_WINSEL_W <'_, WWDTCTL1_SPEC , 0 > { WWDTCTL1_WINSEL_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] # [must_use] pub fn wwdtctl1_key (& mut self) -> WWDTCTL1_KEY_W < WWDTCTL1_SPEC , 24 > { WWDTCTL1_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WWDTCTL1_SPEC ; impl crate :: RegisterSpec for WWDTCTL1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtctl1::R`](R) reader structure"] impl crate :: Readable for WWDTCTL1_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtctl1::W`](W) writer structure"] impl crate :: Writable for WWDTCTL1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCTL1 to value 0"] impl crate :: Resettable for WWDTCTL1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/ctl0.rs:1:38112 [INFO] [stdout] | [INFO] [stdout] 1 | ... pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W <'_, CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:42165 [INFO] [stdout] | [INFO] [stdout] 1 | ...t0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W <'_, INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg1/pwren.rs:1:2941 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W <'_, PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/pdbgctl.rs:1:2014 [INFO] [stdout] | [INFO] [stdout] 1 | ...se] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = r" Writes raw bi... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PDBGCTL` reader"] pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"] pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"] pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"] PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"] PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)] fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"] # [inline (always)] pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"] # [inline (always)] pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"] pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"] # [inline (always)] pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"] # [inline (always)] pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } impl R { # [doc = "Bit 0 - Free run control"] # [inline (always)] pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"] # [inline (always)] # [must_use] pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W <'_, PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"] impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"] impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0x01"] impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0x01 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/ctl0.rs:1:38343 [INFO] [stdout] | [INFO] [stdout] 1 | ..._use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W <'_, CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/wwdtctl1.rs:1:3607 [INFO] [stdout] | [INFO] [stdout] 1 | ...e] pub fn wwdtctl1_key (& mut self) -> WWDTCTL1_KEY_W < WWDTCTL1_SPEC , 24 > { WWDTCTL1_KEY_W :: new (self) } # [doc = r" Writes raw b... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `WWDTCTL1` reader"] pub type R = crate :: R < WWDTCTL1_SPEC > ; # [doc = "Register `WWDTCTL1` writer"] pub type W = crate :: W < WWDTCTL1_SPEC > ; # [doc = "Field `WWDTCTL1_WINSEL` reader - Close Window Select"] pub type WWDTCTL1_WINSEL_R = crate :: BitReader < WWDTCTL1_WINSEL_A > ; # [doc = "Close Window Select\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WWDTCTL1_WINSEL_A { # [doc = "0: WIN0"] WWDTCTL1_WINSEL_WIN0 = 0 , # [doc = "1: WIN1"] WWDTCTL1_WINSEL_WIN1 = 1 , } impl From < WWDTCTL1_WINSEL_A > for bool { # [inline (always)] fn from (variant : WWDTCTL1_WINSEL_A) -> Self { variant as u8 != 0 } } impl WWDTCTL1_WINSEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> WWDTCTL1_WINSEL_A { match self . bits { false => WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN0 , true => WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN1 , } } # [doc = "WIN0"] # [inline (always)] pub fn is_wwdtctl1_winsel_win0 (& self) -> bool { * self == WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN0 } # [doc = "WIN1"] # [inline (always)] pub fn is_wwdtctl1_winsel_win1 (& self) -> bool { * self == WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN1 } } # [doc = "Field `WWDTCTL1_WINSEL` writer - Close Window Select"] pub type WWDTCTL1_WINSEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL1_WINSEL_A > ; impl < 'a , REG , const O : u8 > WWDTCTL1_WINSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "WIN0"] # [inline (always)] pub fn wwdtctl1_winsel_win0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN0) } # [doc = "WIN1"] # [inline (always)] pub fn wwdtctl1_winsel_win1 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN1) } } # [doc = "KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum WWDTCTL1_KEY_AW { # [doc = "190: _TO_UNLOCK_W_"] WWDTCTL1_KEY_UNLOCK_W = 190 , } impl From < WWDTCTL1_KEY_AW > for u8 { # [inline (always)] fn from (variant : WWDTCTL1_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL1_KEY_AW { type Ux = u8 ; } # [doc = "Field `WWDTCTL1_KEY` writer - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] pub type WWDTCTL1_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , WWDTCTL1_KEY_AW > ; impl < 'a , REG , const O : u8 > WWDTCTL1_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn wwdtctl1_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL1_KEY_AW :: WWDTCTL1_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Close Window Select"] # [inline (always)] pub fn wwdtctl1_winsel (& self) -> WWDTCTL1_WINSEL_R { WWDTCTL1_WINSEL_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Close Window Select"] # [inline (always)] # [must_use] pub fn wwdtctl1_winsel (& mut self) -> WWDTCTL1_WINSEL_W < WWDTCTL1_SPEC , 0 > { WWDTCTL1_WINSEL_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."] # [inline (always)] # [must_use] pub fn wwdtctl1_key (& mut self) -> WWDTCTL1_KEY_W <'_, WWDTCTL1_SPEC , 24 > { WWDTCTL1_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WWDTCTL1_SPEC ; impl crate :: RegisterSpec for WWDTCTL1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtctl1::R`](R) reader structure"] impl crate :: Readable for WWDTCTL1_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtctl1::W`](W) writer structure"] impl crate :: Writable for WWDTCTL1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCTL1 to value 0"] impl crate :: Resettable for WWDTCTL1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/int_event0_imask.rs:1:66161 [INFO] [stdout] | [INFO] [stdout] 1 | ...nt0_imask_dio0 (& mut self) -> INT_EVENT0_IMASK_DIO0_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_DIO0_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_DIO0` reader - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_R = crate :: BitReader < INT_EVENT0_IMASK_DIO0_A > ; # [doc = "DIO0 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO0_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO0_A { match self . bits { false => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR , true => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio0_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO0` writer - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` reader - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_R = crate :: BitReader < INT_EVENT0_IMASK_DIO1_A > ; # [doc = "DIO1 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO1_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO1_A { match self . bits { false => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR , true => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio1_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` writer - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` reader - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_R = crate :: BitReader < INT_EVENT0_IMASK_DIO2_A > ; # [doc = "DIO2 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO2_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO2_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO2_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO2_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO2_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO2_A { match self . bits { false => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR , true => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio2_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` writer - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` reader - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_R = crate :: BitReader < INT_EVENT0_IMASK_DIO3_A > ; # [doc = "DIO3 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO3_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO3_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO3_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO3_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO3_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO3_A { match self . bits { false => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR , true => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio3_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` writer - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` reader - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_R = crate :: BitReader < INT_EVENT0_IMASK_DIO4_A > ; # [doc = "DIO4 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO4_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO4_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO4_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO4_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO4_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO4_A { match self . bits { false => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR , true => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio4_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio4_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` writer - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO4_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` reader - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_R = crate :: BitReader < INT_EVENT0_IMASK_DIO5_A > ; # [doc = "DIO5 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO5_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO5_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO5_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO5_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO5_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO5_A { match self . bits { false => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR , true => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio5_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio5_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` writer - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO5_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` reader - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_R = crate :: BitReader < INT_EVENT0_IMASK_DIO6_A > ; # [doc = "DIO6 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO6_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO6_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO6_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO6_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO6_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO6_A { match self . bits { false => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR , true => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio6_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio6_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` writer - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO6_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` reader - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_R = crate :: BitReader < INT_EVENT0_IMASK_DIO7_A > ; # [doc = "DIO7 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO7_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO7_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO7_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO7_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO7_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO7_A { match self . bits { false => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR , true => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio7_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio7_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` writer - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO7_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` reader - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_R = crate :: BitReader < INT_EVENT0_IMASK_DIO8_A > ; # [doc = "DIO8 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO8_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO8_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO8_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO8_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO8_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO8_A { match self . bits { false => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR , true => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio8_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio8_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` writer - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO8_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` reader - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_R = crate :: BitReader < INT_EVENT0_IMASK_DIO9_A > ; # [doc = "DIO9 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO9_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO9_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO9_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO9_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO9_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO9_A { match self . bits { false => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR , true => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio9_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio9_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` writer - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO9_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` reader - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_R = crate :: BitReader < INT_EVENT0_IMASK_DIO10_A > ; # [doc = "DIO10 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO10_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO10_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO10_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO10_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO10_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO10_A { match self . bits { false => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR , true => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio10_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio10_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` writer - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO10_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` reader - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_R = crate :: BitReader < INT_EVENT0_IMASK_DIO11_A > ; # [doc = "DIO11 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO11_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO11_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO11_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO11_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO11_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO11_A { match self . bits { false => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR , true => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio11_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio11_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` writer - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO11_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` reader - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_R = crate :: BitReader < INT_EVENT0_IMASK_DIO12_A > ; # [doc = "DIO12 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO12_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO12_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO12_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO12_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO12_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO12_A { match self . bits { false => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR , true => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio12_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio12_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` writer - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO12_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` reader - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_R = crate :: BitReader < INT_EVENT0_IMASK_DIO13_A > ; # [doc = "DIO13 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO13_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO13_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO13_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO13_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO13_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO13_A { match self . bits { false => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR , true => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio13_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio13_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` writer - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO13_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` reader - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_R = crate :: BitReader < INT_EVENT0_IMASK_DIO14_A > ; # [doc = "DIO14 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO14_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO14_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO14_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO14_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO14_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO14_A { match self . bits { false => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR , true => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio14_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio14_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` writer - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO14_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` reader - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_R = crate :: BitReader < INT_EVENT0_IMASK_DIO15_A > ; # [doc = "DIO15 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO15_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO15_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO15_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO15_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO15_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO15_A { match self . bits { false => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR , true => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio15_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio15_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` writer - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO15_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` reader - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_R = crate :: BitReader < INT_EVENT0_IMASK_DIO16_A > ; # [doc = "DIO16 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO16_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO16_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO16_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO16_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO16_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO16_A { match self . bits { false => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR , true => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio16_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio16_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` writer - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO16_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` reader - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_R = crate :: BitReader < INT_EVENT0_IMASK_DIO17_A > ; # [doc = "DIO17 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO17_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO17_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO17_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO17_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO17_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO17_A { match self . bits { false => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR , true => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio17_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio17_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` writer - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO17_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` reader - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_R = crate :: BitReader < INT_EVENT0_IMASK_DIO18_A > ; # [doc = "DIO18 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO18_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO18_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO18_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO18_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO18_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO18_A { match self . bits { false => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR , true => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio18_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio18_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` writer - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO18_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` reader - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_R = crate :: BitReader < INT_EVENT0_IMASK_DIO19_A > ; # [doc = "DIO19 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO19_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO19_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO19_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO19_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO19_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO19_A { match self . bits { false => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR , true => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio19_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio19_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` writer - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO19_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` reader - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_R = crate :: BitReader < INT_EVENT0_IMASK_DIO20_A > ; # [doc = "DIO20 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO20_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO20_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO20_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO20_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO20_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO20_A { match self . bits { false => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR , true => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio20_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio20_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` writer - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO20_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` reader - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_R = crate :: BitReader < INT_EVENT0_IMASK_DIO21_A > ; # [doc = "DIO21 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO21_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO21_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO21_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO21_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO21_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO21_A { match self . bits { false => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR , true => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio21_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio21_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` writer - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO21_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` reader - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_R = crate :: BitReader < INT_EVENT0_IMASK_DIO22_A > ; # [doc = "DIO22 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO22_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO22_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO22_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO22_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO22_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO22_A { match self . bits { false => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR , true => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio22_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio22_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` writer - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO22_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` reader - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_R = crate :: BitReader < INT_EVENT0_IMASK_DIO23_A > ; # [doc = "DIO23 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO23_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO23_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO23_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO23_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO23_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO23_A { match self . bits { false => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR , true => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio23_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio23_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` writer - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO23_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` reader - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_R = crate :: BitReader < INT_EVENT0_IMASK_DIO24_A > ; # [doc = "DIO24 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO24_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO24_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO24_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO24_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO24_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO24_A { match self . bits { false => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR , true => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio24_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio24_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` writer - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO24_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` reader - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_R = crate :: BitReader < INT_EVENT0_IMASK_DIO25_A > ; # [doc = "DIO25 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO25_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO25_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO25_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO25_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO25_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO25_A { match self . bits { false => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR , true => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio25_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio25_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` writer - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO25_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` reader - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_R = crate :: BitReader < INT_EVENT0_IMASK_DIO26_A > ; # [doc = "DIO26 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO26_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO26_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO26_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO26_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO26_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO26_A { match self . bits { false => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR , true => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio26_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio26_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` writer - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO26_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` reader - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_R = crate :: BitReader < INT_EVENT0_IMASK_DIO27_A > ; # [doc = "DIO27 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO27_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO27_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO27_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO27_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO27_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO27_A { match self . bits { false => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR , true => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio27_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio27_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` writer - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO27_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` reader - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_R = crate :: BitReader < INT_EVENT0_IMASK_DIO28_A > ; # [doc = "DIO28 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO28_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO28_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO28_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO28_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO28_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO28_A { match self . bits { false => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR , true => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio28_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio28_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` writer - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO28_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` reader - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_R = crate :: BitReader < INT_EVENT0_IMASK_DIO29_A > ; # [doc = "DIO29 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO29_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO29_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO29_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO29_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO29_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO29_A { match self . bits { false => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR , true => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio29_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio29_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` writer - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO29_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` reader - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_R = crate :: BitReader < INT_EVENT0_IMASK_DIO30_A > ; # [doc = "DIO30 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO30_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO30_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO30_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO30_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO30_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO30_A { match self . bits { false => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR , true => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio30_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio30_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` writer - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO30_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` reader - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_R = crate :: BitReader < INT_EVENT0_IMASK_DIO31_A > ; # [doc = "DIO31 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO31_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO31_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO31_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO31_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO31_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO31_A { match self . bits { false => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR , true => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio31_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio31_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` writer - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO31_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET) } } impl R { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] pub fn int_event0_imask_dio0 (& self) -> INT_EVENT0_IMASK_DIO0_R { INT_EVENT0_IMASK_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] pub fn int_event0_imask_dio1 (& self) -> INT_EVENT0_IMASK_DIO1_R { INT_EVENT0_IMASK_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] pub fn int_event0_imask_dio2 (& self) -> INT_EVENT0_IMASK_DIO2_R { INT_EVENT0_IMASK_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] pub fn int_event0_imask_dio3 (& self) -> INT_EVENT0_IMASK_DIO3_R { INT_EVENT0_IMASK_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] pub fn int_event0_imask_dio4 (& self) -> INT_EVENT0_IMASK_DIO4_R { INT_EVENT0_IMASK_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] pub fn int_event0_imask_dio5 (& self) -> INT_EVENT0_IMASK_DIO5_R { INT_EVENT0_IMASK_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] pub fn int_event0_imask_dio6 (& self) -> INT_EVENT0_IMASK_DIO6_R { INT_EVENT0_IMASK_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] pub fn int_event0_imask_dio7 (& self) -> INT_EVENT0_IMASK_DIO7_R { INT_EVENT0_IMASK_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] pub fn int_event0_imask_dio8 (& self) -> INT_EVENT0_IMASK_DIO8_R { INT_EVENT0_IMASK_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] pub fn int_event0_imask_dio9 (& self) -> INT_EVENT0_IMASK_DIO9_R { INT_EVENT0_IMASK_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] pub fn int_event0_imask_dio10 (& self) -> INT_EVENT0_IMASK_DIO10_R { INT_EVENT0_IMASK_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] pub fn int_event0_imask_dio11 (& self) -> INT_EVENT0_IMASK_DIO11_R { INT_EVENT0_IMASK_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] pub fn int_event0_imask_dio12 (& self) -> INT_EVENT0_IMASK_DIO12_R { INT_EVENT0_IMASK_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] pub fn int_event0_imask_dio13 (& self) -> INT_EVENT0_IMASK_DIO13_R { INT_EVENT0_IMASK_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] pub fn int_event0_imask_dio14 (& self) -> INT_EVENT0_IMASK_DIO14_R { INT_EVENT0_IMASK_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] pub fn int_event0_imask_dio15 (& self) -> INT_EVENT0_IMASK_DIO15_R { INT_EVENT0_IMASK_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] pub fn int_event0_imask_dio16 (& self) -> INT_EVENT0_IMASK_DIO16_R { INT_EVENT0_IMASK_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] pub fn int_event0_imask_dio17 (& self) -> INT_EVENT0_IMASK_DIO17_R { INT_EVENT0_IMASK_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] pub fn int_event0_imask_dio18 (& self) -> INT_EVENT0_IMASK_DIO18_R { INT_EVENT0_IMASK_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] pub fn int_event0_imask_dio19 (& self) -> INT_EVENT0_IMASK_DIO19_R { INT_EVENT0_IMASK_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] pub fn int_event0_imask_dio20 (& self) -> INT_EVENT0_IMASK_DIO20_R { INT_EVENT0_IMASK_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] pub fn int_event0_imask_dio21 (& self) -> INT_EVENT0_IMASK_DIO21_R { INT_EVENT0_IMASK_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] pub fn int_event0_imask_dio22 (& self) -> INT_EVENT0_IMASK_DIO22_R { INT_EVENT0_IMASK_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] pub fn int_event0_imask_dio23 (& self) -> INT_EVENT0_IMASK_DIO23_R { INT_EVENT0_IMASK_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] pub fn int_event0_imask_dio24 (& self) -> INT_EVENT0_IMASK_DIO24_R { INT_EVENT0_IMASK_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] pub fn int_event0_imask_dio25 (& self) -> INT_EVENT0_IMASK_DIO25_R { INT_EVENT0_IMASK_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] pub fn int_event0_imask_dio26 (& self) -> INT_EVENT0_IMASK_DIO26_R { INT_EVENT0_IMASK_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] pub fn int_event0_imask_dio27 (& self) -> INT_EVENT0_IMASK_DIO27_R { INT_EVENT0_IMASK_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] pub fn int_event0_imask_dio28 (& self) -> INT_EVENT0_IMASK_DIO28_R { INT_EVENT0_IMASK_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] pub fn int_event0_imask_dio29 (& self) -> INT_EVENT0_IMASK_DIO29_R { INT_EVENT0_IMASK_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] pub fn int_event0_imask_dio30 (& self) -> INT_EVENT0_IMASK_DIO30_R { INT_EVENT0_IMASK_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] pub fn int_event0_imask_dio31 (& self) -> INT_EVENT0_IMASK_DIO31_R { INT_EVENT0_IMASK_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio0 (& mut self) -> INT_EVENT0_IMASK_DIO0_W <'_, INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio1 (& mut self) -> INT_EVENT0_IMASK_DIO1_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio2 (& mut self) -> INT_EVENT0_IMASK_DIO2_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio3 (& mut self) -> INT_EVENT0_IMASK_DIO3_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio4 (& mut self) -> INT_EVENT0_IMASK_DIO4_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio5 (& mut self) -> INT_EVENT0_IMASK_DIO5_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio6 (& mut self) -> INT_EVENT0_IMASK_DIO6_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio7 (& mut self) -> INT_EVENT0_IMASK_DIO7_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio8 (& mut self) -> INT_EVENT0_IMASK_DIO8_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio9 (& mut self) -> INT_EVENT0_IMASK_DIO9_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio10 (& mut self) -> INT_EVENT0_IMASK_DIO10_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio11 (& mut self) -> INT_EVENT0_IMASK_DIO11_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio12 (& mut self) -> INT_EVENT0_IMASK_DIO12_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio13 (& mut self) -> INT_EVENT0_IMASK_DIO13_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio14 (& mut self) -> INT_EVENT0_IMASK_DIO14_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio15 (& mut self) -> INT_EVENT0_IMASK_DIO15_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DIO15_W :: new (self) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio16 (& mut self) -> INT_EVENT0_IMASK_DIO16_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio17 (& mut self) -> INT_EVENT0_IMASK_DIO17_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio18 (& mut self) -> INT_EVENT0_IMASK_DIO18_W < INT_EVENT0_IMASK_SPEC , 18 > { INT_EVENT0_IMASK_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio19 (& mut self) -> INT_EVENT0_IMASK_DIO19_W < INT_EVENT0_IMASK_SPEC , 19 > { INT_EVENT0_IMASK_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio20 (& mut self) -> INT_EVENT0_IMASK_DIO20_W < INT_EVENT0_IMASK_SPEC , 20 > { INT_EVENT0_IMASK_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio21 (& mut self) -> INT_EVENT0_IMASK_DIO21_W < INT_EVENT0_IMASK_SPEC , 21 > { INT_EVENT0_IMASK_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio22 (& mut self) -> INT_EVENT0_IMASK_DIO22_W < INT_EVENT0_IMASK_SPEC , 22 > { INT_EVENT0_IMASK_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio23 (& mut self) -> INT_EVENT0_IMASK_DIO23_W < INT_EVENT0_IMASK_SPEC , 23 > { INT_EVENT0_IMASK_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio24 (& mut self) -> INT_EVENT0_IMASK_DIO24_W < INT_EVENT0_IMASK_SPEC , 24 > { INT_EVENT0_IMASK_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio25 (& mut self) -> INT_EVENT0_IMASK_DIO25_W < INT_EVENT0_IMASK_SPEC , 25 > { INT_EVENT0_IMASK_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio26 (& mut self) -> INT_EVENT0_IMASK_DIO26_W < INT_EVENT0_IMASK_SPEC , 26 > { INT_EVENT0_IMASK_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio27 (& mut self) -> INT_EVENT0_IMASK_DIO27_W < INT_EVENT0_IMASK_SPEC , 27 > { INT_EVENT0_IMASK_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio28 (& mut self) -> INT_EVENT0_IMASK_DIO28_W < INT_EVENT0_IMASK_SPEC , 28 > { INT_EVENT0_IMASK_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio29 (& mut self) -> INT_EVENT0_IMASK_DIO29_W < INT_EVENT0_IMASK_SPEC , 29 > { INT_EVENT0_IMASK_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio30 (& mut self) -> INT_EVENT0_IMASK_DIO30_W < INT_EVENT0_IMASK_SPEC , 30 > { INT_EVENT0_IMASK_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio31 (& mut self) -> INT_EVENT0_IMASK_DIO31_W < INT_EVENT0_IMASK_SPEC , 31 > { INT_EVENT0_IMASK_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg1/pwren.rs:1:3131 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PWREN` reader"] pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"] pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"] pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"] PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)] fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"] pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"] PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)] fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"] pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"] # [inline (always)] pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"] # [inline (always)] # [must_use] pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"] # [inline (always)] # [must_use] pub fn pwren_key (& mut self) -> PWREN_KEY_W <'_, PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"] impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"] impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"] impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/wwdt0/wwdtcntrst.rs:1:1378 [INFO] [stdout] | [INFO] [stdout] 1 | ... wwdtcntrst_restart (& mut self) -> WWDTCNTRST_RESTART_W < WWDTCNTRST_SPEC , 0 > { WWDTCNTRST_RESTART_W :: new (self) } # [doc = r" Wr... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `WWDTCNTRST` reader"] pub type R = crate :: R < WWDTCNTRST_SPEC > ; # [doc = "Register `WWDTCNTRST` writer"] pub type W = crate :: W < WWDTCNTRST_SPEC > ; # [doc = "Field `WWDTCNTRST_RESTART` reader - Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0."] pub type WWDTCNTRST_RESTART_R = crate :: FieldReader < u32 > ; # [doc = "Field `WWDTCNTRST_RESTART` writer - Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0."] pub type WWDTCNTRST_RESTART_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl R { # [doc = "Bits 0:31 - Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0."] # [inline (always)] pub fn wwdtcntrst_restart (& self) -> WWDTCNTRST_RESTART_R { WWDTCNTRST_RESTART_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0."] # [inline (always)] # [must_use] pub fn wwdtcntrst_restart (& mut self) -> WWDTCNTRST_RESTART_W <'_, WWDTCNTRST_SPEC , 0 > { WWDTCNTRST_RESTART_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Counter Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtcntrst::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtcntrst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WWDTCNTRST_SPEC ; impl crate :: RegisterSpec for WWDTCNTRST_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtcntrst::R`](R) reader structure"] impl crate :: Readable for WWDTCNTRST_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtcntrst::W`](W) writer structure"] impl crate :: Writable for WWDTCNTRST_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCNTRST to value 0"] impl crate :: Resettable for WWDTCNTRST_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mfifoctl.rs:1:12308 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W <'_, MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:35412 [INFO] [stdout] | [INFO] [stdout] 1 | ...nt0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W <'_, INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:42394 [INFO] [stdout] | [INFO] [stdout] 1 | ...t0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W <'_, INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/int_event0_imask.rs:1:66371 [INFO] [stdout] | [INFO] [stdout] 1 | ...nt0_imask_dio1 (& mut self) -> INT_EVENT0_IMASK_DIO1_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_DIO1_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_DIO0` reader - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_R = crate :: BitReader < INT_EVENT0_IMASK_DIO0_A > ; # [doc = "DIO0 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO0_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO0_A { match self . bits { false => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR , true => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio0_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO0` writer - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` reader - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_R = crate :: BitReader < INT_EVENT0_IMASK_DIO1_A > ; # [doc = "DIO1 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO1_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO1_A { match self . bits { false => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR , true => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio1_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` writer - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` reader - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_R = crate :: BitReader < INT_EVENT0_IMASK_DIO2_A > ; # [doc = "DIO2 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO2_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO2_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO2_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO2_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO2_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO2_A { match self . bits { false => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR , true => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio2_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` writer - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` reader - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_R = crate :: BitReader < INT_EVENT0_IMASK_DIO3_A > ; # [doc = "DIO3 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO3_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO3_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO3_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO3_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO3_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO3_A { match self . bits { false => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR , true => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio3_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` writer - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` reader - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_R = crate :: BitReader < INT_EVENT0_IMASK_DIO4_A > ; # [doc = "DIO4 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO4_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO4_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO4_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO4_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO4_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO4_A { match self . bits { false => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR , true => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio4_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio4_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` writer - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO4_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` reader - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_R = crate :: BitReader < INT_EVENT0_IMASK_DIO5_A > ; # [doc = "DIO5 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO5_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO5_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO5_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO5_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO5_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO5_A { match self . bits { false => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR , true => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio5_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio5_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` writer - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO5_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` reader - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_R = crate :: BitReader < INT_EVENT0_IMASK_DIO6_A > ; # [doc = "DIO6 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO6_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO6_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO6_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO6_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO6_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO6_A { match self . bits { false => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR , true => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio6_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio6_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` writer - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO6_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` reader - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_R = crate :: BitReader < INT_EVENT0_IMASK_DIO7_A > ; # [doc = "DIO7 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO7_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO7_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO7_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO7_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO7_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO7_A { match self . bits { false => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR , true => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio7_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio7_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` writer - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO7_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` reader - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_R = crate :: BitReader < INT_EVENT0_IMASK_DIO8_A > ; # [doc = "DIO8 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO8_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO8_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO8_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO8_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO8_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO8_A { match self . bits { false => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR , true => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio8_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio8_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` writer - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO8_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` reader - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_R = crate :: BitReader < INT_EVENT0_IMASK_DIO9_A > ; # [doc = "DIO9 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO9_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO9_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO9_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO9_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO9_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO9_A { match self . bits { false => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR , true => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio9_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio9_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` writer - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO9_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` reader - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_R = crate :: BitReader < INT_EVENT0_IMASK_DIO10_A > ; # [doc = "DIO10 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO10_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO10_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO10_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO10_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO10_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO10_A { match self . bits { false => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR , true => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio10_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio10_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` writer - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO10_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` reader - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_R = crate :: BitReader < INT_EVENT0_IMASK_DIO11_A > ; # [doc = "DIO11 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO11_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO11_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO11_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO11_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO11_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO11_A { match self . bits { false => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR , true => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio11_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio11_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` writer - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO11_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` reader - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_R = crate :: BitReader < INT_EVENT0_IMASK_DIO12_A > ; # [doc = "DIO12 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO12_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO12_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO12_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO12_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO12_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO12_A { match self . bits { false => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR , true => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio12_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio12_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` writer - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO12_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` reader - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_R = crate :: BitReader < INT_EVENT0_IMASK_DIO13_A > ; # [doc = "DIO13 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO13_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO13_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO13_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO13_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO13_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO13_A { match self . bits { false => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR , true => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio13_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio13_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` writer - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO13_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` reader - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_R = crate :: BitReader < INT_EVENT0_IMASK_DIO14_A > ; # [doc = "DIO14 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO14_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO14_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO14_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO14_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO14_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO14_A { match self . bits { false => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR , true => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio14_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio14_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` writer - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO14_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` reader - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_R = crate :: BitReader < INT_EVENT0_IMASK_DIO15_A > ; # [doc = "DIO15 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO15_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO15_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO15_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO15_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO15_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO15_A { match self . bits { false => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR , true => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio15_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio15_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` writer - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO15_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` reader - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_R = crate :: BitReader < INT_EVENT0_IMASK_DIO16_A > ; # [doc = "DIO16 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO16_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO16_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO16_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO16_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO16_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO16_A { match self . bits { false => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR , true => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio16_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio16_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` writer - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO16_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` reader - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_R = crate :: BitReader < INT_EVENT0_IMASK_DIO17_A > ; # [doc = "DIO17 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO17_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO17_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO17_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO17_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO17_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO17_A { match self . bits { false => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR , true => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio17_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio17_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` writer - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO17_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` reader - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_R = crate :: BitReader < INT_EVENT0_IMASK_DIO18_A > ; # [doc = "DIO18 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO18_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO18_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO18_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO18_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO18_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO18_A { match self . bits { false => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR , true => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio18_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio18_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` writer - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO18_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` reader - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_R = crate :: BitReader < INT_EVENT0_IMASK_DIO19_A > ; # [doc = "DIO19 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO19_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO19_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO19_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO19_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO19_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO19_A { match self . bits { false => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR , true => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio19_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio19_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` writer - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO19_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` reader - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_R = crate :: BitReader < INT_EVENT0_IMASK_DIO20_A > ; # [doc = "DIO20 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO20_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO20_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO20_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO20_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO20_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO20_A { match self . bits { false => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR , true => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio20_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio20_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` writer - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO20_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` reader - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_R = crate :: BitReader < INT_EVENT0_IMASK_DIO21_A > ; # [doc = "DIO21 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO21_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO21_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO21_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO21_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO21_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO21_A { match self . bits { false => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR , true => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio21_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio21_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` writer - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO21_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` reader - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_R = crate :: BitReader < INT_EVENT0_IMASK_DIO22_A > ; # [doc = "DIO22 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO22_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO22_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO22_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO22_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO22_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO22_A { match self . bits { false => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR , true => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio22_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio22_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` writer - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO22_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` reader - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_R = crate :: BitReader < INT_EVENT0_IMASK_DIO23_A > ; # [doc = "DIO23 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO23_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO23_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO23_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO23_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO23_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO23_A { match self . bits { false => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR , true => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio23_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio23_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` writer - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO23_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` reader - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_R = crate :: BitReader < INT_EVENT0_IMASK_DIO24_A > ; # [doc = "DIO24 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO24_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO24_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO24_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO24_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO24_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO24_A { match self . bits { false => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR , true => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio24_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio24_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` writer - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO24_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` reader - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_R = crate :: BitReader < INT_EVENT0_IMASK_DIO25_A > ; # [doc = "DIO25 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO25_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO25_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO25_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO25_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO25_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO25_A { match self . bits { false => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR , true => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio25_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio25_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` writer - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO25_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` reader - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_R = crate :: BitReader < INT_EVENT0_IMASK_DIO26_A > ; # [doc = "DIO26 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO26_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO26_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO26_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO26_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO26_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO26_A { match self . bits { false => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR , true => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio26_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio26_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` writer - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO26_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` reader - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_R = crate :: BitReader < INT_EVENT0_IMASK_DIO27_A > ; # [doc = "DIO27 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO27_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO27_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO27_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO27_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO27_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO27_A { match self . bits { false => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR , true => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio27_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio27_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` writer - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO27_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` reader - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_R = crate :: BitReader < INT_EVENT0_IMASK_DIO28_A > ; # [doc = "DIO28 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO28_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO28_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO28_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO28_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO28_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO28_A { match self . bits { false => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR , true => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio28_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio28_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` writer - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO28_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` reader - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_R = crate :: BitReader < INT_EVENT0_IMASK_DIO29_A > ; # [doc = "DIO29 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO29_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO29_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO29_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO29_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO29_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO29_A { match self . bits { false => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR , true => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio29_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio29_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` writer - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO29_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` reader - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_R = crate :: BitReader < INT_EVENT0_IMASK_DIO30_A > ; # [doc = "DIO30 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO30_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO30_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO30_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO30_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO30_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO30_A { match self . bits { false => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR , true => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio30_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio30_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` writer - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO30_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` reader - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_R = crate :: BitReader < INT_EVENT0_IMASK_DIO31_A > ; # [doc = "DIO31 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO31_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO31_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO31_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO31_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO31_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO31_A { match self . bits { false => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR , true => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio31_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio31_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` writer - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO31_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET) } } impl R { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] pub fn int_event0_imask_dio0 (& self) -> INT_EVENT0_IMASK_DIO0_R { INT_EVENT0_IMASK_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] pub fn int_event0_imask_dio1 (& self) -> INT_EVENT0_IMASK_DIO1_R { INT_EVENT0_IMASK_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] pub fn int_event0_imask_dio2 (& self) -> INT_EVENT0_IMASK_DIO2_R { INT_EVENT0_IMASK_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] pub fn int_event0_imask_dio3 (& self) -> INT_EVENT0_IMASK_DIO3_R { INT_EVENT0_IMASK_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] pub fn int_event0_imask_dio4 (& self) -> INT_EVENT0_IMASK_DIO4_R { INT_EVENT0_IMASK_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] pub fn int_event0_imask_dio5 (& self) -> INT_EVENT0_IMASK_DIO5_R { INT_EVENT0_IMASK_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] pub fn int_event0_imask_dio6 (& self) -> INT_EVENT0_IMASK_DIO6_R { INT_EVENT0_IMASK_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] pub fn int_event0_imask_dio7 (& self) -> INT_EVENT0_IMASK_DIO7_R { INT_EVENT0_IMASK_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] pub fn int_event0_imask_dio8 (& self) -> INT_EVENT0_IMASK_DIO8_R { INT_EVENT0_IMASK_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] pub fn int_event0_imask_dio9 (& self) -> INT_EVENT0_IMASK_DIO9_R { INT_EVENT0_IMASK_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] pub fn int_event0_imask_dio10 (& self) -> INT_EVENT0_IMASK_DIO10_R { INT_EVENT0_IMASK_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] pub fn int_event0_imask_dio11 (& self) -> INT_EVENT0_IMASK_DIO11_R { INT_EVENT0_IMASK_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] pub fn int_event0_imask_dio12 (& self) -> INT_EVENT0_IMASK_DIO12_R { INT_EVENT0_IMASK_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] pub fn int_event0_imask_dio13 (& self) -> INT_EVENT0_IMASK_DIO13_R { INT_EVENT0_IMASK_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] pub fn int_event0_imask_dio14 (& self) -> INT_EVENT0_IMASK_DIO14_R { INT_EVENT0_IMASK_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] pub fn int_event0_imask_dio15 (& self) -> INT_EVENT0_IMASK_DIO15_R { INT_EVENT0_IMASK_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] pub fn int_event0_imask_dio16 (& self) -> INT_EVENT0_IMASK_DIO16_R { INT_EVENT0_IMASK_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] pub fn int_event0_imask_dio17 (& self) -> INT_EVENT0_IMASK_DIO17_R { INT_EVENT0_IMASK_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] pub fn int_event0_imask_dio18 (& self) -> INT_EVENT0_IMASK_DIO18_R { INT_EVENT0_IMASK_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] pub fn int_event0_imask_dio19 (& self) -> INT_EVENT0_IMASK_DIO19_R { INT_EVENT0_IMASK_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] pub fn int_event0_imask_dio20 (& self) -> INT_EVENT0_IMASK_DIO20_R { INT_EVENT0_IMASK_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] pub fn int_event0_imask_dio21 (& self) -> INT_EVENT0_IMASK_DIO21_R { INT_EVENT0_IMASK_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] pub fn int_event0_imask_dio22 (& self) -> INT_EVENT0_IMASK_DIO22_R { INT_EVENT0_IMASK_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] pub fn int_event0_imask_dio23 (& self) -> INT_EVENT0_IMASK_DIO23_R { INT_EVENT0_IMASK_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] pub fn int_event0_imask_dio24 (& self) -> INT_EVENT0_IMASK_DIO24_R { INT_EVENT0_IMASK_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] pub fn int_event0_imask_dio25 (& self) -> INT_EVENT0_IMASK_DIO25_R { INT_EVENT0_IMASK_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] pub fn int_event0_imask_dio26 (& self) -> INT_EVENT0_IMASK_DIO26_R { INT_EVENT0_IMASK_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] pub fn int_event0_imask_dio27 (& self) -> INT_EVENT0_IMASK_DIO27_R { INT_EVENT0_IMASK_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] pub fn int_event0_imask_dio28 (& self) -> INT_EVENT0_IMASK_DIO28_R { INT_EVENT0_IMASK_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] pub fn int_event0_imask_dio29 (& self) -> INT_EVENT0_IMASK_DIO29_R { INT_EVENT0_IMASK_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] pub fn int_event0_imask_dio30 (& self) -> INT_EVENT0_IMASK_DIO30_R { INT_EVENT0_IMASK_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] pub fn int_event0_imask_dio31 (& self) -> INT_EVENT0_IMASK_DIO31_R { INT_EVENT0_IMASK_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio0 (& mut self) -> INT_EVENT0_IMASK_DIO0_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio1 (& mut self) -> INT_EVENT0_IMASK_DIO1_W <'_, INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio2 (& mut self) -> INT_EVENT0_IMASK_DIO2_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio3 (& mut self) -> INT_EVENT0_IMASK_DIO3_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio4 (& mut self) -> INT_EVENT0_IMASK_DIO4_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio5 (& mut self) -> INT_EVENT0_IMASK_DIO5_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio6 (& mut self) -> INT_EVENT0_IMASK_DIO6_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio7 (& mut self) -> INT_EVENT0_IMASK_DIO7_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio8 (& mut self) -> INT_EVENT0_IMASK_DIO8_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio9 (& mut self) -> INT_EVENT0_IMASK_DIO9_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio10 (& mut self) -> INT_EVENT0_IMASK_DIO10_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio11 (& mut self) -> INT_EVENT0_IMASK_DIO11_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio12 (& mut self) -> INT_EVENT0_IMASK_DIO12_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio13 (& mut self) -> INT_EVENT0_IMASK_DIO13_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio14 (& mut self) -> INT_EVENT0_IMASK_DIO14_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio15 (& mut self) -> INT_EVENT0_IMASK_DIO15_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DIO15_W :: new (self) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio16 (& mut self) -> INT_EVENT0_IMASK_DIO16_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio17 (& mut self) -> INT_EVENT0_IMASK_DIO17_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio18 (& mut self) -> INT_EVENT0_IMASK_DIO18_W < INT_EVENT0_IMASK_SPEC , 18 > { INT_EVENT0_IMASK_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio19 (& mut self) -> INT_EVENT0_IMASK_DIO19_W < INT_EVENT0_IMASK_SPEC , 19 > { INT_EVENT0_IMASK_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio20 (& mut self) -> INT_EVENT0_IMASK_DIO20_W < INT_EVENT0_IMASK_SPEC , 20 > { INT_EVENT0_IMASK_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio21 (& mut self) -> INT_EVENT0_IMASK_DIO21_W < INT_EVENT0_IMASK_SPEC , 21 > { INT_EVENT0_IMASK_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio22 (& mut self) -> INT_EVENT0_IMASK_DIO22_W < INT_EVENT0_IMASK_SPEC , 22 > { INT_EVENT0_IMASK_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio23 (& mut self) -> INT_EVENT0_IMASK_DIO23_W < INT_EVENT0_IMASK_SPEC , 23 > { INT_EVENT0_IMASK_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio24 (& mut self) -> INT_EVENT0_IMASK_DIO24_W < INT_EVENT0_IMASK_SPEC , 24 > { INT_EVENT0_IMASK_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio25 (& mut self) -> INT_EVENT0_IMASK_DIO25_W < INT_EVENT0_IMASK_SPEC , 25 > { INT_EVENT0_IMASK_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio26 (& mut self) -> INT_EVENT0_IMASK_DIO26_W < INT_EVENT0_IMASK_SPEC , 26 > { INT_EVENT0_IMASK_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio27 (& mut self) -> INT_EVENT0_IMASK_DIO27_W < INT_EVENT0_IMASK_SPEC , 27 > { INT_EVENT0_IMASK_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio28 (& mut self) -> INT_EVENT0_IMASK_DIO28_W < INT_EVENT0_IMASK_SPEC , 28 > { INT_EVENT0_IMASK_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio29 (& mut self) -> INT_EVENT0_IMASK_DIO29_W < INT_EVENT0_IMASK_SPEC , 29 > { INT_EVENT0_IMASK_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio30 (& mut self) -> INT_EVENT0_IMASK_DIO30_W < INT_EVENT0_IMASK_SPEC , 30 > { INT_EVENT0_IMASK_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio31 (& mut self) -> INT_EVENT0_IMASK_DIO31_W < INT_EVENT0_IMASK_SPEC , 31 > { INT_EVENT0_IMASK_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/debugss/imask.rs:1:7524 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn imask_txifg (& mut self) -> IMASK_TXIFG_W < IMASK_SPEC , 0 > { IMASK_TXIFG_W :: new (self) } # [doc = "Bit 1 - Masks RXI... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `IMASK` reader"] pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"] pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_TXIFG` reader - Masks TXIFG in MIS register"] pub type IMASK_TXIFG_R = crate :: BitReader < IMASK_TXIFG_A > ; # [doc = "Masks TXIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_TXIFG_A { # [doc = "0: CLR"] IMASK_TXIFG_CLR = 0 , # [doc = "1: SET"] IMASK_TXIFG_SET = 1 , } impl From < IMASK_TXIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_TXIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_TXIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_TXIFG_A { match self . bits { false => IMASK_TXIFG_A :: IMASK_TXIFG_CLR , true => IMASK_TXIFG_A :: IMASK_TXIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_txifg_clr (& self) -> bool { * self == IMASK_TXIFG_A :: IMASK_TXIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_txifg_set (& self) -> bool { * self == IMASK_TXIFG_A :: IMASK_TXIFG_SET } } # [doc = "Field `IMASK_TXIFG` writer - Masks TXIFG in MIS register"] pub type IMASK_TXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_TXIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_TXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_txifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TXIFG_A :: IMASK_TXIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_txifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TXIFG_A :: IMASK_TXIFG_SET) } } # [doc = "Field `IMASK_RXIFG` reader - Masks RXIFG in MIS register"] pub type IMASK_RXIFG_R = crate :: BitReader < IMASK_RXIFG_A > ; # [doc = "Masks RXIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_RXIFG_A { # [doc = "0: CLR"] IMASK_RXIFG_CLR = 0 , # [doc = "1: SET"] IMASK_RXIFG_SET = 1 , } impl From < IMASK_RXIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_RXIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_RXIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_RXIFG_A { match self . bits { false => IMASK_RXIFG_A :: IMASK_RXIFG_CLR , true => IMASK_RXIFG_A :: IMASK_RXIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_rxifg_clr (& self) -> bool { * self == IMASK_RXIFG_A :: IMASK_RXIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_rxifg_set (& self) -> bool { * self == IMASK_RXIFG_A :: IMASK_RXIFG_SET } } # [doc = "Field `IMASK_RXIFG` writer - Masks RXIFG in MIS register"] pub type IMASK_RXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_RXIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_RXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_rxifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_RXIFG_A :: IMASK_RXIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_rxifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_RXIFG_A :: IMASK_RXIFG_SET) } } # [doc = "Field `IMASK_PWRUPIFG` reader - Masks PWRUPIFG in MIS register"] pub type IMASK_PWRUPIFG_R = crate :: BitReader < IMASK_PWRUPIFG_A > ; # [doc = "Masks PWRUPIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_PWRUPIFG_A { # [doc = "0: CLR"] IMASK_PWRUPIFG_CLR = 0 , # [doc = "1: SET"] IMASK_PWRUPIFG_SET = 1 , } impl From < IMASK_PWRUPIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_PWRUPIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_PWRUPIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_PWRUPIFG_A { match self . bits { false => IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR , true => IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_pwrupifg_clr (& self) -> bool { * self == IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_pwrupifg_set (& self) -> bool { * self == IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET } } # [doc = "Field `IMASK_PWRUPIFG` writer - Masks PWRUPIFG in MIS register"] pub type IMASK_PWRUPIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_PWRUPIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_PWRUPIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_pwrupifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_pwrupifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET) } } # [doc = "Field `IMASK_PWRDWNIFG` reader - Masks PWRDWNIFG in MIS register"] pub type IMASK_PWRDWNIFG_R = crate :: BitReader < IMASK_PWRDWNIFG_A > ; # [doc = "Masks PWRDWNIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_PWRDWNIFG_A { # [doc = "0: CLR"] IMASK_PWRDWNIFG_CLR = 0 , # [doc = "1: SET"] IMASK_PWRDWNIFG_SET = 1 , } impl From < IMASK_PWRDWNIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_PWRDWNIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_PWRDWNIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_PWRDWNIFG_A { match self . bits { false => IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR , true => IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_pwrdwnifg_clr (& self) -> bool { * self == IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_pwrdwnifg_set (& self) -> bool { * self == IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET } } # [doc = "Field `IMASK_PWRDWNIFG` writer - Masks PWRDWNIFG in MIS register"] pub type IMASK_PWRDWNIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_PWRDWNIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_PWRDWNIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_pwrdwnifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_pwrdwnifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET) } } impl R { # [doc = "Bit 0 - Masks TXIFG in MIS register"] # [inline (always)] pub fn imask_txifg (& self) -> IMASK_TXIFG_R { IMASK_TXIFG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Masks RXIFG in MIS register"] # [inline (always)] pub fn imask_rxifg (& self) -> IMASK_RXIFG_R { IMASK_RXIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Masks PWRUPIFG in MIS register"] # [inline (always)] pub fn imask_pwrupifg (& self) -> IMASK_PWRUPIFG_R { IMASK_PWRUPIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Masks PWRDWNIFG in MIS register"] # [inline (always)] pub fn imask_pwrdwnifg (& self) -> IMASK_PWRDWNIFG_R { IMASK_PWRDWNIFG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Masks TXIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_txifg (& mut self) -> IMASK_TXIFG_W <'_, IMASK_SPEC , 0 > { IMASK_TXIFG_W :: new (self) } # [doc = "Bit 1 - Masks RXIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_rxifg (& mut self) -> IMASK_RXIFG_W < IMASK_SPEC , 1 > { IMASK_RXIFG_W :: new (self) } # [doc = "Bit 2 - Masks PWRUPIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_pwrupifg (& mut self) -> IMASK_PWRUPIFG_W < IMASK_SPEC , 2 > { IMASK_PWRUPIFG_W :: new (self) } # [doc = "Bit 3 - Masks PWRDWNIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_pwrdwnifg (& mut self) -> IMASK_PWRDWNIFG_W < IMASK_SPEC , 3 > { IMASK_PWRDWNIFG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"] impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"] impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"] impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:35639 [INFO] [stdout] | [INFO] [stdout] 1 | ...0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W <'_, INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/ctl0.rs:1:38596 [INFO] [stdout] | [INFO] [stdout] 1 | ...must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to S... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W <'_, CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:42640 [INFO] [stdout] | [INFO] [stdout] 1 | ..._imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W <'_, INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg1/rstctl.rs:1:3243 [INFO] [stdout] | [INFO] [stdout] 1 | ...fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W <'_, RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mfifoctl.rs:1:12656 [INFO] [stdout] | [INFO] [stdout] 1 | ...b fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:1... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W <'_, MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg1/rstctl.rs:1:3464 [INFO] [stdout] | [INFO] [stdout] 1 | ... rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W <'_, RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mfifoctl.rs:1:13018 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - R... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W <'_, MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:35870 [INFO] [stdout] | [INFO] [stdout] 1 | ...0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W <'_, INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/int_event0_imask.rs:1:66581 [INFO] [stdout] | [INFO] [stdout] 1 | ...nt0_imask_dio2 (& mut self) -> INT_EVENT0_IMASK_DIO2_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_DIO2_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_DIO0` reader - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_R = crate :: BitReader < INT_EVENT0_IMASK_DIO0_A > ; # [doc = "DIO0 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO0_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO0_A { match self . bits { false => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR , true => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio0_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO0` writer - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` reader - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_R = crate :: BitReader < INT_EVENT0_IMASK_DIO1_A > ; # [doc = "DIO1 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO1_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO1_A { match self . bits { false => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR , true => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio1_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` writer - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` reader - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_R = crate :: BitReader < INT_EVENT0_IMASK_DIO2_A > ; # [doc = "DIO2 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO2_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO2_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO2_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO2_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO2_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO2_A { match self . bits { false => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR , true => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio2_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` writer - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` reader - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_R = crate :: BitReader < INT_EVENT0_IMASK_DIO3_A > ; # [doc = "DIO3 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO3_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO3_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO3_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO3_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO3_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO3_A { match self . bits { false => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR , true => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio3_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` writer - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` reader - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_R = crate :: BitReader < INT_EVENT0_IMASK_DIO4_A > ; # [doc = "DIO4 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO4_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO4_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO4_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO4_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO4_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO4_A { match self . bits { false => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR , true => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio4_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio4_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` writer - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO4_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` reader - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_R = crate :: BitReader < INT_EVENT0_IMASK_DIO5_A > ; # [doc = "DIO5 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO5_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO5_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO5_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO5_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO5_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO5_A { match self . bits { false => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR , true => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio5_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio5_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` writer - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO5_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` reader - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_R = crate :: BitReader < INT_EVENT0_IMASK_DIO6_A > ; # [doc = "DIO6 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO6_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO6_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO6_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO6_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO6_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO6_A { match self . bits { false => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR , true => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio6_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio6_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` writer - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO6_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` reader - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_R = crate :: BitReader < INT_EVENT0_IMASK_DIO7_A > ; # [doc = "DIO7 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO7_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO7_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO7_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO7_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO7_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO7_A { match self . bits { false => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR , true => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio7_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio7_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` writer - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO7_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` reader - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_R = crate :: BitReader < INT_EVENT0_IMASK_DIO8_A > ; # [doc = "DIO8 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO8_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO8_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO8_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO8_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO8_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO8_A { match self . bits { false => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR , true => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio8_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio8_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` writer - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO8_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` reader - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_R = crate :: BitReader < INT_EVENT0_IMASK_DIO9_A > ; # [doc = "DIO9 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO9_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO9_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO9_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO9_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO9_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO9_A { match self . bits { false => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR , true => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio9_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio9_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` writer - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO9_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` reader - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_R = crate :: BitReader < INT_EVENT0_IMASK_DIO10_A > ; # [doc = "DIO10 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO10_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO10_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO10_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO10_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO10_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO10_A { match self . bits { false => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR , true => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio10_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio10_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` writer - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO10_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` reader - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_R = crate :: BitReader < INT_EVENT0_IMASK_DIO11_A > ; # [doc = "DIO11 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO11_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO11_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO11_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO11_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO11_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO11_A { match self . bits { false => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR , true => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio11_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio11_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` writer - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO11_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` reader - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_R = crate :: BitReader < INT_EVENT0_IMASK_DIO12_A > ; # [doc = "DIO12 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO12_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO12_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO12_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO12_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO12_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO12_A { match self . bits { false => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR , true => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio12_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio12_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` writer - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO12_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` reader - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_R = crate :: BitReader < INT_EVENT0_IMASK_DIO13_A > ; # [doc = "DIO13 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO13_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO13_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO13_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO13_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO13_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO13_A { match self . bits { false => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR , true => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio13_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio13_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` writer - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO13_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` reader - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_R = crate :: BitReader < INT_EVENT0_IMASK_DIO14_A > ; # [doc = "DIO14 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO14_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO14_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO14_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO14_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO14_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO14_A { match self . bits { false => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR , true => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio14_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio14_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` writer - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO14_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` reader - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_R = crate :: BitReader < INT_EVENT0_IMASK_DIO15_A > ; # [doc = "DIO15 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO15_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO15_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO15_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO15_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO15_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO15_A { match self . bits { false => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR , true => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio15_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio15_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` writer - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO15_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` reader - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_R = crate :: BitReader < INT_EVENT0_IMASK_DIO16_A > ; # [doc = "DIO16 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO16_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO16_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO16_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO16_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO16_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO16_A { match self . bits { false => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR , true => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio16_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio16_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` writer - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO16_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` reader - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_R = crate :: BitReader < INT_EVENT0_IMASK_DIO17_A > ; # [doc = "DIO17 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO17_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO17_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO17_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO17_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO17_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO17_A { match self . bits { false => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR , true => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio17_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio17_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` writer - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO17_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` reader - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_R = crate :: BitReader < INT_EVENT0_IMASK_DIO18_A > ; # [doc = "DIO18 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO18_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO18_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO18_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO18_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO18_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO18_A { match self . bits { false => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR , true => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio18_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio18_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` writer - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO18_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` reader - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_R = crate :: BitReader < INT_EVENT0_IMASK_DIO19_A > ; # [doc = "DIO19 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO19_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO19_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO19_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO19_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO19_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO19_A { match self . bits { false => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR , true => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio19_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio19_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` writer - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO19_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` reader - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_R = crate :: BitReader < INT_EVENT0_IMASK_DIO20_A > ; # [doc = "DIO20 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO20_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO20_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO20_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO20_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO20_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO20_A { match self . bits { false => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR , true => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio20_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio20_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` writer - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO20_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` reader - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_R = crate :: BitReader < INT_EVENT0_IMASK_DIO21_A > ; # [doc = "DIO21 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO21_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO21_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO21_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO21_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO21_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO21_A { match self . bits { false => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR , true => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio21_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio21_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` writer - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO21_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` reader - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_R = crate :: BitReader < INT_EVENT0_IMASK_DIO22_A > ; # [doc = "DIO22 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO22_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO22_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO22_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO22_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO22_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO22_A { match self . bits { false => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR , true => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio22_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio22_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` writer - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO22_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` reader - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_R = crate :: BitReader < INT_EVENT0_IMASK_DIO23_A > ; # [doc = "DIO23 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO23_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO23_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO23_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO23_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO23_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO23_A { match self . bits { false => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR , true => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio23_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio23_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` writer - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO23_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` reader - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_R = crate :: BitReader < INT_EVENT0_IMASK_DIO24_A > ; # [doc = "DIO24 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO24_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO24_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO24_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO24_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO24_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO24_A { match self . bits { false => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR , true => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio24_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio24_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` writer - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO24_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` reader - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_R = crate :: BitReader < INT_EVENT0_IMASK_DIO25_A > ; # [doc = "DIO25 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO25_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO25_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO25_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO25_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO25_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO25_A { match self . bits { false => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR , true => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio25_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio25_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` writer - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO25_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` reader - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_R = crate :: BitReader < INT_EVENT0_IMASK_DIO26_A > ; # [doc = "DIO26 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO26_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO26_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO26_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO26_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO26_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO26_A { match self . bits { false => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR , true => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio26_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio26_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` writer - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO26_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` reader - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_R = crate :: BitReader < INT_EVENT0_IMASK_DIO27_A > ; # [doc = "DIO27 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO27_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO27_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO27_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO27_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO27_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO27_A { match self . bits { false => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR , true => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio27_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio27_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` writer - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO27_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` reader - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_R = crate :: BitReader < INT_EVENT0_IMASK_DIO28_A > ; # [doc = "DIO28 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO28_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO28_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO28_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO28_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO28_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO28_A { match self . bits { false => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR , true => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio28_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio28_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` writer - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO28_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` reader - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_R = crate :: BitReader < INT_EVENT0_IMASK_DIO29_A > ; # [doc = "DIO29 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO29_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO29_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO29_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO29_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO29_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO29_A { match self . bits { false => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR , true => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio29_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio29_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` writer - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO29_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` reader - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_R = crate :: BitReader < INT_EVENT0_IMASK_DIO30_A > ; # [doc = "DIO30 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO30_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO30_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO30_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO30_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO30_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO30_A { match self . bits { false => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR , true => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio30_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio30_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` writer - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO30_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` reader - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_R = crate :: BitReader < INT_EVENT0_IMASK_DIO31_A > ; # [doc = "DIO31 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO31_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO31_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO31_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO31_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO31_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO31_A { match self . bits { false => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR , true => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio31_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio31_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` writer - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO31_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET) } } impl R { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] pub fn int_event0_imask_dio0 (& self) -> INT_EVENT0_IMASK_DIO0_R { INT_EVENT0_IMASK_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] pub fn int_event0_imask_dio1 (& self) -> INT_EVENT0_IMASK_DIO1_R { INT_EVENT0_IMASK_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] pub fn int_event0_imask_dio2 (& self) -> INT_EVENT0_IMASK_DIO2_R { INT_EVENT0_IMASK_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] pub fn int_event0_imask_dio3 (& self) -> INT_EVENT0_IMASK_DIO3_R { INT_EVENT0_IMASK_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] pub fn int_event0_imask_dio4 (& self) -> INT_EVENT0_IMASK_DIO4_R { INT_EVENT0_IMASK_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] pub fn int_event0_imask_dio5 (& self) -> INT_EVENT0_IMASK_DIO5_R { INT_EVENT0_IMASK_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] pub fn int_event0_imask_dio6 (& self) -> INT_EVENT0_IMASK_DIO6_R { INT_EVENT0_IMASK_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] pub fn int_event0_imask_dio7 (& self) -> INT_EVENT0_IMASK_DIO7_R { INT_EVENT0_IMASK_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] pub fn int_event0_imask_dio8 (& self) -> INT_EVENT0_IMASK_DIO8_R { INT_EVENT0_IMASK_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] pub fn int_event0_imask_dio9 (& self) -> INT_EVENT0_IMASK_DIO9_R { INT_EVENT0_IMASK_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] pub fn int_event0_imask_dio10 (& self) -> INT_EVENT0_IMASK_DIO10_R { INT_EVENT0_IMASK_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] pub fn int_event0_imask_dio11 (& self) -> INT_EVENT0_IMASK_DIO11_R { INT_EVENT0_IMASK_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] pub fn int_event0_imask_dio12 (& self) -> INT_EVENT0_IMASK_DIO12_R { INT_EVENT0_IMASK_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] pub fn int_event0_imask_dio13 (& self) -> INT_EVENT0_IMASK_DIO13_R { INT_EVENT0_IMASK_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] pub fn int_event0_imask_dio14 (& self) -> INT_EVENT0_IMASK_DIO14_R { INT_EVENT0_IMASK_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] pub fn int_event0_imask_dio15 (& self) -> INT_EVENT0_IMASK_DIO15_R { INT_EVENT0_IMASK_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] pub fn int_event0_imask_dio16 (& self) -> INT_EVENT0_IMASK_DIO16_R { INT_EVENT0_IMASK_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] pub fn int_event0_imask_dio17 (& self) -> INT_EVENT0_IMASK_DIO17_R { INT_EVENT0_IMASK_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] pub fn int_event0_imask_dio18 (& self) -> INT_EVENT0_IMASK_DIO18_R { INT_EVENT0_IMASK_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] pub fn int_event0_imask_dio19 (& self) -> INT_EVENT0_IMASK_DIO19_R { INT_EVENT0_IMASK_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] pub fn int_event0_imask_dio20 (& self) -> INT_EVENT0_IMASK_DIO20_R { INT_EVENT0_IMASK_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] pub fn int_event0_imask_dio21 (& self) -> INT_EVENT0_IMASK_DIO21_R { INT_EVENT0_IMASK_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] pub fn int_event0_imask_dio22 (& self) -> INT_EVENT0_IMASK_DIO22_R { INT_EVENT0_IMASK_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] pub fn int_event0_imask_dio23 (& self) -> INT_EVENT0_IMASK_DIO23_R { INT_EVENT0_IMASK_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] pub fn int_event0_imask_dio24 (& self) -> INT_EVENT0_IMASK_DIO24_R { INT_EVENT0_IMASK_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] pub fn int_event0_imask_dio25 (& self) -> INT_EVENT0_IMASK_DIO25_R { INT_EVENT0_IMASK_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] pub fn int_event0_imask_dio26 (& self) -> INT_EVENT0_IMASK_DIO26_R { INT_EVENT0_IMASK_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] pub fn int_event0_imask_dio27 (& self) -> INT_EVENT0_IMASK_DIO27_R { INT_EVENT0_IMASK_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] pub fn int_event0_imask_dio28 (& self) -> INT_EVENT0_IMASK_DIO28_R { INT_EVENT0_IMASK_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] pub fn int_event0_imask_dio29 (& self) -> INT_EVENT0_IMASK_DIO29_R { INT_EVENT0_IMASK_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] pub fn int_event0_imask_dio30 (& self) -> INT_EVENT0_IMASK_DIO30_R { INT_EVENT0_IMASK_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] pub fn int_event0_imask_dio31 (& self) -> INT_EVENT0_IMASK_DIO31_R { INT_EVENT0_IMASK_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio0 (& mut self) -> INT_EVENT0_IMASK_DIO0_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio1 (& mut self) -> INT_EVENT0_IMASK_DIO1_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio2 (& mut self) -> INT_EVENT0_IMASK_DIO2_W <'_, INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio3 (& mut self) -> INT_EVENT0_IMASK_DIO3_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio4 (& mut self) -> INT_EVENT0_IMASK_DIO4_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio5 (& mut self) -> INT_EVENT0_IMASK_DIO5_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio6 (& mut self) -> INT_EVENT0_IMASK_DIO6_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio7 (& mut self) -> INT_EVENT0_IMASK_DIO7_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio8 (& mut self) -> INT_EVENT0_IMASK_DIO8_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio9 (& mut self) -> INT_EVENT0_IMASK_DIO9_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio10 (& mut self) -> INT_EVENT0_IMASK_DIO10_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio11 (& mut self) -> INT_EVENT0_IMASK_DIO11_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio12 (& mut self) -> INT_EVENT0_IMASK_DIO12_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio13 (& mut self) -> INT_EVENT0_IMASK_DIO13_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio14 (& mut self) -> INT_EVENT0_IMASK_DIO14_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio15 (& mut self) -> INT_EVENT0_IMASK_DIO15_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DIO15_W :: new (self) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio16 (& mut self) -> INT_EVENT0_IMASK_DIO16_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio17 (& mut self) -> INT_EVENT0_IMASK_DIO17_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio18 (& mut self) -> INT_EVENT0_IMASK_DIO18_W < INT_EVENT0_IMASK_SPEC , 18 > { INT_EVENT0_IMASK_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio19 (& mut self) -> INT_EVENT0_IMASK_DIO19_W < INT_EVENT0_IMASK_SPEC , 19 > { INT_EVENT0_IMASK_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio20 (& mut self) -> INT_EVENT0_IMASK_DIO20_W < INT_EVENT0_IMASK_SPEC , 20 > { INT_EVENT0_IMASK_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio21 (& mut self) -> INT_EVENT0_IMASK_DIO21_W < INT_EVENT0_IMASK_SPEC , 21 > { INT_EVENT0_IMASK_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio22 (& mut self) -> INT_EVENT0_IMASK_DIO22_W < INT_EVENT0_IMASK_SPEC , 22 > { INT_EVENT0_IMASK_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio23 (& mut self) -> INT_EVENT0_IMASK_DIO23_W < INT_EVENT0_IMASK_SPEC , 23 > { INT_EVENT0_IMASK_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio24 (& mut self) -> INT_EVENT0_IMASK_DIO24_W < INT_EVENT0_IMASK_SPEC , 24 > { INT_EVENT0_IMASK_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio25 (& mut self) -> INT_EVENT0_IMASK_DIO25_W < INT_EVENT0_IMASK_SPEC , 25 > { INT_EVENT0_IMASK_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio26 (& mut self) -> INT_EVENT0_IMASK_DIO26_W < INT_EVENT0_IMASK_SPEC , 26 > { INT_EVENT0_IMASK_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio27 (& mut self) -> INT_EVENT0_IMASK_DIO27_W < INT_EVENT0_IMASK_SPEC , 27 > { INT_EVENT0_IMASK_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio28 (& mut self) -> INT_EVENT0_IMASK_DIO28_W < INT_EVENT0_IMASK_SPEC , 28 > { INT_EVENT0_IMASK_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio29 (& mut self) -> INT_EVENT0_IMASK_DIO29_W < INT_EVENT0_IMASK_SPEC , 29 > { INT_EVENT0_IMASK_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio30 (& mut self) -> INT_EVENT0_IMASK_DIO30_W < INT_EVENT0_IMASK_SPEC , 30 > { INT_EVENT0_IMASK_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio31 (& mut self) -> INT_EVENT0_IMASK_DIO31_W < INT_EVENT0_IMASK_SPEC , 31 > { INT_EVENT0_IMASK_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/debugss/imask.rs:1:7705 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn imask_rxifg (& mut self) -> IMASK_RXIFG_W < IMASK_SPEC , 1 > { IMASK_RXIFG_W :: new (self) } # [doc = "Bit 2 - Masks PWR... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `IMASK` reader"] pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"] pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_TXIFG` reader - Masks TXIFG in MIS register"] pub type IMASK_TXIFG_R = crate :: BitReader < IMASK_TXIFG_A > ; # [doc = "Masks TXIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_TXIFG_A { # [doc = "0: CLR"] IMASK_TXIFG_CLR = 0 , # [doc = "1: SET"] IMASK_TXIFG_SET = 1 , } impl From < IMASK_TXIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_TXIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_TXIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_TXIFG_A { match self . bits { false => IMASK_TXIFG_A :: IMASK_TXIFG_CLR , true => IMASK_TXIFG_A :: IMASK_TXIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_txifg_clr (& self) -> bool { * self == IMASK_TXIFG_A :: IMASK_TXIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_txifg_set (& self) -> bool { * self == IMASK_TXIFG_A :: IMASK_TXIFG_SET } } # [doc = "Field `IMASK_TXIFG` writer - Masks TXIFG in MIS register"] pub type IMASK_TXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_TXIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_TXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_txifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TXIFG_A :: IMASK_TXIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_txifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TXIFG_A :: IMASK_TXIFG_SET) } } # [doc = "Field `IMASK_RXIFG` reader - Masks RXIFG in MIS register"] pub type IMASK_RXIFG_R = crate :: BitReader < IMASK_RXIFG_A > ; # [doc = "Masks RXIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_RXIFG_A { # [doc = "0: CLR"] IMASK_RXIFG_CLR = 0 , # [doc = "1: SET"] IMASK_RXIFG_SET = 1 , } impl From < IMASK_RXIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_RXIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_RXIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_RXIFG_A { match self . bits { false => IMASK_RXIFG_A :: IMASK_RXIFG_CLR , true => IMASK_RXIFG_A :: IMASK_RXIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_rxifg_clr (& self) -> bool { * self == IMASK_RXIFG_A :: IMASK_RXIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_rxifg_set (& self) -> bool { * self == IMASK_RXIFG_A :: IMASK_RXIFG_SET } } # [doc = "Field `IMASK_RXIFG` writer - Masks RXIFG in MIS register"] pub type IMASK_RXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_RXIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_RXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_rxifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_RXIFG_A :: IMASK_RXIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_rxifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_RXIFG_A :: IMASK_RXIFG_SET) } } # [doc = "Field `IMASK_PWRUPIFG` reader - Masks PWRUPIFG in MIS register"] pub type IMASK_PWRUPIFG_R = crate :: BitReader < IMASK_PWRUPIFG_A > ; # [doc = "Masks PWRUPIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_PWRUPIFG_A { # [doc = "0: CLR"] IMASK_PWRUPIFG_CLR = 0 , # [doc = "1: SET"] IMASK_PWRUPIFG_SET = 1 , } impl From < IMASK_PWRUPIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_PWRUPIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_PWRUPIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_PWRUPIFG_A { match self . bits { false => IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR , true => IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_pwrupifg_clr (& self) -> bool { * self == IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_pwrupifg_set (& self) -> bool { * self == IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET } } # [doc = "Field `IMASK_PWRUPIFG` writer - Masks PWRUPIFG in MIS register"] pub type IMASK_PWRUPIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_PWRUPIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_PWRUPIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_pwrupifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_pwrupifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET) } } # [doc = "Field `IMASK_PWRDWNIFG` reader - Masks PWRDWNIFG in MIS register"] pub type IMASK_PWRDWNIFG_R = crate :: BitReader < IMASK_PWRDWNIFG_A > ; # [doc = "Masks PWRDWNIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_PWRDWNIFG_A { # [doc = "0: CLR"] IMASK_PWRDWNIFG_CLR = 0 , # [doc = "1: SET"] IMASK_PWRDWNIFG_SET = 1 , } impl From < IMASK_PWRDWNIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_PWRDWNIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_PWRDWNIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_PWRDWNIFG_A { match self . bits { false => IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR , true => IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_pwrdwnifg_clr (& self) -> bool { * self == IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_pwrdwnifg_set (& self) -> bool { * self == IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET } } # [doc = "Field `IMASK_PWRDWNIFG` writer - Masks PWRDWNIFG in MIS register"] pub type IMASK_PWRDWNIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_PWRDWNIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_PWRDWNIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_pwrdwnifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_pwrdwnifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET) } } impl R { # [doc = "Bit 0 - Masks TXIFG in MIS register"] # [inline (always)] pub fn imask_txifg (& self) -> IMASK_TXIFG_R { IMASK_TXIFG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Masks RXIFG in MIS register"] # [inline (always)] pub fn imask_rxifg (& self) -> IMASK_RXIFG_R { IMASK_RXIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Masks PWRUPIFG in MIS register"] # [inline (always)] pub fn imask_pwrupifg (& self) -> IMASK_PWRUPIFG_R { IMASK_PWRUPIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Masks PWRDWNIFG in MIS register"] # [inline (always)] pub fn imask_pwrdwnifg (& self) -> IMASK_PWRDWNIFG_R { IMASK_PWRDWNIFG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Masks TXIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_txifg (& mut self) -> IMASK_TXIFG_W < IMASK_SPEC , 0 > { IMASK_TXIFG_W :: new (self) } # [doc = "Bit 1 - Masks RXIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_rxifg (& mut self) -> IMASK_RXIFG_W <'_, IMASK_SPEC , 1 > { IMASK_RXIFG_W :: new (self) } # [doc = "Bit 2 - Masks PWRUPIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_pwrupifg (& mut self) -> IMASK_PWRUPIFG_W < IMASK_SPEC , 2 > { IMASK_PWRUPIFG_W :: new (self) } # [doc = "Bit 3 - Masks PWRDWNIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_pwrdwnifg (& mut self) -> IMASK_PWRDWNIFG_W < IMASK_SPEC , 3 > { IMASK_PWRDWNIFG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"] impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"] impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"] impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/ctl0.rs:1:39022 [INFO] [stdout] | [INFO] [stdout] 1 | ...[must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardwa... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W <'_, CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg1/rstctl.rs:1:3649 [INFO] [stdout] | [INFO] [stdout] 1 | ...t_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `RSTCTL` writer"] pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"] RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"] RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"] pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"] # [inline (always)] pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"] RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"] RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)] fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"] pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"] # [inline (always)] pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"] # [inline (always)] pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"] RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)] fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"] pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"] # [inline (always)] pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"] # [inline (always)] # [must_use] pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"] # [inline (always)] # [must_use] pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"] # [inline (always)] # [must_use] pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W <'_, RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"] impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"] impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:42871 [INFO] [stdout] | [INFO] [stdout] 1 | ...0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W <'_, INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/debugss/imask.rs:1:7892 [INFO] [stdout] | [INFO] [stdout] 1 | ...] pub fn imask_pwrupifg (& mut self) -> IMASK_PWRUPIFG_W < IMASK_SPEC , 2 > { IMASK_PWRUPIFG_W :: new (self) } # [doc = "Bit 3 - Masks... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `IMASK` reader"] pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"] pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_TXIFG` reader - Masks TXIFG in MIS register"] pub type IMASK_TXIFG_R = crate :: BitReader < IMASK_TXIFG_A > ; # [doc = "Masks TXIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_TXIFG_A { # [doc = "0: CLR"] IMASK_TXIFG_CLR = 0 , # [doc = "1: SET"] IMASK_TXIFG_SET = 1 , } impl From < IMASK_TXIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_TXIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_TXIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_TXIFG_A { match self . bits { false => IMASK_TXIFG_A :: IMASK_TXIFG_CLR , true => IMASK_TXIFG_A :: IMASK_TXIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_txifg_clr (& self) -> bool { * self == IMASK_TXIFG_A :: IMASK_TXIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_txifg_set (& self) -> bool { * self == IMASK_TXIFG_A :: IMASK_TXIFG_SET } } # [doc = "Field `IMASK_TXIFG` writer - Masks TXIFG in MIS register"] pub type IMASK_TXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_TXIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_TXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_txifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TXIFG_A :: IMASK_TXIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_txifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TXIFG_A :: IMASK_TXIFG_SET) } } # [doc = "Field `IMASK_RXIFG` reader - Masks RXIFG in MIS register"] pub type IMASK_RXIFG_R = crate :: BitReader < IMASK_RXIFG_A > ; # [doc = "Masks RXIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_RXIFG_A { # [doc = "0: CLR"] IMASK_RXIFG_CLR = 0 , # [doc = "1: SET"] IMASK_RXIFG_SET = 1 , } impl From < IMASK_RXIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_RXIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_RXIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_RXIFG_A { match self . bits { false => IMASK_RXIFG_A :: IMASK_RXIFG_CLR , true => IMASK_RXIFG_A :: IMASK_RXIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_rxifg_clr (& self) -> bool { * self == IMASK_RXIFG_A :: IMASK_RXIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_rxifg_set (& self) -> bool { * self == IMASK_RXIFG_A :: IMASK_RXIFG_SET } } # [doc = "Field `IMASK_RXIFG` writer - Masks RXIFG in MIS register"] pub type IMASK_RXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_RXIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_RXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_rxifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_RXIFG_A :: IMASK_RXIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_rxifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_RXIFG_A :: IMASK_RXIFG_SET) } } # [doc = "Field `IMASK_PWRUPIFG` reader - Masks PWRUPIFG in MIS register"] pub type IMASK_PWRUPIFG_R = crate :: BitReader < IMASK_PWRUPIFG_A > ; # [doc = "Masks PWRUPIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_PWRUPIFG_A { # [doc = "0: CLR"] IMASK_PWRUPIFG_CLR = 0 , # [doc = "1: SET"] IMASK_PWRUPIFG_SET = 1 , } impl From < IMASK_PWRUPIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_PWRUPIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_PWRUPIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_PWRUPIFG_A { match self . bits { false => IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR , true => IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_pwrupifg_clr (& self) -> bool { * self == IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_pwrupifg_set (& self) -> bool { * self == IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET } } # [doc = "Field `IMASK_PWRUPIFG` writer - Masks PWRUPIFG in MIS register"] pub type IMASK_PWRUPIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_PWRUPIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_PWRUPIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_pwrupifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_pwrupifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET) } } # [doc = "Field `IMASK_PWRDWNIFG` reader - Masks PWRDWNIFG in MIS register"] pub type IMASK_PWRDWNIFG_R = crate :: BitReader < IMASK_PWRDWNIFG_A > ; # [doc = "Masks PWRDWNIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_PWRDWNIFG_A { # [doc = "0: CLR"] IMASK_PWRDWNIFG_CLR = 0 , # [doc = "1: SET"] IMASK_PWRDWNIFG_SET = 1 , } impl From < IMASK_PWRDWNIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_PWRDWNIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_PWRDWNIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_PWRDWNIFG_A { match self . bits { false => IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR , true => IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_pwrdwnifg_clr (& self) -> bool { * self == IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_pwrdwnifg_set (& self) -> bool { * self == IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET } } # [doc = "Field `IMASK_PWRDWNIFG` writer - Masks PWRDWNIFG in MIS register"] pub type IMASK_PWRDWNIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_PWRDWNIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_PWRDWNIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_pwrdwnifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_pwrdwnifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET) } } impl R { # [doc = "Bit 0 - Masks TXIFG in MIS register"] # [inline (always)] pub fn imask_txifg (& self) -> IMASK_TXIFG_R { IMASK_TXIFG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Masks RXIFG in MIS register"] # [inline (always)] pub fn imask_rxifg (& self) -> IMASK_RXIFG_R { IMASK_RXIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Masks PWRUPIFG in MIS register"] # [inline (always)] pub fn imask_pwrupifg (& self) -> IMASK_PWRUPIFG_R { IMASK_PWRUPIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Masks PWRDWNIFG in MIS register"] # [inline (always)] pub fn imask_pwrdwnifg (& self) -> IMASK_PWRDWNIFG_R { IMASK_PWRDWNIFG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Masks TXIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_txifg (& mut self) -> IMASK_TXIFG_W < IMASK_SPEC , 0 > { IMASK_TXIFG_W :: new (self) } # [doc = "Bit 1 - Masks RXIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_rxifg (& mut self) -> IMASK_RXIFG_W < IMASK_SPEC , 1 > { IMASK_RXIFG_W :: new (self) } # [doc = "Bit 2 - Masks PWRUPIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_pwrupifg (& mut self) -> IMASK_PWRUPIFG_W <'_, IMASK_SPEC , 2 > { IMASK_PWRUPIFG_W :: new (self) } # [doc = "Bit 3 - Masks PWRDWNIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_pwrdwnifg (& mut self) -> IMASK_PWRDWNIFG_W < IMASK_SPEC , 3 > { IMASK_PWRDWNIFG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"] impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"] impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"] impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/mfifoctl.rs:1:13367 [INFO] [stdout] | [INFO] [stdout] 1 | ... fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MFIFOCTL` reader"] pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"] pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"] MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"] MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"] MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"] MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"] # [inline (always)] pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"] MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"] MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"] MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"] MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)] fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"] # [inline (always)] pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"] # [inline (always)] pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"] # [inline (always)] pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"] # [inline (always)] pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"] # [inline (always)] pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"] MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"] MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)] fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"] # [inline (always)] pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"] # [inline (always)] pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."] # [inline (always)] # [must_use] pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."] # [inline (always)] # [must_use] pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."] # [inline (always)] # [must_use] pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W <'_, MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"] impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"] impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"] impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/int_event0_imask.rs:1:66791 [INFO] [stdout] | [INFO] [stdout] 1 | ...nt0_imask_dio3 (& mut self) -> INT_EVENT0_IMASK_DIO3_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_DIO3_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_DIO0` reader - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_R = crate :: BitReader < INT_EVENT0_IMASK_DIO0_A > ; # [doc = "DIO0 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO0_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO0_A { match self . bits { false => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR , true => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio0_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO0` writer - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` reader - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_R = crate :: BitReader < INT_EVENT0_IMASK_DIO1_A > ; # [doc = "DIO1 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO1_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO1_A { match self . bits { false => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR , true => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio1_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` writer - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` reader - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_R = crate :: BitReader < INT_EVENT0_IMASK_DIO2_A > ; # [doc = "DIO2 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO2_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO2_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO2_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO2_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO2_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO2_A { match self . bits { false => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR , true => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio2_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` writer - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` reader - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_R = crate :: BitReader < INT_EVENT0_IMASK_DIO3_A > ; # [doc = "DIO3 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO3_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO3_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO3_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO3_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO3_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO3_A { match self . bits { false => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR , true => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio3_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` writer - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` reader - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_R = crate :: BitReader < INT_EVENT0_IMASK_DIO4_A > ; # [doc = "DIO4 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO4_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO4_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO4_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO4_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO4_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO4_A { match self . bits { false => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR , true => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio4_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio4_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` writer - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO4_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` reader - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_R = crate :: BitReader < INT_EVENT0_IMASK_DIO5_A > ; # [doc = "DIO5 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO5_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO5_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO5_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO5_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO5_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO5_A { match self . bits { false => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR , true => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio5_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio5_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` writer - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO5_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` reader - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_R = crate :: BitReader < INT_EVENT0_IMASK_DIO6_A > ; # [doc = "DIO6 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO6_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO6_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO6_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO6_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO6_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO6_A { match self . bits { false => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR , true => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio6_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio6_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` writer - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO6_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` reader - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_R = crate :: BitReader < INT_EVENT0_IMASK_DIO7_A > ; # [doc = "DIO7 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO7_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO7_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO7_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO7_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO7_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO7_A { match self . bits { false => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR , true => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio7_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio7_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` writer - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO7_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` reader - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_R = crate :: BitReader < INT_EVENT0_IMASK_DIO8_A > ; # [doc = "DIO8 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO8_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO8_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO8_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO8_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO8_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO8_A { match self . bits { false => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR , true => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio8_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio8_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` writer - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO8_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` reader - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_R = crate :: BitReader < INT_EVENT0_IMASK_DIO9_A > ; # [doc = "DIO9 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO9_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO9_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO9_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO9_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO9_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO9_A { match self . bits { false => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR , true => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio9_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio9_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` writer - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO9_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` reader - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_R = crate :: BitReader < INT_EVENT0_IMASK_DIO10_A > ; # [doc = "DIO10 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO10_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO10_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO10_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO10_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO10_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO10_A { match self . bits { false => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR , true => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio10_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio10_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` writer - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO10_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` reader - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_R = crate :: BitReader < INT_EVENT0_IMASK_DIO11_A > ; # [doc = "DIO11 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO11_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO11_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO11_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO11_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO11_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO11_A { match self . bits { false => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR , true => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio11_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio11_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` writer - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO11_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` reader - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_R = crate :: BitReader < INT_EVENT0_IMASK_DIO12_A > ; # [doc = "DIO12 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO12_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO12_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO12_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO12_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO12_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO12_A { match self . bits { false => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR , true => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio12_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio12_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` writer - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO12_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` reader - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_R = crate :: BitReader < INT_EVENT0_IMASK_DIO13_A > ; # [doc = "DIO13 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO13_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO13_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO13_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO13_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO13_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO13_A { match self . bits { false => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR , true => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio13_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio13_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` writer - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO13_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` reader - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_R = crate :: BitReader < INT_EVENT0_IMASK_DIO14_A > ; # [doc = "DIO14 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO14_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO14_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO14_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO14_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO14_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO14_A { match self . bits { false => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR , true => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio14_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio14_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` writer - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO14_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` reader - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_R = crate :: BitReader < INT_EVENT0_IMASK_DIO15_A > ; # [doc = "DIO15 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO15_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO15_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO15_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO15_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO15_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO15_A { match self . bits { false => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR , true => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio15_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio15_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` writer - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO15_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` reader - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_R = crate :: BitReader < INT_EVENT0_IMASK_DIO16_A > ; # [doc = "DIO16 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO16_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO16_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO16_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO16_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO16_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO16_A { match self . bits { false => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR , true => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio16_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio16_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` writer - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO16_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` reader - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_R = crate :: BitReader < INT_EVENT0_IMASK_DIO17_A > ; # [doc = "DIO17 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO17_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO17_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO17_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO17_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO17_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO17_A { match self . bits { false => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR , true => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio17_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio17_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` writer - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO17_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` reader - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_R = crate :: BitReader < INT_EVENT0_IMASK_DIO18_A > ; # [doc = "DIO18 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO18_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO18_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO18_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO18_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO18_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO18_A { match self . bits { false => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR , true => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio18_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio18_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` writer - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO18_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` reader - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_R = crate :: BitReader < INT_EVENT0_IMASK_DIO19_A > ; # [doc = "DIO19 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO19_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO19_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO19_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO19_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO19_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO19_A { match self . bits { false => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR , true => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio19_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio19_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` writer - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO19_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` reader - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_R = crate :: BitReader < INT_EVENT0_IMASK_DIO20_A > ; # [doc = "DIO20 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO20_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO20_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO20_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO20_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO20_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO20_A { match self . bits { false => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR , true => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio20_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio20_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` writer - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO20_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` reader - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_R = crate :: BitReader < INT_EVENT0_IMASK_DIO21_A > ; # [doc = "DIO21 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO21_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO21_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO21_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO21_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO21_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO21_A { match self . bits { false => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR , true => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio21_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio21_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` writer - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO21_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` reader - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_R = crate :: BitReader < INT_EVENT0_IMASK_DIO22_A > ; # [doc = "DIO22 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO22_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO22_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO22_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO22_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO22_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO22_A { match self . bits { false => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR , true => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio22_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio22_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` writer - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO22_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` reader - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_R = crate :: BitReader < INT_EVENT0_IMASK_DIO23_A > ; # [doc = "DIO23 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO23_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO23_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO23_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO23_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO23_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO23_A { match self . bits { false => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR , true => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio23_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio23_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` writer - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO23_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` reader - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_R = crate :: BitReader < INT_EVENT0_IMASK_DIO24_A > ; # [doc = "DIO24 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO24_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO24_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO24_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO24_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO24_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO24_A { match self . bits { false => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR , true => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio24_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio24_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` writer - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO24_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` reader - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_R = crate :: BitReader < INT_EVENT0_IMASK_DIO25_A > ; # [doc = "DIO25 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO25_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO25_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO25_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO25_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO25_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO25_A { match self . bits { false => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR , true => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio25_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio25_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` writer - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO25_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` reader - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_R = crate :: BitReader < INT_EVENT0_IMASK_DIO26_A > ; # [doc = "DIO26 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO26_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO26_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO26_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO26_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO26_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO26_A { match self . bits { false => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR , true => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio26_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio26_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` writer - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO26_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` reader - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_R = crate :: BitReader < INT_EVENT0_IMASK_DIO27_A > ; # [doc = "DIO27 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO27_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO27_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO27_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO27_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO27_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO27_A { match self . bits { false => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR , true => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio27_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio27_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` writer - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO27_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` reader - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_R = crate :: BitReader < INT_EVENT0_IMASK_DIO28_A > ; # [doc = "DIO28 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO28_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO28_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO28_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO28_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO28_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO28_A { match self . bits { false => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR , true => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio28_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio28_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` writer - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO28_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` reader - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_R = crate :: BitReader < INT_EVENT0_IMASK_DIO29_A > ; # [doc = "DIO29 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO29_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO29_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO29_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO29_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO29_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO29_A { match self . bits { false => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR , true => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio29_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio29_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` writer - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO29_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` reader - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_R = crate :: BitReader < INT_EVENT0_IMASK_DIO30_A > ; # [doc = "DIO30 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO30_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO30_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO30_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO30_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO30_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO30_A { match self . bits { false => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR , true => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio30_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio30_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` writer - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO30_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` reader - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_R = crate :: BitReader < INT_EVENT0_IMASK_DIO31_A > ; # [doc = "DIO31 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO31_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO31_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO31_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO31_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO31_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO31_A { match self . bits { false => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR , true => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio31_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio31_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` writer - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO31_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET) } } impl R { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] pub fn int_event0_imask_dio0 (& self) -> INT_EVENT0_IMASK_DIO0_R { INT_EVENT0_IMASK_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] pub fn int_event0_imask_dio1 (& self) -> INT_EVENT0_IMASK_DIO1_R { INT_EVENT0_IMASK_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] pub fn int_event0_imask_dio2 (& self) -> INT_EVENT0_IMASK_DIO2_R { INT_EVENT0_IMASK_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] pub fn int_event0_imask_dio3 (& self) -> INT_EVENT0_IMASK_DIO3_R { INT_EVENT0_IMASK_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] pub fn int_event0_imask_dio4 (& self) -> INT_EVENT0_IMASK_DIO4_R { INT_EVENT0_IMASK_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] pub fn int_event0_imask_dio5 (& self) -> INT_EVENT0_IMASK_DIO5_R { INT_EVENT0_IMASK_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] pub fn int_event0_imask_dio6 (& self) -> INT_EVENT0_IMASK_DIO6_R { INT_EVENT0_IMASK_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] pub fn int_event0_imask_dio7 (& self) -> INT_EVENT0_IMASK_DIO7_R { INT_EVENT0_IMASK_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] pub fn int_event0_imask_dio8 (& self) -> INT_EVENT0_IMASK_DIO8_R { INT_EVENT0_IMASK_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] pub fn int_event0_imask_dio9 (& self) -> INT_EVENT0_IMASK_DIO9_R { INT_EVENT0_IMASK_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] pub fn int_event0_imask_dio10 (& self) -> INT_EVENT0_IMASK_DIO10_R { INT_EVENT0_IMASK_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] pub fn int_event0_imask_dio11 (& self) -> INT_EVENT0_IMASK_DIO11_R { INT_EVENT0_IMASK_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] pub fn int_event0_imask_dio12 (& self) -> INT_EVENT0_IMASK_DIO12_R { INT_EVENT0_IMASK_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] pub fn int_event0_imask_dio13 (& self) -> INT_EVENT0_IMASK_DIO13_R { INT_EVENT0_IMASK_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] pub fn int_event0_imask_dio14 (& self) -> INT_EVENT0_IMASK_DIO14_R { INT_EVENT0_IMASK_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] pub fn int_event0_imask_dio15 (& self) -> INT_EVENT0_IMASK_DIO15_R { INT_EVENT0_IMASK_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] pub fn int_event0_imask_dio16 (& self) -> INT_EVENT0_IMASK_DIO16_R { INT_EVENT0_IMASK_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] pub fn int_event0_imask_dio17 (& self) -> INT_EVENT0_IMASK_DIO17_R { INT_EVENT0_IMASK_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] pub fn int_event0_imask_dio18 (& self) -> INT_EVENT0_IMASK_DIO18_R { INT_EVENT0_IMASK_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] pub fn int_event0_imask_dio19 (& self) -> INT_EVENT0_IMASK_DIO19_R { INT_EVENT0_IMASK_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] pub fn int_event0_imask_dio20 (& self) -> INT_EVENT0_IMASK_DIO20_R { INT_EVENT0_IMASK_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] pub fn int_event0_imask_dio21 (& self) -> INT_EVENT0_IMASK_DIO21_R { INT_EVENT0_IMASK_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] pub fn int_event0_imask_dio22 (& self) -> INT_EVENT0_IMASK_DIO22_R { INT_EVENT0_IMASK_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] pub fn int_event0_imask_dio23 (& self) -> INT_EVENT0_IMASK_DIO23_R { INT_EVENT0_IMASK_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] pub fn int_event0_imask_dio24 (& self) -> INT_EVENT0_IMASK_DIO24_R { INT_EVENT0_IMASK_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] pub fn int_event0_imask_dio25 (& self) -> INT_EVENT0_IMASK_DIO25_R { INT_EVENT0_IMASK_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] pub fn int_event0_imask_dio26 (& self) -> INT_EVENT0_IMASK_DIO26_R { INT_EVENT0_IMASK_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] pub fn int_event0_imask_dio27 (& self) -> INT_EVENT0_IMASK_DIO27_R { INT_EVENT0_IMASK_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] pub fn int_event0_imask_dio28 (& self) -> INT_EVENT0_IMASK_DIO28_R { INT_EVENT0_IMASK_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] pub fn int_event0_imask_dio29 (& self) -> INT_EVENT0_IMASK_DIO29_R { INT_EVENT0_IMASK_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] pub fn int_event0_imask_dio30 (& self) -> INT_EVENT0_IMASK_DIO30_R { INT_EVENT0_IMASK_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] pub fn int_event0_imask_dio31 (& self) -> INT_EVENT0_IMASK_DIO31_R { INT_EVENT0_IMASK_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio0 (& mut self) -> INT_EVENT0_IMASK_DIO0_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio1 (& mut self) -> INT_EVENT0_IMASK_DIO1_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio2 (& mut self) -> INT_EVENT0_IMASK_DIO2_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio3 (& mut self) -> INT_EVENT0_IMASK_DIO3_W <'_, INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio4 (& mut self) -> INT_EVENT0_IMASK_DIO4_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio5 (& mut self) -> INT_EVENT0_IMASK_DIO5_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio6 (& mut self) -> INT_EVENT0_IMASK_DIO6_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio7 (& mut self) -> INT_EVENT0_IMASK_DIO7_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio8 (& mut self) -> INT_EVENT0_IMASK_DIO8_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio9 (& mut self) -> INT_EVENT0_IMASK_DIO9_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio10 (& mut self) -> INT_EVENT0_IMASK_DIO10_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio11 (& mut self) -> INT_EVENT0_IMASK_DIO11_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio12 (& mut self) -> INT_EVENT0_IMASK_DIO12_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio13 (& mut self) -> INT_EVENT0_IMASK_DIO13_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio14 (& mut self) -> INT_EVENT0_IMASK_DIO14_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio15 (& mut self) -> INT_EVENT0_IMASK_DIO15_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DIO15_W :: new (self) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio16 (& mut self) -> INT_EVENT0_IMASK_DIO16_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio17 (& mut self) -> INT_EVENT0_IMASK_DIO17_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio18 (& mut self) -> INT_EVENT0_IMASK_DIO18_W < INT_EVENT0_IMASK_SPEC , 18 > { INT_EVENT0_IMASK_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio19 (& mut self) -> INT_EVENT0_IMASK_DIO19_W < INT_EVENT0_IMASK_SPEC , 19 > { INT_EVENT0_IMASK_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio20 (& mut self) -> INT_EVENT0_IMASK_DIO20_W < INT_EVENT0_IMASK_SPEC , 20 > { INT_EVENT0_IMASK_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio21 (& mut self) -> INT_EVENT0_IMASK_DIO21_W < INT_EVENT0_IMASK_SPEC , 21 > { INT_EVENT0_IMASK_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio22 (& mut self) -> INT_EVENT0_IMASK_DIO22_W < INT_EVENT0_IMASK_SPEC , 22 > { INT_EVENT0_IMASK_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio23 (& mut self) -> INT_EVENT0_IMASK_DIO23_W < INT_EVENT0_IMASK_SPEC , 23 > { INT_EVENT0_IMASK_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio24 (& mut self) -> INT_EVENT0_IMASK_DIO24_W < INT_EVENT0_IMASK_SPEC , 24 > { INT_EVENT0_IMASK_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio25 (& mut self) -> INT_EVENT0_IMASK_DIO25_W < INT_EVENT0_IMASK_SPEC , 25 > { INT_EVENT0_IMASK_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio26 (& mut self) -> INT_EVENT0_IMASK_DIO26_W < INT_EVENT0_IMASK_SPEC , 26 > { INT_EVENT0_IMASK_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio27 (& mut self) -> INT_EVENT0_IMASK_DIO27_W < INT_EVENT0_IMASK_SPEC , 27 > { INT_EVENT0_IMASK_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio28 (& mut self) -> INT_EVENT0_IMASK_DIO28_W < INT_EVENT0_IMASK_SPEC , 28 > { INT_EVENT0_IMASK_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio29 (& mut self) -> INT_EVENT0_IMASK_DIO29_W < INT_EVENT0_IMASK_SPEC , 29 > { INT_EVENT0_IMASK_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio30 (& mut self) -> INT_EVENT0_IMASK_DIO30_W < INT_EVENT0_IMASK_SPEC , 30 > { INT_EVENT0_IMASK_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio31 (& mut self) -> INT_EVENT0_IMASK_DIO31_W < INT_EVENT0_IMASK_SPEC , 31 > { INT_EVENT0_IMASK_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg1/clkdiv.rs:1:4791 [INFO] [stdout] | [INFO] [stdout] 1 | ...use] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bi... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKDIV` reader"] pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"] pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"] CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"] CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"] CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"] CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"] CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"] CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"] CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"] CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)] fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"] # [inline (always)] pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"] pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"] # [inline (always)] pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"] # [inline (always)] pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"] # [inline (always)] pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"] # [inline (always)] pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"] # [inline (always)] pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"] # [inline (always)] pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"] # [inline (always)] pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"] # [inline (always)] pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"] # [inline (always)] # [must_use] pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W <'_, CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"] impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"] impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"] impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/ctl0.rs:1:39212 [INFO] [stdout] | [INFO] [stdout] 1 | ...st_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Cle... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W <'_, CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:36250 [INFO] [stdout] | [INFO] [stdout] 1 | ...ent0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc =... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W <'_, INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:43102 [INFO] [stdout] | [INFO] [stdout] 1 | ...0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W <'_, INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/master_i2cpecctl.rs:1:9830 [INFO] [stdout] | [INFO] [stdout] 1 | ...pecctl_peccnt (& mut self) -> MASTER_I2CPECCTL_PECCNT_W < MASTER_I2CPECCTL_SPEC , 0 > { MASTER_I2CPECCTL_PECCNT_W :: new (self) } # [d... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MASTER_I2CPECCTL` reader"] pub type R = crate :: R < MASTER_I2CPECCTL_SPEC > ; # [doc = "Register `MASTER_I2CPECCTL` writer"] pub type W = crate :: W < MASTER_I2CPECCTL_SPEC > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` reader - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` writer - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 9 , O , u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECEN` reader - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_R = crate :: BitReader < MASTER_I2CPECCTL_PECEN_A > ; # [doc = "PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MASTER_I2CPECCTL_PECEN_A { # [doc = "0: DISABLE"] MASTER_I2CPECCTL_PECEN_DISABLE = 0 , # [doc = "1: ENABLE"] MASTER_I2CPECCTL_PECEN_ENABLE = 1 , } impl From < MASTER_I2CPECCTL_PECEN_A > for bool { # [inline (always)] fn from (variant : MASTER_I2CPECCTL_PECEN_A) -> Self { variant as u8 != 0 } } impl MASTER_I2CPECCTL_PECEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MASTER_I2CPECCTL_PECEN_A { match self . bits { false => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE , true => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_disable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_enable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE } } # [doc = "Field `MASTER_I2CPECCTL_PECEN` writer - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MASTER_I2CPECCTL_PECEN_A > ; impl < 'a , REG , const O : u8 > MASTER_I2CPECCTL_PECEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE) } } impl R { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] pub fn master_i2cpecctl_peccnt (& self) -> MASTER_I2CPECCTL_PECCNT_R { MASTER_I2CPECCTL_PECCNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] pub fn master_i2cpecctl_pecen (& self) -> MASTER_I2CPECCTL_PECEN_R { MASTER_I2CPECCTL_PECEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_peccnt (& mut self) -> MASTER_I2CPECCTL_PECCNT_W <'_, MASTER_I2CPECCTL_SPEC , 0 > { MASTER_I2CPECCTL_PECCNT_W :: new (self) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_pecen (& mut self) -> MASTER_I2CPECCTL_PECEN_W < MASTER_I2CPECCTL_SPEC , 12 > { MASTER_I2CPECCTL_PECEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C master PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_i2cpecctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`master_i2cpecctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MASTER_I2CPECCTL_SPEC ; impl crate :: RegisterSpec for MASTER_I2CPECCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`master_i2cpecctl::R`](R) reader structure"] impl crate :: Readable for MASTER_I2CPECCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`master_i2cpecctl::W`](W) writer structure"] impl crate :: Writable for MASTER_I2CPECCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MASTER_I2CPECCTL to value 0"] impl crate :: Resettable for MASTER_I2CPECCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/ctl0.rs:1:39384 [INFO] [stdout] | [INFO] [stdout] 1 | ...st_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-S... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W <'_, CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/debugss/imask.rs:1:8087 [INFO] [stdout] | [INFO] [stdout] 1 | ... pub fn imask_pwrdwnifg (& mut self) -> IMASK_PWRDWNIFG_W < IMASK_SPEC , 3 > { IMASK_PWRDWNIFG_W :: new (self) } # [doc = r" Writes ra... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `IMASK` reader"] pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"] pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_TXIFG` reader - Masks TXIFG in MIS register"] pub type IMASK_TXIFG_R = crate :: BitReader < IMASK_TXIFG_A > ; # [doc = "Masks TXIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_TXIFG_A { # [doc = "0: CLR"] IMASK_TXIFG_CLR = 0 , # [doc = "1: SET"] IMASK_TXIFG_SET = 1 , } impl From < IMASK_TXIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_TXIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_TXIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_TXIFG_A { match self . bits { false => IMASK_TXIFG_A :: IMASK_TXIFG_CLR , true => IMASK_TXIFG_A :: IMASK_TXIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_txifg_clr (& self) -> bool { * self == IMASK_TXIFG_A :: IMASK_TXIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_txifg_set (& self) -> bool { * self == IMASK_TXIFG_A :: IMASK_TXIFG_SET } } # [doc = "Field `IMASK_TXIFG` writer - Masks TXIFG in MIS register"] pub type IMASK_TXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_TXIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_TXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_txifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TXIFG_A :: IMASK_TXIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_txifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TXIFG_A :: IMASK_TXIFG_SET) } } # [doc = "Field `IMASK_RXIFG` reader - Masks RXIFG in MIS register"] pub type IMASK_RXIFG_R = crate :: BitReader < IMASK_RXIFG_A > ; # [doc = "Masks RXIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_RXIFG_A { # [doc = "0: CLR"] IMASK_RXIFG_CLR = 0 , # [doc = "1: SET"] IMASK_RXIFG_SET = 1 , } impl From < IMASK_RXIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_RXIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_RXIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_RXIFG_A { match self . bits { false => IMASK_RXIFG_A :: IMASK_RXIFG_CLR , true => IMASK_RXIFG_A :: IMASK_RXIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_rxifg_clr (& self) -> bool { * self == IMASK_RXIFG_A :: IMASK_RXIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_rxifg_set (& self) -> bool { * self == IMASK_RXIFG_A :: IMASK_RXIFG_SET } } # [doc = "Field `IMASK_RXIFG` writer - Masks RXIFG in MIS register"] pub type IMASK_RXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_RXIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_RXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_rxifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_RXIFG_A :: IMASK_RXIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_rxifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_RXIFG_A :: IMASK_RXIFG_SET) } } # [doc = "Field `IMASK_PWRUPIFG` reader - Masks PWRUPIFG in MIS register"] pub type IMASK_PWRUPIFG_R = crate :: BitReader < IMASK_PWRUPIFG_A > ; # [doc = "Masks PWRUPIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_PWRUPIFG_A { # [doc = "0: CLR"] IMASK_PWRUPIFG_CLR = 0 , # [doc = "1: SET"] IMASK_PWRUPIFG_SET = 1 , } impl From < IMASK_PWRUPIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_PWRUPIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_PWRUPIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_PWRUPIFG_A { match self . bits { false => IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR , true => IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_pwrupifg_clr (& self) -> bool { * self == IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_pwrupifg_set (& self) -> bool { * self == IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET } } # [doc = "Field `IMASK_PWRUPIFG` writer - Masks PWRUPIFG in MIS register"] pub type IMASK_PWRUPIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_PWRUPIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_PWRUPIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_pwrupifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_pwrupifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET) } } # [doc = "Field `IMASK_PWRDWNIFG` reader - Masks PWRDWNIFG in MIS register"] pub type IMASK_PWRDWNIFG_R = crate :: BitReader < IMASK_PWRDWNIFG_A > ; # [doc = "Masks PWRDWNIFG in MIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum IMASK_PWRDWNIFG_A { # [doc = "0: CLR"] IMASK_PWRDWNIFG_CLR = 0 , # [doc = "1: SET"] IMASK_PWRDWNIFG_SET = 1 , } impl From < IMASK_PWRDWNIFG_A > for bool { # [inline (always)] fn from (variant : IMASK_PWRDWNIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_PWRDWNIFG_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> IMASK_PWRDWNIFG_A { match self . bits { false => IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR , true => IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_imask_pwrdwnifg_clr (& self) -> bool { * self == IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR } # [doc = "SET"] # [inline (always)] pub fn is_imask_pwrdwnifg_set (& self) -> bool { * self == IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET } } # [doc = "Field `IMASK_PWRDWNIFG` writer - Masks PWRDWNIFG in MIS register"] pub type IMASK_PWRDWNIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_PWRDWNIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_PWRDWNIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn imask_pwrdwnifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR) } # [doc = "SET"] # [inline (always)] pub fn imask_pwrdwnifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET) } } impl R { # [doc = "Bit 0 - Masks TXIFG in MIS register"] # [inline (always)] pub fn imask_txifg (& self) -> IMASK_TXIFG_R { IMASK_TXIFG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Masks RXIFG in MIS register"] # [inline (always)] pub fn imask_rxifg (& self) -> IMASK_RXIFG_R { IMASK_RXIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Masks PWRUPIFG in MIS register"] # [inline (always)] pub fn imask_pwrupifg (& self) -> IMASK_PWRUPIFG_R { IMASK_PWRUPIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Masks PWRDWNIFG in MIS register"] # [inline (always)] pub fn imask_pwrdwnifg (& self) -> IMASK_PWRDWNIFG_R { IMASK_PWRDWNIFG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Masks TXIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_txifg (& mut self) -> IMASK_TXIFG_W < IMASK_SPEC , 0 > { IMASK_TXIFG_W :: new (self) } # [doc = "Bit 1 - Masks RXIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_rxifg (& mut self) -> IMASK_RXIFG_W < IMASK_SPEC , 1 > { IMASK_RXIFG_W :: new (self) } # [doc = "Bit 2 - Masks PWRUPIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_pwrupifg (& mut self) -> IMASK_PWRUPIFG_W < IMASK_SPEC , 2 > { IMASK_PWRUPIFG_W :: new (self) } # [doc = "Bit 3 - Masks PWRDWNIFG in MIS register"] # [inline (always)] # [must_use] pub fn imask_pwrdwnifg (& mut self) -> IMASK_PWRDWNIFG_W <'_, IMASK_SPEC , 3 > { IMASK_PWRDWNIFG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"] impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"] impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"] impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/master_i2cpecctl.rs:1:10529 [INFO] [stdout] | [INFO] [stdout] 1 | ...cpecctl_pecen (& mut self) -> MASTER_I2CPECCTL_PECEN_W < MASTER_I2CPECCTL_SPEC , 12 > { MASTER_I2CPECCTL_PECEN_W :: new (self) } # [do... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `MASTER_I2CPECCTL` reader"] pub type R = crate :: R < MASTER_I2CPECCTL_SPEC > ; # [doc = "Register `MASTER_I2CPECCTL` writer"] pub type W = crate :: W < MASTER_I2CPECCTL_SPEC > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` reader - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` writer - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] pub type MASTER_I2CPECCTL_PECCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 9 , O , u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECEN` reader - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_R = crate :: BitReader < MASTER_I2CPECCTL_PECEN_A > ; # [doc = "PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MASTER_I2CPECCTL_PECEN_A { # [doc = "0: DISABLE"] MASTER_I2CPECCTL_PECEN_DISABLE = 0 , # [doc = "1: ENABLE"] MASTER_I2CPECCTL_PECEN_ENABLE = 1 , } impl From < MASTER_I2CPECCTL_PECEN_A > for bool { # [inline (always)] fn from (variant : MASTER_I2CPECCTL_PECEN_A) -> Self { variant as u8 != 0 } } impl MASTER_I2CPECCTL_PECEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MASTER_I2CPECCTL_PECEN_A { match self . bits { false => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE , true => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_disable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_master_i2cpecctl_pecen_enable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE } } # [doc = "Field `MASTER_I2CPECCTL_PECEN` writer - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] pub type MASTER_I2CPECCTL_PECEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MASTER_I2CPECCTL_PECEN_A > ; impl < 'a , REG , const O : u8 > MASTER_I2CPECCTL_PECEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn master_i2cpecctl_pecen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE) } } impl R { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] pub fn master_i2cpecctl_peccnt (& self) -> MASTER_I2CPECCTL_PECCNT_R { MASTER_I2CPECCTL_PECCNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] pub fn master_i2cpecctl_pecen (& self) -> MASTER_I2CPECCTL_PECEN_R { MASTER_I2CPECCTL_PECEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_peccnt (& mut self) -> MASTER_I2CPECCTL_PECCNT_W < MASTER_I2CPECCTL_SPEC , 0 > { MASTER_I2CPECCTL_PECCNT_W :: new (self) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."] # [inline (always)] # [must_use] pub fn master_i2cpecctl_pecen (& mut self) -> MASTER_I2CPECCTL_PECEN_W <'_, MASTER_I2CPECCTL_SPEC , 12 > { MASTER_I2CPECCTL_PECEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C master PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_i2cpecctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`master_i2cpecctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MASTER_I2CPECCTL_SPEC ; impl crate :: RegisterSpec for MASTER_I2CPECCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`master_i2cpecctl::R`](R) reader structure"] impl crate :: Readable for MASTER_I2CPECCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`master_i2cpecctl::W`](W) writer structure"] impl crate :: Writable for MASTER_I2CPECCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MASTER_I2CPECCTL to value 0"] impl crate :: Resettable for MASTER_I2CPECCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/int_event0_imask.rs:1:67001 [INFO] [stdout] | [INFO] [stdout] 1 | ...nt0_imask_dio4 (& mut self) -> INT_EVENT0_IMASK_DIO4_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_DIO4_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_DIO0` reader - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_R = crate :: BitReader < INT_EVENT0_IMASK_DIO0_A > ; # [doc = "DIO0 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO0_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO0_A { match self . bits { false => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR , true => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio0_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO0` writer - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` reader - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_R = crate :: BitReader < INT_EVENT0_IMASK_DIO1_A > ; # [doc = "DIO1 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO1_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO1_A { match self . bits { false => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR , true => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio1_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` writer - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` reader - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_R = crate :: BitReader < INT_EVENT0_IMASK_DIO2_A > ; # [doc = "DIO2 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO2_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO2_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO2_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO2_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO2_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO2_A { match self . bits { false => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR , true => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio2_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` writer - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` reader - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_R = crate :: BitReader < INT_EVENT0_IMASK_DIO3_A > ; # [doc = "DIO3 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO3_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO3_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO3_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO3_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO3_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO3_A { match self . bits { false => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR , true => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio3_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` writer - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` reader - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_R = crate :: BitReader < INT_EVENT0_IMASK_DIO4_A > ; # [doc = "DIO4 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO4_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO4_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO4_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO4_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO4_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO4_A { match self . bits { false => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR , true => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio4_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio4_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` writer - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO4_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` reader - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_R = crate :: BitReader < INT_EVENT0_IMASK_DIO5_A > ; # [doc = "DIO5 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO5_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO5_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO5_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO5_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO5_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO5_A { match self . bits { false => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR , true => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio5_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio5_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` writer - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO5_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` reader - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_R = crate :: BitReader < INT_EVENT0_IMASK_DIO6_A > ; # [doc = "DIO6 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO6_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO6_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO6_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO6_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO6_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO6_A { match self . bits { false => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR , true => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio6_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio6_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` writer - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO6_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` reader - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_R = crate :: BitReader < INT_EVENT0_IMASK_DIO7_A > ; # [doc = "DIO7 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO7_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO7_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO7_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO7_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO7_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO7_A { match self . bits { false => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR , true => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio7_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio7_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` writer - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO7_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` reader - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_R = crate :: BitReader < INT_EVENT0_IMASK_DIO8_A > ; # [doc = "DIO8 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO8_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO8_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO8_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO8_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO8_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO8_A { match self . bits { false => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR , true => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio8_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio8_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` writer - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO8_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` reader - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_R = crate :: BitReader < INT_EVENT0_IMASK_DIO9_A > ; # [doc = "DIO9 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO9_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO9_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO9_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO9_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO9_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO9_A { match self . bits { false => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR , true => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio9_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio9_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` writer - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO9_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` reader - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_R = crate :: BitReader < INT_EVENT0_IMASK_DIO10_A > ; # [doc = "DIO10 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO10_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO10_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO10_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO10_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO10_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO10_A { match self . bits { false => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR , true => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio10_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio10_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` writer - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO10_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` reader - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_R = crate :: BitReader < INT_EVENT0_IMASK_DIO11_A > ; # [doc = "DIO11 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO11_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO11_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO11_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO11_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO11_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO11_A { match self . bits { false => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR , true => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio11_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio11_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` writer - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO11_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` reader - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_R = crate :: BitReader < INT_EVENT0_IMASK_DIO12_A > ; # [doc = "DIO12 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO12_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO12_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO12_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO12_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO12_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO12_A { match self . bits { false => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR , true => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio12_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio12_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` writer - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO12_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` reader - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_R = crate :: BitReader < INT_EVENT0_IMASK_DIO13_A > ; # [doc = "DIO13 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO13_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO13_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO13_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO13_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO13_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO13_A { match self . bits { false => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR , true => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio13_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio13_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` writer - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO13_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` reader - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_R = crate :: BitReader < INT_EVENT0_IMASK_DIO14_A > ; # [doc = "DIO14 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO14_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO14_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO14_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO14_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO14_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO14_A { match self . bits { false => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR , true => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio14_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio14_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` writer - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO14_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` reader - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_R = crate :: BitReader < INT_EVENT0_IMASK_DIO15_A > ; # [doc = "DIO15 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO15_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO15_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO15_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO15_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO15_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO15_A { match self . bits { false => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR , true => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio15_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio15_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` writer - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO15_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` reader - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_R = crate :: BitReader < INT_EVENT0_IMASK_DIO16_A > ; # [doc = "DIO16 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO16_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO16_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO16_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO16_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO16_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO16_A { match self . bits { false => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR , true => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio16_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio16_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` writer - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO16_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` reader - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_R = crate :: BitReader < INT_EVENT0_IMASK_DIO17_A > ; # [doc = "DIO17 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO17_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO17_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO17_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO17_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO17_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO17_A { match self . bits { false => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR , true => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio17_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio17_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` writer - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO17_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` reader - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_R = crate :: BitReader < INT_EVENT0_IMASK_DIO18_A > ; # [doc = "DIO18 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO18_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO18_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO18_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO18_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO18_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO18_A { match self . bits { false => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR , true => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio18_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio18_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` writer - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO18_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` reader - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_R = crate :: BitReader < INT_EVENT0_IMASK_DIO19_A > ; # [doc = "DIO19 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO19_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO19_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO19_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO19_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO19_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO19_A { match self . bits { false => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR , true => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio19_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio19_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` writer - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO19_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` reader - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_R = crate :: BitReader < INT_EVENT0_IMASK_DIO20_A > ; # [doc = "DIO20 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO20_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO20_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO20_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO20_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO20_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO20_A { match self . bits { false => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR , true => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio20_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio20_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` writer - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO20_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` reader - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_R = crate :: BitReader < INT_EVENT0_IMASK_DIO21_A > ; # [doc = "DIO21 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO21_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO21_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO21_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO21_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO21_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO21_A { match self . bits { false => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR , true => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio21_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio21_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` writer - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO21_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` reader - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_R = crate :: BitReader < INT_EVENT0_IMASK_DIO22_A > ; # [doc = "DIO22 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO22_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO22_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO22_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO22_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO22_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO22_A { match self . bits { false => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR , true => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio22_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio22_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` writer - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO22_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` reader - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_R = crate :: BitReader < INT_EVENT0_IMASK_DIO23_A > ; # [doc = "DIO23 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO23_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO23_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO23_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO23_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO23_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO23_A { match self . bits { false => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR , true => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio23_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio23_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` writer - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO23_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` reader - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_R = crate :: BitReader < INT_EVENT0_IMASK_DIO24_A > ; # [doc = "DIO24 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO24_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO24_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO24_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO24_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO24_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO24_A { match self . bits { false => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR , true => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio24_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio24_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` writer - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO24_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` reader - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_R = crate :: BitReader < INT_EVENT0_IMASK_DIO25_A > ; # [doc = "DIO25 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO25_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO25_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO25_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO25_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO25_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO25_A { match self . bits { false => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR , true => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio25_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio25_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` writer - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO25_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` reader - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_R = crate :: BitReader < INT_EVENT0_IMASK_DIO26_A > ; # [doc = "DIO26 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO26_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO26_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO26_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO26_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO26_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO26_A { match self . bits { false => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR , true => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio26_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio26_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` writer - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO26_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` reader - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_R = crate :: BitReader < INT_EVENT0_IMASK_DIO27_A > ; # [doc = "DIO27 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO27_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO27_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO27_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO27_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO27_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO27_A { match self . bits { false => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR , true => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio27_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio27_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` writer - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO27_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` reader - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_R = crate :: BitReader < INT_EVENT0_IMASK_DIO28_A > ; # [doc = "DIO28 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO28_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO28_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO28_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO28_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO28_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO28_A { match self . bits { false => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR , true => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio28_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio28_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` writer - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO28_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` reader - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_R = crate :: BitReader < INT_EVENT0_IMASK_DIO29_A > ; # [doc = "DIO29 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO29_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO29_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO29_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO29_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO29_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO29_A { match self . bits { false => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR , true => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio29_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio29_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` writer - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO29_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` reader - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_R = crate :: BitReader < INT_EVENT0_IMASK_DIO30_A > ; # [doc = "DIO30 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO30_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO30_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO30_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO30_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO30_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO30_A { match self . bits { false => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR , true => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio30_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio30_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` writer - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO30_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` reader - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_R = crate :: BitReader < INT_EVENT0_IMASK_DIO31_A > ; # [doc = "DIO31 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO31_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO31_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO31_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO31_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO31_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO31_A { match self . bits { false => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR , true => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio31_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio31_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` writer - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO31_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET) } } impl R { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] pub fn int_event0_imask_dio0 (& self) -> INT_EVENT0_IMASK_DIO0_R { INT_EVENT0_IMASK_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] pub fn int_event0_imask_dio1 (& self) -> INT_EVENT0_IMASK_DIO1_R { INT_EVENT0_IMASK_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] pub fn int_event0_imask_dio2 (& self) -> INT_EVENT0_IMASK_DIO2_R { INT_EVENT0_IMASK_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] pub fn int_event0_imask_dio3 (& self) -> INT_EVENT0_IMASK_DIO3_R { INT_EVENT0_IMASK_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] pub fn int_event0_imask_dio4 (& self) -> INT_EVENT0_IMASK_DIO4_R { INT_EVENT0_IMASK_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] pub fn int_event0_imask_dio5 (& self) -> INT_EVENT0_IMASK_DIO5_R { INT_EVENT0_IMASK_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] pub fn int_event0_imask_dio6 (& self) -> INT_EVENT0_IMASK_DIO6_R { INT_EVENT0_IMASK_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] pub fn int_event0_imask_dio7 (& self) -> INT_EVENT0_IMASK_DIO7_R { INT_EVENT0_IMASK_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] pub fn int_event0_imask_dio8 (& self) -> INT_EVENT0_IMASK_DIO8_R { INT_EVENT0_IMASK_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] pub fn int_event0_imask_dio9 (& self) -> INT_EVENT0_IMASK_DIO9_R { INT_EVENT0_IMASK_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] pub fn int_event0_imask_dio10 (& self) -> INT_EVENT0_IMASK_DIO10_R { INT_EVENT0_IMASK_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] pub fn int_event0_imask_dio11 (& self) -> INT_EVENT0_IMASK_DIO11_R { INT_EVENT0_IMASK_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] pub fn int_event0_imask_dio12 (& self) -> INT_EVENT0_IMASK_DIO12_R { INT_EVENT0_IMASK_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] pub fn int_event0_imask_dio13 (& self) -> INT_EVENT0_IMASK_DIO13_R { INT_EVENT0_IMASK_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] pub fn int_event0_imask_dio14 (& self) -> INT_EVENT0_IMASK_DIO14_R { INT_EVENT0_IMASK_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] pub fn int_event0_imask_dio15 (& self) -> INT_EVENT0_IMASK_DIO15_R { INT_EVENT0_IMASK_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] pub fn int_event0_imask_dio16 (& self) -> INT_EVENT0_IMASK_DIO16_R { INT_EVENT0_IMASK_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] pub fn int_event0_imask_dio17 (& self) -> INT_EVENT0_IMASK_DIO17_R { INT_EVENT0_IMASK_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] pub fn int_event0_imask_dio18 (& self) -> INT_EVENT0_IMASK_DIO18_R { INT_EVENT0_IMASK_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] pub fn int_event0_imask_dio19 (& self) -> INT_EVENT0_IMASK_DIO19_R { INT_EVENT0_IMASK_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] pub fn int_event0_imask_dio20 (& self) -> INT_EVENT0_IMASK_DIO20_R { INT_EVENT0_IMASK_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] pub fn int_event0_imask_dio21 (& self) -> INT_EVENT0_IMASK_DIO21_R { INT_EVENT0_IMASK_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] pub fn int_event0_imask_dio22 (& self) -> INT_EVENT0_IMASK_DIO22_R { INT_EVENT0_IMASK_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] pub fn int_event0_imask_dio23 (& self) -> INT_EVENT0_IMASK_DIO23_R { INT_EVENT0_IMASK_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] pub fn int_event0_imask_dio24 (& self) -> INT_EVENT0_IMASK_DIO24_R { INT_EVENT0_IMASK_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] pub fn int_event0_imask_dio25 (& self) -> INT_EVENT0_IMASK_DIO25_R { INT_EVENT0_IMASK_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] pub fn int_event0_imask_dio26 (& self) -> INT_EVENT0_IMASK_DIO26_R { INT_EVENT0_IMASK_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] pub fn int_event0_imask_dio27 (& self) -> INT_EVENT0_IMASK_DIO27_R { INT_EVENT0_IMASK_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] pub fn int_event0_imask_dio28 (& self) -> INT_EVENT0_IMASK_DIO28_R { INT_EVENT0_IMASK_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] pub fn int_event0_imask_dio29 (& self) -> INT_EVENT0_IMASK_DIO29_R { INT_EVENT0_IMASK_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] pub fn int_event0_imask_dio30 (& self) -> INT_EVENT0_IMASK_DIO30_R { INT_EVENT0_IMASK_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] pub fn int_event0_imask_dio31 (& self) -> INT_EVENT0_IMASK_DIO31_R { INT_EVENT0_IMASK_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio0 (& mut self) -> INT_EVENT0_IMASK_DIO0_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio1 (& mut self) -> INT_EVENT0_IMASK_DIO1_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio2 (& mut self) -> INT_EVENT0_IMASK_DIO2_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio3 (& mut self) -> INT_EVENT0_IMASK_DIO3_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio4 (& mut self) -> INT_EVENT0_IMASK_DIO4_W <'_, INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio5 (& mut self) -> INT_EVENT0_IMASK_DIO5_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio6 (& mut self) -> INT_EVENT0_IMASK_DIO6_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio7 (& mut self) -> INT_EVENT0_IMASK_DIO7_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio8 (& mut self) -> INT_EVENT0_IMASK_DIO8_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio9 (& mut self) -> INT_EVENT0_IMASK_DIO9_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio10 (& mut self) -> INT_EVENT0_IMASK_DIO10_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio11 (& mut self) -> INT_EVENT0_IMASK_DIO11_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio12 (& mut self) -> INT_EVENT0_IMASK_DIO12_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio13 (& mut self) -> INT_EVENT0_IMASK_DIO13_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio14 (& mut self) -> INT_EVENT0_IMASK_DIO14_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio15 (& mut self) -> INT_EVENT0_IMASK_DIO15_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DIO15_W :: new (self) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio16 (& mut self) -> INT_EVENT0_IMASK_DIO16_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio17 (& mut self) -> INT_EVENT0_IMASK_DIO17_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio18 (& mut self) -> INT_EVENT0_IMASK_DIO18_W < INT_EVENT0_IMASK_SPEC , 18 > { INT_EVENT0_IMASK_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio19 (& mut self) -> INT_EVENT0_IMASK_DIO19_W < INT_EVENT0_IMASK_SPEC , 19 > { INT_EVENT0_IMASK_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio20 (& mut self) -> INT_EVENT0_IMASK_DIO20_W < INT_EVENT0_IMASK_SPEC , 20 > { INT_EVENT0_IMASK_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio21 (& mut self) -> INT_EVENT0_IMASK_DIO21_W < INT_EVENT0_IMASK_SPEC , 21 > { INT_EVENT0_IMASK_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio22 (& mut self) -> INT_EVENT0_IMASK_DIO22_W < INT_EVENT0_IMASK_SPEC , 22 > { INT_EVENT0_IMASK_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio23 (& mut self) -> INT_EVENT0_IMASK_DIO23_W < INT_EVENT0_IMASK_SPEC , 23 > { INT_EVENT0_IMASK_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio24 (& mut self) -> INT_EVENT0_IMASK_DIO24_W < INT_EVENT0_IMASK_SPEC , 24 > { INT_EVENT0_IMASK_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio25 (& mut self) -> INT_EVENT0_IMASK_DIO25_W < INT_EVENT0_IMASK_SPEC , 25 > { INT_EVENT0_IMASK_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio26 (& mut self) -> INT_EVENT0_IMASK_DIO26_W < INT_EVENT0_IMASK_SPEC , 26 > { INT_EVENT0_IMASK_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio27 (& mut self) -> INT_EVENT0_IMASK_DIO27_W < INT_EVENT0_IMASK_SPEC , 27 > { INT_EVENT0_IMASK_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio28 (& mut self) -> INT_EVENT0_IMASK_DIO28_W < INT_EVENT0_IMASK_SPEC , 28 > { INT_EVENT0_IMASK_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio29 (& mut self) -> INT_EVENT0_IMASK_DIO29_W < INT_EVENT0_IMASK_SPEC , 29 > { INT_EVENT0_IMASK_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio30 (& mut self) -> INT_EVENT0_IMASK_DIO30_W < INT_EVENT0_IMASK_SPEC , 30 > { INT_EVENT0_IMASK_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio31 (& mut self) -> INT_EVENT0_IMASK_DIO31_W < INT_EVENT0_IMASK_SPEC , 31 > { INT_EVENT0_IMASK_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:43482 [INFO] [stdout] | [INFO] [stdout] 1 | ...ent0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc =... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W <'_, INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:36482 [INFO] [stdout] | [INFO] [stdout] 1 | ..._addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self)... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W <'_, INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/timg1/clksel.rs:1:6422 [INFO] [stdout] | [INFO] [stdout] 1 | ...ub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - S... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUSCLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUSCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUSCLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W <'_, CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/debugss/iset.rs:1:4175 [INFO] [stdout] | [INFO] [stdout] 1 | ...ust_use] pub fn iset_txifg (& mut self) -> ISET_TXIFG_W < ISET_SPEC , 0 > { ISET_TXIFG_W :: new (self) } # [doc = "Bit 1 - Sets RXIFG ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ISET` writer"] pub type W = crate :: W < ISET_SPEC > ; # [doc = "Sets TXIFG in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ISET_TXIFG_AW { # [doc = "0: NO_EFFECT"] ISET_TXIFG_NO_EFFECT = 0 , # [doc = "1: SET"] ISET_TXIFG_SET = 1 , } impl From < ISET_TXIFG_AW > for bool { # [inline (always)] fn from (variant : ISET_TXIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_TXIFG` writer - Sets TXIFG in RIS register"] pub type ISET_TXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_TXIFG_AW > ; impl < 'a , REG , const O : u8 > ISET_TXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iset_txifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TXIFG_AW :: ISET_TXIFG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn iset_txifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TXIFG_AW :: ISET_TXIFG_SET) } } # [doc = "Sets RXIFG in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ISET_RXIFG_AW { # [doc = "0: NO_EFFECT"] ISET_RXIFG_NO_EFFECT = 0 , # [doc = "1: SET"] ISET_RXIFG_SET = 1 , } impl From < ISET_RXIFG_AW > for bool { # [inline (always)] fn from (variant : ISET_RXIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_RXIFG` writer - Sets RXIFG in RIS register"] pub type ISET_RXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_RXIFG_AW > ; impl < 'a , REG , const O : u8 > ISET_RXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iset_rxifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_RXIFG_AW :: ISET_RXIFG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn iset_rxifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_RXIFG_AW :: ISET_RXIFG_SET) } } # [doc = "Sets PWRUPIFG in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ISET_PWRUPIFG_AW { # [doc = "0: NO_EFFECT"] ISET_PWRUPIFG_NO_EFFECT = 0 , # [doc = "1: SET"] ISET_PWRUPIFG_SET = 1 , } impl From < ISET_PWRUPIFG_AW > for bool { # [inline (always)] fn from (variant : ISET_PWRUPIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_PWRUPIFG` writer - Sets PWRUPIFG in RIS register"] pub type ISET_PWRUPIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_PWRUPIFG_AW > ; impl < 'a , REG , const O : u8 > ISET_PWRUPIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iset_pwrupifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_PWRUPIFG_AW :: ISET_PWRUPIFG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn iset_pwrupifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_PWRUPIFG_AW :: ISET_PWRUPIFG_SET) } } # [doc = "Sets PWRDWNIFG in RIS register\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ISET_PWRDWNIFG_AW { # [doc = "0: NO_EFFECT"] ISET_PWRDWNIFG_NO_EFFECT = 0 , # [doc = "1: SET"] ISET_PWRDWNIFG_SET = 1 , } impl From < ISET_PWRDWNIFG_AW > for bool { # [inline (always)] fn from (variant : ISET_PWRDWNIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_PWRDWNIFG` writer - Sets PWRDWNIFG in RIS register"] pub type ISET_PWRDWNIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_PWRDWNIFG_AW > ; impl < 'a , REG , const O : u8 > ISET_PWRDWNIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn iset_pwrdwnifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_PWRDWNIFG_AW :: ISET_PWRDWNIFG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn iset_pwrdwnifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_PWRDWNIFG_AW :: ISET_PWRDWNIFG_SET) } } impl W { # [doc = "Bit 0 - Sets TXIFG in RIS register"] # [inline (always)] # [must_use] pub fn iset_txifg (& mut self) -> ISET_TXIFG_W <'_, ISET_SPEC , 0 > { ISET_TXIFG_W :: new (self) } # [doc = "Bit 1 - Sets RXIFG in RIS register"] # [inline (always)] # [must_use] pub fn iset_rxifg (& mut self) -> ISET_RXIFG_W < ISET_SPEC , 1 > { ISET_RXIFG_W :: new (self) } # [doc = "Bit 2 - Sets PWRUPIFG in RIS register"] # [inline (always)] # [must_use] pub fn iset_pwrupifg (& mut self) -> ISET_PWRUPIFG_W < ISET_SPEC , 2 > { ISET_PWRUPIFG_W :: new (self) } # [doc = "Bit 3 - Sets PWRDWNIFG in RIS register"] # [inline (always)] # [must_use] pub fn iset_pwrdwnifg (& mut self) -> ISET_PWRDWNIFG_W < ISET_SPEC , 3 > { ISET_PWRDWNIFG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"] impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"] impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/gpioa/int_event0_imask.rs:1:67211 [INFO] [stdout] | [INFO] [stdout] 1 | ...nt0_imask_dio5 (& mut self) -> INT_EVENT0_IMASK_DIO5_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_DIO5_W :: new (self) } # [doc ... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_DIO0` reader - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_R = crate :: BitReader < INT_EVENT0_IMASK_DIO0_A > ; # [doc = "DIO0 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO0_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO0_A { match self . bits { false => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR , true => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio0_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO0` writer - DIO0 event mask"] pub type INT_EVENT0_IMASK_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` reader - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_R = crate :: BitReader < INT_EVENT0_IMASK_DIO1_A > ; # [doc = "DIO1 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO1_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO1_A { match self . bits { false => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR , true => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio1_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` writer - DIO1 event mask"] pub type INT_EVENT0_IMASK_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` reader - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_R = crate :: BitReader < INT_EVENT0_IMASK_DIO2_A > ; # [doc = "DIO2 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO2_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO2_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO2_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO2_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO2_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO2_A { match self . bits { false => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR , true => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio2_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` writer - DIO2 event mask"] pub type INT_EVENT0_IMASK_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` reader - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_R = crate :: BitReader < INT_EVENT0_IMASK_DIO3_A > ; # [doc = "DIO3 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO3_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO3_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO3_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO3_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO3_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO3_A { match self . bits { false => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR , true => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio3_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` writer - DIO3 event mask"] pub type INT_EVENT0_IMASK_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` reader - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_R = crate :: BitReader < INT_EVENT0_IMASK_DIO4_A > ; # [doc = "DIO4 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO4_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO4_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO4_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO4_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO4_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO4_A { match self . bits { false => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR , true => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio4_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio4_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` writer - DIO4 event mask"] pub type INT_EVENT0_IMASK_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO4_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` reader - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_R = crate :: BitReader < INT_EVENT0_IMASK_DIO5_A > ; # [doc = "DIO5 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO5_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO5_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO5_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO5_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO5_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO5_A { match self . bits { false => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR , true => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio5_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio5_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` writer - DIO5 event mask"] pub type INT_EVENT0_IMASK_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO5_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` reader - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_R = crate :: BitReader < INT_EVENT0_IMASK_DIO6_A > ; # [doc = "DIO6 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO6_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO6_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO6_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO6_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO6_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO6_A { match self . bits { false => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR , true => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio6_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio6_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` writer - DIO6 event mask"] pub type INT_EVENT0_IMASK_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO6_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` reader - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_R = crate :: BitReader < INT_EVENT0_IMASK_DIO7_A > ; # [doc = "DIO7 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO7_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO7_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO7_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO7_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO7_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO7_A { match self . bits { false => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR , true => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio7_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio7_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` writer - DIO7 event mask"] pub type INT_EVENT0_IMASK_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO7_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` reader - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_R = crate :: BitReader < INT_EVENT0_IMASK_DIO8_A > ; # [doc = "DIO8 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO8_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO8_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO8_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO8_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO8_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO8_A { match self . bits { false => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR , true => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio8_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio8_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` writer - DIO8 event mask"] pub type INT_EVENT0_IMASK_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO8_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` reader - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_R = crate :: BitReader < INT_EVENT0_IMASK_DIO9_A > ; # [doc = "DIO9 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO9_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO9_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO9_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO9_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO9_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO9_A { match self . bits { false => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR , true => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio9_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio9_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` writer - DIO9 event mask"] pub type INT_EVENT0_IMASK_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO9_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` reader - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_R = crate :: BitReader < INT_EVENT0_IMASK_DIO10_A > ; # [doc = "DIO10 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO10_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO10_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO10_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO10_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO10_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO10_A { match self . bits { false => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR , true => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio10_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio10_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` writer - DIO10 event mask"] pub type INT_EVENT0_IMASK_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO10_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` reader - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_R = crate :: BitReader < INT_EVENT0_IMASK_DIO11_A > ; # [doc = "DIO11 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO11_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO11_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO11_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO11_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO11_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO11_A { match self . bits { false => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR , true => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio11_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio11_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` writer - DIO11 event mask"] pub type INT_EVENT0_IMASK_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO11_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` reader - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_R = crate :: BitReader < INT_EVENT0_IMASK_DIO12_A > ; # [doc = "DIO12 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO12_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO12_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO12_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO12_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO12_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO12_A { match self . bits { false => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR , true => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio12_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio12_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` writer - DIO12 event mask"] pub type INT_EVENT0_IMASK_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO12_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` reader - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_R = crate :: BitReader < INT_EVENT0_IMASK_DIO13_A > ; # [doc = "DIO13 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO13_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO13_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO13_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO13_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO13_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO13_A { match self . bits { false => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR , true => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio13_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio13_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` writer - DIO13 event mask"] pub type INT_EVENT0_IMASK_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO13_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` reader - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_R = crate :: BitReader < INT_EVENT0_IMASK_DIO14_A > ; # [doc = "DIO14 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO14_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO14_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO14_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO14_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO14_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO14_A { match self . bits { false => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR , true => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio14_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio14_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` writer - DIO14 event mask"] pub type INT_EVENT0_IMASK_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO14_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` reader - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_R = crate :: BitReader < INT_EVENT0_IMASK_DIO15_A > ; # [doc = "DIO15 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO15_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO15_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO15_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO15_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO15_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO15_A { match self . bits { false => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR , true => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio15_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio15_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` writer - DIO15 event mask"] pub type INT_EVENT0_IMASK_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO15_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` reader - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_R = crate :: BitReader < INT_EVENT0_IMASK_DIO16_A > ; # [doc = "DIO16 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO16_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO16_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO16_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO16_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO16_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO16_A { match self . bits { false => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR , true => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio16_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio16_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` writer - DIO16 event mask"] pub type INT_EVENT0_IMASK_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO16_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` reader - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_R = crate :: BitReader < INT_EVENT0_IMASK_DIO17_A > ; # [doc = "DIO17 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO17_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO17_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO17_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO17_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO17_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO17_A { match self . bits { false => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR , true => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio17_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio17_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` writer - DIO17 event mask"] pub type INT_EVENT0_IMASK_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO17_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` reader - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_R = crate :: BitReader < INT_EVENT0_IMASK_DIO18_A > ; # [doc = "DIO18 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO18_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO18_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO18_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO18_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO18_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO18_A { match self . bits { false => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR , true => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio18_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio18_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` writer - DIO18 event mask"] pub type INT_EVENT0_IMASK_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO18_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` reader - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_R = crate :: BitReader < INT_EVENT0_IMASK_DIO19_A > ; # [doc = "DIO19 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO19_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO19_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO19_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO19_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO19_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO19_A { match self . bits { false => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR , true => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio19_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio19_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` writer - DIO19 event mask"] pub type INT_EVENT0_IMASK_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO19_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` reader - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_R = crate :: BitReader < INT_EVENT0_IMASK_DIO20_A > ; # [doc = "DIO20 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO20_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO20_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO20_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO20_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO20_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO20_A { match self . bits { false => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR , true => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio20_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio20_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` writer - DIO20 event mask"] pub type INT_EVENT0_IMASK_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO20_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` reader - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_R = crate :: BitReader < INT_EVENT0_IMASK_DIO21_A > ; # [doc = "DIO21 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO21_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO21_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO21_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO21_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO21_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO21_A { match self . bits { false => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR , true => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio21_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio21_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` writer - DIO21 event mask"] pub type INT_EVENT0_IMASK_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO21_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` reader - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_R = crate :: BitReader < INT_EVENT0_IMASK_DIO22_A > ; # [doc = "DIO22 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO22_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO22_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO22_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO22_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO22_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO22_A { match self . bits { false => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR , true => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio22_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio22_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` writer - DIO22 event mask"] pub type INT_EVENT0_IMASK_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO22_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` reader - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_R = crate :: BitReader < INT_EVENT0_IMASK_DIO23_A > ; # [doc = "DIO23 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO23_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO23_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO23_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO23_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO23_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO23_A { match self . bits { false => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR , true => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio23_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio23_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` writer - DIO23 event mask"] pub type INT_EVENT0_IMASK_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO23_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` reader - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_R = crate :: BitReader < INT_EVENT0_IMASK_DIO24_A > ; # [doc = "DIO24 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO24_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO24_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO24_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO24_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO24_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO24_A { match self . bits { false => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR , true => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio24_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio24_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` writer - DIO24 event mask"] pub type INT_EVENT0_IMASK_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO24_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` reader - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_R = crate :: BitReader < INT_EVENT0_IMASK_DIO25_A > ; # [doc = "DIO25 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO25_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO25_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO25_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO25_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO25_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO25_A { match self . bits { false => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR , true => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio25_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio25_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` writer - DIO25 event mask"] pub type INT_EVENT0_IMASK_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO25_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` reader - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_R = crate :: BitReader < INT_EVENT0_IMASK_DIO26_A > ; # [doc = "DIO26 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO26_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO26_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO26_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO26_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO26_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO26_A { match self . bits { false => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR , true => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio26_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio26_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` writer - DIO26 event mask"] pub type INT_EVENT0_IMASK_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO26_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` reader - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_R = crate :: BitReader < INT_EVENT0_IMASK_DIO27_A > ; # [doc = "DIO27 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO27_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO27_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO27_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO27_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO27_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO27_A { match self . bits { false => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR , true => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio27_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio27_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` writer - DIO27 event mask"] pub type INT_EVENT0_IMASK_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO27_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` reader - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_R = crate :: BitReader < INT_EVENT0_IMASK_DIO28_A > ; # [doc = "DIO28 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO28_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO28_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO28_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO28_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO28_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO28_A { match self . bits { false => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR , true => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio28_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio28_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` writer - DIO28 event mask"] pub type INT_EVENT0_IMASK_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO28_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` reader - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_R = crate :: BitReader < INT_EVENT0_IMASK_DIO29_A > ; # [doc = "DIO29 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO29_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO29_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO29_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO29_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO29_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO29_A { match self . bits { false => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR , true => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio29_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio29_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` writer - DIO29 event mask"] pub type INT_EVENT0_IMASK_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO29_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` reader - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_R = crate :: BitReader < INT_EVENT0_IMASK_DIO30_A > ; # [doc = "DIO30 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO30_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO30_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO30_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO30_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO30_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO30_A { match self . bits { false => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR , true => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio30_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio30_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` writer - DIO30 event mask"] pub type INT_EVENT0_IMASK_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO30_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` reader - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_R = crate :: BitReader < INT_EVENT0_IMASK_DIO31_A > ; # [doc = "DIO31 event mask\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DIO31_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DIO31_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DIO31_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO31_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO31_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO31_A { match self . bits { false => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR , true => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dio31_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dio31_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` writer - DIO31 event mask"] pub type INT_EVENT0_IMASK_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO31_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET) } } impl R { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] pub fn int_event0_imask_dio0 (& self) -> INT_EVENT0_IMASK_DIO0_R { INT_EVENT0_IMASK_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] pub fn int_event0_imask_dio1 (& self) -> INT_EVENT0_IMASK_DIO1_R { INT_EVENT0_IMASK_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] pub fn int_event0_imask_dio2 (& self) -> INT_EVENT0_IMASK_DIO2_R { INT_EVENT0_IMASK_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] pub fn int_event0_imask_dio3 (& self) -> INT_EVENT0_IMASK_DIO3_R { INT_EVENT0_IMASK_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] pub fn int_event0_imask_dio4 (& self) -> INT_EVENT0_IMASK_DIO4_R { INT_EVENT0_IMASK_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] pub fn int_event0_imask_dio5 (& self) -> INT_EVENT0_IMASK_DIO5_R { INT_EVENT0_IMASK_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] pub fn int_event0_imask_dio6 (& self) -> INT_EVENT0_IMASK_DIO6_R { INT_EVENT0_IMASK_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] pub fn int_event0_imask_dio7 (& self) -> INT_EVENT0_IMASK_DIO7_R { INT_EVENT0_IMASK_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] pub fn int_event0_imask_dio8 (& self) -> INT_EVENT0_IMASK_DIO8_R { INT_EVENT0_IMASK_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] pub fn int_event0_imask_dio9 (& self) -> INT_EVENT0_IMASK_DIO9_R { INT_EVENT0_IMASK_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] pub fn int_event0_imask_dio10 (& self) -> INT_EVENT0_IMASK_DIO10_R { INT_EVENT0_IMASK_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] pub fn int_event0_imask_dio11 (& self) -> INT_EVENT0_IMASK_DIO11_R { INT_EVENT0_IMASK_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] pub fn int_event0_imask_dio12 (& self) -> INT_EVENT0_IMASK_DIO12_R { INT_EVENT0_IMASK_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] pub fn int_event0_imask_dio13 (& self) -> INT_EVENT0_IMASK_DIO13_R { INT_EVENT0_IMASK_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] pub fn int_event0_imask_dio14 (& self) -> INT_EVENT0_IMASK_DIO14_R { INT_EVENT0_IMASK_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] pub fn int_event0_imask_dio15 (& self) -> INT_EVENT0_IMASK_DIO15_R { INT_EVENT0_IMASK_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] pub fn int_event0_imask_dio16 (& self) -> INT_EVENT0_IMASK_DIO16_R { INT_EVENT0_IMASK_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] pub fn int_event0_imask_dio17 (& self) -> INT_EVENT0_IMASK_DIO17_R { INT_EVENT0_IMASK_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] pub fn int_event0_imask_dio18 (& self) -> INT_EVENT0_IMASK_DIO18_R { INT_EVENT0_IMASK_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] pub fn int_event0_imask_dio19 (& self) -> INT_EVENT0_IMASK_DIO19_R { INT_EVENT0_IMASK_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] pub fn int_event0_imask_dio20 (& self) -> INT_EVENT0_IMASK_DIO20_R { INT_EVENT0_IMASK_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] pub fn int_event0_imask_dio21 (& self) -> INT_EVENT0_IMASK_DIO21_R { INT_EVENT0_IMASK_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] pub fn int_event0_imask_dio22 (& self) -> INT_EVENT0_IMASK_DIO22_R { INT_EVENT0_IMASK_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] pub fn int_event0_imask_dio23 (& self) -> INT_EVENT0_IMASK_DIO23_R { INT_EVENT0_IMASK_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] pub fn int_event0_imask_dio24 (& self) -> INT_EVENT0_IMASK_DIO24_R { INT_EVENT0_IMASK_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] pub fn int_event0_imask_dio25 (& self) -> INT_EVENT0_IMASK_DIO25_R { INT_EVENT0_IMASK_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] pub fn int_event0_imask_dio26 (& self) -> INT_EVENT0_IMASK_DIO26_R { INT_EVENT0_IMASK_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] pub fn int_event0_imask_dio27 (& self) -> INT_EVENT0_IMASK_DIO27_R { INT_EVENT0_IMASK_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] pub fn int_event0_imask_dio28 (& self) -> INT_EVENT0_IMASK_DIO28_R { INT_EVENT0_IMASK_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] pub fn int_event0_imask_dio29 (& self) -> INT_EVENT0_IMASK_DIO29_R { INT_EVENT0_IMASK_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] pub fn int_event0_imask_dio30 (& self) -> INT_EVENT0_IMASK_DIO30_R { INT_EVENT0_IMASK_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] pub fn int_event0_imask_dio31 (& self) -> INT_EVENT0_IMASK_DIO31_R { INT_EVENT0_IMASK_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - DIO0 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio0 (& mut self) -> INT_EVENT0_IMASK_DIO0_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio1 (& mut self) -> INT_EVENT0_IMASK_DIO1_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio2 (& mut self) -> INT_EVENT0_IMASK_DIO2_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio3 (& mut self) -> INT_EVENT0_IMASK_DIO3_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio4 (& mut self) -> INT_EVENT0_IMASK_DIO4_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio5 (& mut self) -> INT_EVENT0_IMASK_DIO5_W <'_, INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio6 (& mut self) -> INT_EVENT0_IMASK_DIO6_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio7 (& mut self) -> INT_EVENT0_IMASK_DIO7_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio8 (& mut self) -> INT_EVENT0_IMASK_DIO8_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio9 (& mut self) -> INT_EVENT0_IMASK_DIO9_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio10 (& mut self) -> INT_EVENT0_IMASK_DIO10_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio11 (& mut self) -> INT_EVENT0_IMASK_DIO11_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio12 (& mut self) -> INT_EVENT0_IMASK_DIO12_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio13 (& mut self) -> INT_EVENT0_IMASK_DIO13_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio14 (& mut self) -> INT_EVENT0_IMASK_DIO14_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio15 (& mut self) -> INT_EVENT0_IMASK_DIO15_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DIO15_W :: new (self) } # [doc = "Bit 16 - DIO16 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio16 (& mut self) -> INT_EVENT0_IMASK_DIO16_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio17 (& mut self) -> INT_EVENT0_IMASK_DIO17_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio18 (& mut self) -> INT_EVENT0_IMASK_DIO18_W < INT_EVENT0_IMASK_SPEC , 18 > { INT_EVENT0_IMASK_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio19 (& mut self) -> INT_EVENT0_IMASK_DIO19_W < INT_EVENT0_IMASK_SPEC , 19 > { INT_EVENT0_IMASK_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio20 (& mut self) -> INT_EVENT0_IMASK_DIO20_W < INT_EVENT0_IMASK_SPEC , 20 > { INT_EVENT0_IMASK_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio21 (& mut self) -> INT_EVENT0_IMASK_DIO21_W < INT_EVENT0_IMASK_SPEC , 21 > { INT_EVENT0_IMASK_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio22 (& mut self) -> INT_EVENT0_IMASK_DIO22_W < INT_EVENT0_IMASK_SPEC , 22 > { INT_EVENT0_IMASK_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio23 (& mut self) -> INT_EVENT0_IMASK_DIO23_W < INT_EVENT0_IMASK_SPEC , 23 > { INT_EVENT0_IMASK_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio24 (& mut self) -> INT_EVENT0_IMASK_DIO24_W < INT_EVENT0_IMASK_SPEC , 24 > { INT_EVENT0_IMASK_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio25 (& mut self) -> INT_EVENT0_IMASK_DIO25_W < INT_EVENT0_IMASK_SPEC , 25 > { INT_EVENT0_IMASK_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio26 (& mut self) -> INT_EVENT0_IMASK_DIO26_W < INT_EVENT0_IMASK_SPEC , 26 > { INT_EVENT0_IMASK_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio27 (& mut self) -> INT_EVENT0_IMASK_DIO27_W < INT_EVENT0_IMASK_SPEC , 27 > { INT_EVENT0_IMASK_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio28 (& mut self) -> INT_EVENT0_IMASK_DIO28_W < INT_EVENT0_IMASK_SPEC , 28 > { INT_EVENT0_IMASK_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio29 (& mut self) -> INT_EVENT0_IMASK_DIO29_W < INT_EVENT0_IMASK_SPEC , 29 > { INT_EVENT0_IMASK_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio30 (& mut self) -> INT_EVENT0_IMASK_DIO30_W < INT_EVENT0_IMASK_SPEC , 30 > { INT_EVENT0_IMASK_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event mask"] # [inline (always)] # [must_use] pub fn int_event0_imask_dio31 (& mut self) -> INT_EVENT0_IMASK_DIO31_W < INT_EVENT0_IMASK_SPEC , 31 > { INT_EVENT0_IMASK_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart0/int_event0_imask.rs:1:43714 [INFO] [stdout] | [INFO] [stdout] 1 | ..._addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self)... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."] pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."] pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."] pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W <'_, INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/ctl0.rs:1:39769 [INFO] [stdout] | [INFO] [stdout] 1 | ...[must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable F... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CTL0` reader"] pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"] pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"] CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)] fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"] pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_LBE_A { # [doc = "0: DISABLE"] CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)] fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"] pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RXE_A { # [doc = "0: DISABLE"] CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)] fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXE_A { # [doc = "0: DISABLE"] CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)] fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"] CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"] CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"] CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)] fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"] # [inline (always)] pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"] # [inline (always)] pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"] # [inline (always)] pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"] # [inline (always)] pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_MODE_A { # [doc = "0: UART"] CTL0_MODE_UART = 0 , # [doc = "1: RS485"] CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"] CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"] CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"] CTL0_MODE_SMART = 4 , # [doc = "5: DALI"] CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)] fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"] # [inline (always)] pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"] # [inline (always)] pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"] # [inline (always)] pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"] # [inline (always)] pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"] # [inline (always)] pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"] # [inline (always)] pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"] # [inline (always)] pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"] # [inline (always)] pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"] # [inline (always)] pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"] # [inline (always)] pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"] # [inline (always)] pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"] # [inline (always)] pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTS_A { # [doc = "0: CLR"] CTL0_RTS_CLR = 0 , # [doc = "1: SET"] CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)] fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"] CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"] pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"] pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"] CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)] fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"] pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum CTL0_HSE_A { # [doc = "0: OVS16"] CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"] CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"] CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)] fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"] # [inline (always)] pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"] # [inline (always)] pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"] # [inline (always)] pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"] # [inline (always)] pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"] # [inline (always)] pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"] # [inline (always)] pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"] pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_FEN_A { # [doc = "0: DISABLE"] CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)] fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"] pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"] CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)] fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"] CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"] CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)] fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."] # [inline (always)] # [must_use] pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"] # [inline (always)] # [must_use] pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."] # [inline (always)] # [must_use] pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"] # [inline (always)] # [must_use] pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."] # [inline (always)] # [must_use] pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"] # [inline (always)] # [must_use] pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."] # [inline (always)] # [must_use] pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"] # [inline (always)] # [must_use] pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"] # [inline (always)] # [must_use] pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."] # [inline (always)] # [must_use] pub fn ctl0_hse (& mut self) -> CTL0_HSE_W <'_, CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"] # [inline (always)] # [must_use] pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."] # [inline (always)] # [must_use] pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."] # [inline (always)] # [must_use] pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"] impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"] impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"] impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/i2c1/soar.rs:1:5262 [INFO] [stdout] | [INFO] [stdout] 1 | ... [must_use] pub fn soar_oar (& mut self) -> SOAR_OAR_W < SOAR_SPEC , 0 > { SOAR_OAR_W :: new (self) } # [doc = "Bit 14 - I2C Slave Own... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SOAR` reader"] pub type R = crate :: R < SOAR_SPEC > ; # [doc = "Register `SOAR` writer"] pub type W = crate :: W < SOAR_SPEC > ; # [doc = "Field `SOAR_OAR` reader - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] pub type SOAR_OAR_R = crate :: FieldReader < u16 > ; # [doc = "Field `SOAR_OAR` writer - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] pub type SOAR_OAR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; # [doc = "Field `SOAR_OAREN` reader - I2C Slave Own Address Enable"] pub type SOAR_OAREN_R = crate :: BitReader < SOAR_OAREN_A > ; # [doc = "I2C Slave Own Address Enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR_OAREN_A { # [doc = "0: DISABLE"] SOAR_OAREN_DISABLE = 0 , # [doc = "1: ENABLE"] SOAR_OAREN_ENABLE = 1 , } impl From < SOAR_OAREN_A > for bool { # [inline (always)] fn from (variant : SOAR_OAREN_A) -> Self { variant as u8 != 0 } } impl SOAR_OAREN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR_OAREN_A { match self . bits { false => SOAR_OAREN_A :: SOAR_OAREN_DISABLE , true => SOAR_OAREN_A :: SOAR_OAREN_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_soar_oaren_disable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_soar_oaren_enable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_ENABLE } } # [doc = "Field `SOAR_OAREN` writer - I2C Slave Own Address Enable"] pub type SOAR_OAREN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_OAREN_A > ; impl < 'a , REG , const O : u8 > SOAR_OAREN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn soar_oaren_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn soar_oaren_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_ENABLE) } } # [doc = "Field `SOAR_SMODE` reader - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type SOAR_SMODE_R = crate :: BitReader < SOAR_SMODE_A > ; # [doc = "This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum SOAR_SMODE_A { # [doc = "0: MODE7"] SOAR_SMODE_MODE7 = 0 , # [doc = "1: MODE10"] SOAR_SMODE_MODE10 = 1 , } impl From < SOAR_SMODE_A > for bool { # [inline (always)] fn from (variant : SOAR_SMODE_A) -> Self { variant as u8 != 0 } } impl SOAR_SMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> SOAR_SMODE_A { match self . bits { false => SOAR_SMODE_A :: SOAR_SMODE_MODE7 , true => SOAR_SMODE_A :: SOAR_SMODE_MODE10 , } } # [doc = "MODE7"] # [inline (always)] pub fn is_soar_smode_mode7 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE7 } # [doc = "MODE10"] # [inline (always)] pub fn is_soar_smode_mode10 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE10 } } # [doc = "Field `SOAR_SMODE` writer - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type SOAR_SMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_SMODE_A > ; impl < 'a , REG , const O : u8 > SOAR_SMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "MODE7"] # [inline (always)] pub fn soar_smode_mode7 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE7) } # [doc = "MODE10"] # [inline (always)] pub fn soar_smode_mode10 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE10) } } impl R { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] # [inline (always)] pub fn soar_oar (& self) -> SOAR_OAR_R { SOAR_OAR_R :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bit 14 - I2C Slave Own Address Enable"] # [inline (always)] pub fn soar_oaren (& self) -> SOAR_OAREN_R { SOAR_OAREN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] pub fn soar_smode (& self) -> SOAR_SMODE_R { SOAR_SMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"] # [inline (always)] # [must_use] pub fn soar_oar (& mut self) -> SOAR_OAR_W <'_, SOAR_SPEC , 0 > { SOAR_OAR_W :: new (self) } # [doc = "Bit 14 - I2C Slave Own Address Enable"] # [inline (always)] # [must_use] pub fn soar_oaren (& mut self) -> SOAR_OAREN_W < SOAR_SPEC , 14 > { SOAR_OAREN_W :: new (self) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] # [must_use] pub fn soar_smode (& mut self) -> SOAR_SMODE_W < SOAR_SPEC , 15 > { SOAR_SMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOAR_SPEC ; impl crate :: RegisterSpec for SOAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar::R`](R) reader structure"] impl crate :: Readable for SOAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar::W`](W) writer structure"] impl crate :: Writable for SOAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR to value 0x4000"] impl crate :: Resettable for SOAR_SPEC { const RESET_VALUE : Self :: Ux = 0x4000 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> src/uart1/int_event0_imask.rs:1:36755 [INFO] [stdout] | [INFO] [stdout] 1 | ...ent0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc =... [INFO] [stdout] | ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `INT_EVENT0_IMASK` reader"] pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"] pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."] pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."] pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."] pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."] pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."] pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."] pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."] pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."] pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."] pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"] pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"] INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"] INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)] fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"] # [inline (always)] pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"] # [inline (always)] pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"] # [inline (always)] pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"] # [inline (always)] pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."] # [inline (always)] # [must_use] pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."] # [inline (always)] # [must_use] pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"] # [inline (always)] # [must_use] pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W <'_, INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"] # [inline (always)] # [must_use] pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"] # [inline (always)] # [must_use] pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"] impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"] impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"] impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } [WARN] too much data in the log, truncating it