[INFO] cloning repository https://github.com/akaDestrocore/stm32f4_bootloader [INFO] running `Command { std: "git" "-c" "credential.helper=" "-c" "credential.helper=/workspace/cargo-home/bin/git-credential-null" "clone" "--bare" "https://github.com/akaDestrocore/stm32f4_bootloader" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FakaDestrocore%2Fstm32f4_bootloader", kill_on_drop: false }` [INFO] [stderr] Cloning into bare repository '/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FakaDestrocore%2Fstm32f4_bootloader'... [INFO] running `Command { std: "git" "rev-parse" "HEAD", kill_on_drop: false }` [INFO] [stdout] 354ead2073eebf5641cdf5b0e9562cb76ada78a9 [INFO] checking akaDestrocore/stm32f4_bootloader against try#a2a6e871b05c7b8ecc9a3c8a20db1f39e995e399 for pr-145770 [INFO] running `Command { std: "git" "clone" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FakaDestrocore%2Fstm32f4_bootloader" "/workspace/builds/worker-6-tc2/source", kill_on_drop: false }` [INFO] [stderr] Cloning into '/workspace/builds/worker-6-tc2/source'... [INFO] [stderr] done. [INFO] removed /workspace/builds/worker-6-tc2/source/.cargo/config.toml [INFO] started tweaking git repo https://github.com/akaDestrocore/stm32f4_bootloader [INFO] finished tweaking git repo https://github.com/akaDestrocore/stm32f4_bootloader [INFO] tweaked toml for git repo https://github.com/akaDestrocore/stm32f4_bootloader written to /workspace/builds/worker-6-tc2/source/Cargo.toml [INFO] validating manifest of git repo https://github.com/akaDestrocore/stm32f4_bootloader on toolchain a2a6e871b05c7b8ecc9a3c8a20db1f39e995e399 [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+a2a6e871b05c7b8ecc9a3c8a20db1f39e995e399" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }` [INFO] crate git repo https://github.com/akaDestrocore/stm32f4_bootloader already has a lockfile, it will not be regenerated [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+a2a6e871b05c7b8ecc9a3c8a20db1f39e995e399" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }` [INFO] [stderr] warning: virtual workspace defaulting to `resolver = "1"` despite one or more workspace members being on edition 2021 which implies `resolver = "2"` [INFO] [stderr] note: to keep the current resolver, specify `workspace.resolver = "1"` in the workspace root's manifest [INFO] [stderr] note: to use the edition 2021 resolver, specify `workspace.resolver = "2"` in the workspace root's manifest [INFO] [stderr] note: for more details see https://doc.rust-lang.org/cargo/reference/resolver.html#resolver-versions [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-6-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-6-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:7ad1b28ee6f5f7f699f6cf7015098d6ccdd96d6f2d78dd06228f5b4c9faf309c" "/opt/rustwide/cargo-home/bin/cargo" "+a2a6e871b05c7b8ecc9a3c8a20db1f39e995e399" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }` [INFO] [stdout] 95a3c25c5da216949110cc237039f54ae528aaf0b42edb608885a15ab326e3cb [INFO] running `Command { std: "docker" "start" "-a" "95a3c25c5da216949110cc237039f54ae528aaf0b42edb608885a15ab326e3cb", kill_on_drop: false }` [INFO] running `Command { std: "docker" "inspect" "95a3c25c5da216949110cc237039f54ae528aaf0b42edb608885a15ab326e3cb", kill_on_drop: false }` [INFO] running `Command { std: "docker" "rm" "-f" "95a3c25c5da216949110cc237039f54ae528aaf0b42edb608885a15ab326e3cb", kill_on_drop: false }` [INFO] [stdout] 95a3c25c5da216949110cc237039f54ae528aaf0b42edb608885a15ab326e3cb [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-6-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-6-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:7ad1b28ee6f5f7f699f6cf7015098d6ccdd96d6f2d78dd06228f5b4c9faf309c" "/opt/rustwide/cargo-home/bin/cargo" "+a2a6e871b05c7b8ecc9a3c8a20db1f39e995e399" "check" "--frozen" "--all" "--all-targets" "--message-format=json", kill_on_drop: false }` [INFO] [stdout] 47a51782a0578f8e69db090e03ba1afff90b54b1ddb7dfe774a0e9e7302b4d3b [INFO] running `Command { std: "docker" "start" "-a" "47a51782a0578f8e69db090e03ba1afff90b54b1ddb7dfe774a0e9e7302b4d3b", kill_on_drop: false }` [INFO] [stderr] warning: virtual workspace defaulting to `resolver = "1"` despite one or more workspace members being on edition 2021 which implies `resolver = "2"` [INFO] [stderr] note: to keep the current resolver, specify `workspace.resolver = "1"` in the workspace root's manifest [INFO] [stderr] note: to use the edition 2021 resolver, specify `workspace.resolver = "2"` in the workspace root's manifest [INFO] [stderr] note: for more details see https://doc.rust-lang.org/cargo/reference/resolver.html#resolver-versions [INFO] [stderr] Compiling cortex-m v0.7.7 [INFO] [stderr] Compiling cortex-m-rt v0.7.5 [INFO] [stderr] Compiling semver-parser v0.7.0 [INFO] [stderr] Compiling proc-macro2 v1.0.95 [INFO] [stderr] Compiling unicode-ident v1.0.18 [INFO] [stderr] Compiling stm32f4 v0.1.0 (/opt/rustwide/workdir/stm32f4) [INFO] [stderr] Checking nb v1.1.0 [INFO] [stderr] Checking vcell v0.1.3 [INFO] [stderr] Checking nb v0.1.3 [INFO] [stderr] Checking void v1.0.2 [INFO] [stderr] Checking volatile-register v0.2.2 [INFO] [stderr] Checking embedded-hal v0.2.7 [INFO] [stderr] Compiling semver v0.9.0 [INFO] [stderr] Checking critical-section v1.2.0 [INFO] [stderr] Checking bitfield v0.13.2 [INFO] [stderr] Checking bare-metal v1.0.0 [INFO] [stderr] Compiling rustc_version v0.2.3 [INFO] [stderr] Checking panic-halt v0.2.0 [INFO] [stderr] Compiling boot v0.1.0 (/opt/rustwide/workdir/boot) [INFO] [stderr] Compiling loader v0.1.0 (/opt/rustwide/workdir/loader) [INFO] [stderr] Compiling updater v0.1.0 (/opt/rustwide/workdir/updater) [INFO] [stderr] Compiling application v0.1.0 (/opt/rustwide/workdir/application) [INFO] [stderr] Compiling bare-metal v0.2.5 [INFO] [stderr] Compiling quote v1.0.40 [INFO] [stderr] Compiling syn v2.0.100 [INFO] [stderr] Compiling cortex-m-rt-macros v0.7.5 [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rng/cr.rs:1:3399 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn rngen (& mut self) -> RngenW < CrSpec > { RngenW :: new (self , 2) } # [doc = "Bit 3 - Interrupt enable"] #... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] = note: `#[warn(mismatched_lifetime_syntaxes)]` on by default [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Random number generator enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Rngen { # [doc = "0: Random number generator is disabled"] Disabled = 0 , # [doc = "1: Random number generator is enabled"] Enabled = 1 , } impl From < Rngen > for bool { # [inline (always)] fn from (variant : Rngen) -> Self { variant as u8 != 0 } } # [doc = "Field `RNGEN` reader - Random number generator enable"] pub type RngenR = crate :: BitReader < Rngen > ; impl RngenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Rngen { match self . bits { false => Rngen :: Disabled , true => Rngen :: Enabled , } } # [doc = "Random number generator is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Rngen :: Disabled } # [doc = "Random number generator is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Rngen :: Enabled } } # [doc = "Field `RNGEN` writer - Random number generator enable"] pub type RngenW < 'a , REG > = crate :: BitWriter < 'a , REG , Rngen > ; impl < 'a , REG > RngenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Random number generator is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Rngen :: Disabled) } # [doc = "Random number generator is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Rngen :: Enabled) } } # [doc = "Interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ie { # [doc = "0: RNG interrupt is disabled"] Disabled = 0 , # [doc = "1: RNG interrupt is enabled"] Enabled = 1 , } impl From < Ie > for bool { # [inline (always)] fn from (variant : Ie) -> Self { variant as u8 != 0 } } # [doc = "Field `IE` reader - Interrupt enable"] pub type IeR = crate :: BitReader < Ie > ; impl IeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ie { match self . bits { false => Ie :: Disabled , true => Ie :: Enabled , } } # [doc = "RNG interrupt is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ie :: Disabled } # [doc = "RNG interrupt is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ie :: Enabled } } # [doc = "Field `IE` writer - Interrupt enable"] pub type IeW < 'a , REG > = crate :: BitWriter < 'a , REG , Ie > ; impl < 'a , REG > IeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RNG interrupt is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ie :: Disabled) } # [doc = "RNG interrupt is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ie :: Enabled) } } impl R { # [doc = "Bit 2 - Random number generator enable"] # [inline (always)] pub fn rngen (& self) -> RngenR { RngenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Interrupt enable"] # [inline (always)] pub fn ie (& self) -> IeR { IeR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 2 - Random number generator enable"] # [inline (always)] pub fn rngen (& mut self) -> RngenW <'_, CrSpec > { RngenW :: new (self , 2) } # [doc = "Bit 3 - Interrupt enable"] # [inline (always)] pub fn ie (& mut self) -> IeW < CrSpec > { IeW :: new (self , 3) } } # [doc = "control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rng/cr.rs:1:3529 [INFO] [stdout] | [INFO] [stdout] 1 | ...le"] # [inline (always)] pub fn ie (& mut self) -> IeW < CrSpec > { IeW :: new (self , 3) } } # [doc = "control register\n\nYou can [`... [INFO] [stdout] | ^^^^^^^^^^ -------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Random number generator enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Rngen { # [doc = "0: Random number generator is disabled"] Disabled = 0 , # [doc = "1: Random number generator is enabled"] Enabled = 1 , } impl From < Rngen > for bool { # [inline (always)] fn from (variant : Rngen) -> Self { variant as u8 != 0 } } # [doc = "Field `RNGEN` reader - Random number generator enable"] pub type RngenR = crate :: BitReader < Rngen > ; impl RngenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Rngen { match self . bits { false => Rngen :: Disabled , true => Rngen :: Enabled , } } # [doc = "Random number generator is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Rngen :: Disabled } # [doc = "Random number generator is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Rngen :: Enabled } } # [doc = "Field `RNGEN` writer - Random number generator enable"] pub type RngenW < 'a , REG > = crate :: BitWriter < 'a , REG , Rngen > ; impl < 'a , REG > RngenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Random number generator is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Rngen :: Disabled) } # [doc = "Random number generator is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Rngen :: Enabled) } } # [doc = "Interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ie { # [doc = "0: RNG interrupt is disabled"] Disabled = 0 , # [doc = "1: RNG interrupt is enabled"] Enabled = 1 , } impl From < Ie > for bool { # [inline (always)] fn from (variant : Ie) -> Self { variant as u8 != 0 } } # [doc = "Field `IE` reader - Interrupt enable"] pub type IeR = crate :: BitReader < Ie > ; impl IeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ie { match self . bits { false => Ie :: Disabled , true => Ie :: Enabled , } } # [doc = "RNG interrupt is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ie :: Disabled } # [doc = "RNG interrupt is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ie :: Enabled } } # [doc = "Field `IE` writer - Interrupt enable"] pub type IeW < 'a , REG > = crate :: BitWriter < 'a , REG , Ie > ; impl < 'a , REG > IeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RNG interrupt is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ie :: Disabled) } # [doc = "RNG interrupt is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ie :: Enabled) } } impl R { # [doc = "Bit 2 - Random number generator enable"] # [inline (always)] pub fn rngen (& self) -> RngenR { RngenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Interrupt enable"] # [inline (always)] pub fn ie (& self) -> IeR { IeR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 2 - Random number generator enable"] # [inline (always)] pub fn rngen (& mut self) -> RngenW < CrSpec > { RngenW :: new (self , 2) } # [doc = "Bit 3 - Interrupt enable"] # [inline (always)] pub fn ie (& mut self) -> IeW <'_, CrSpec > { IeW :: new (self , 3) } } # [doc = "control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rng/sr.rs:1:8324 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn ceis (& mut self) -> CeisW < SrSpec > { CeisW :: new (self , 5) } # [doc = "Bit 6 - Seed error interrupt ... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SR` reader"] pub type R = crate :: R < SrSpec > ; # [doc = "Register `SR` writer"] pub type W = crate :: W < SrSpec > ; # [doc = "Data ready\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Drdy { # [doc = "0: The RNG_DR register is not yet valid, no random data is available"] NotValid = 0 , # [doc = "1: The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated."] Valid = 1 , } impl From < Drdy > for bool { # [inline (always)] fn from (variant : Drdy) -> Self { variant as u8 != 0 } } # [doc = "Field `DRDY` reader - Data ready"] pub type DrdyR = crate :: BitReader < Drdy > ; impl DrdyR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Drdy { match self . bits { false => Drdy :: NotValid , true => Drdy :: Valid , } } # [doc = "The RNG_DR register is not yet valid, no random data is available"] # [inline (always)] pub fn is_not_valid (& self) -> bool { * self == Drdy :: NotValid } # [doc = "The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated."] # [inline (always)] pub fn is_valid (& self) -> bool { * self == Drdy :: Valid } } # [doc = "Clock error current status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cecs { # [doc = "0: The RNG clock is correct (fRNGCLK> fHCLK/16). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered."] Correct = 0 , # [doc = "1: The RNG clock is too slow (fRNGCLK< fHCLK/16)"] TooSlow = 1 , } impl From < Cecs > for bool { # [inline (always)] fn from (variant : Cecs) -> Self { variant as u8 != 0 } } # [doc = "Field `CECS` reader - Clock error current status"] pub type CecsR = crate :: BitReader < Cecs > ; impl CecsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cecs { match self . bits { false => Cecs :: Correct , true => Cecs :: TooSlow , } } # [doc = "The RNG clock is correct (fRNGCLK> fHCLK/16). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered."] # [inline (always)] pub fn is_correct (& self) -> bool { * self == Cecs :: Correct } # [doc = "The RNG clock is too slow (fRNGCLK< fHCLK/16)"] # [inline (always)] pub fn is_too_slow (& self) -> bool { * self == Cecs :: TooSlow } } # [doc = "Seed error current status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Secs { # [doc = "0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered."] NoFaulty = 0 , # [doc = "1: One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bits patterns (“01” or “10”)"] Faulty = 1 , } impl From < Secs > for bool { # [inline (always)] fn from (variant : Secs) -> Self { variant as u8 != 0 } } # [doc = "Field `SECS` reader - Seed error current status"] pub type SecsR = crate :: BitReader < Secs > ; impl SecsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Secs { match self . bits { false => Secs :: NoFaulty , true => Secs :: Faulty , } } # [doc = "No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered."] # [inline (always)] pub fn is_no_faulty (& self) -> bool { * self == Secs :: NoFaulty } # [doc = "One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bits patterns (“01” or “10”)"] # [inline (always)] pub fn is_faulty (& self) -> bool { * self == Secs :: Faulty } } # [doc = "Clock error interrupt status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ceis { # [doc = "0: The RNG clock is correct (fRNGCLK > fHCLK/16)"] Correct = 0 , # [doc = "1: The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] TooSlow = 1 , } impl From < Ceis > for bool { # [inline (always)] fn from (variant : Ceis) -> Self { variant as u8 != 0 } } # [doc = "Field `CEIS` reader - Clock error interrupt status"] pub type CeisR = crate :: BitReader < Ceis > ; impl CeisR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ceis { match self . bits { false => Ceis :: Correct , true => Ceis :: TooSlow , } } # [doc = "The RNG clock is correct (fRNGCLK > fHCLK/16)"] # [inline (always)] pub fn is_correct (& self) -> bool { * self == Ceis :: Correct } # [doc = "The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] # [inline (always)] pub fn is_too_slow (& self) -> bool { * self == Ceis :: TooSlow } } # [doc = "Field `CEIS` writer - Clock error interrupt status"] pub type CeisW < 'a , REG > = crate :: BitWriter < 'a , REG , Ceis > ; impl < 'a , REG > CeisW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The RNG clock is correct (fRNGCLK > fHCLK/16)"] # [inline (always)] pub fn correct (self) -> & 'a mut crate :: W < REG > { self . variant (Ceis :: Correct) } # [doc = "The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] # [inline (always)] pub fn too_slow (self) -> & 'a mut crate :: W < REG > { self . variant (Ceis :: TooSlow) } } # [doc = "Seed error interrupt status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Seis { # [doc = "0: No faulty sequence detected"] NoFaulty = 0 , # [doc = "1: At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] Faulty = 1 , } impl From < Seis > for bool { # [inline (always)] fn from (variant : Seis) -> Self { variant as u8 != 0 } } # [doc = "Field `SEIS` reader - Seed error interrupt status"] pub type SeisR = crate :: BitReader < Seis > ; impl SeisR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Seis { match self . bits { false => Seis :: NoFaulty , true => Seis :: Faulty , } } # [doc = "No faulty sequence detected"] # [inline (always)] pub fn is_no_faulty (& self) -> bool { * self == Seis :: NoFaulty } # [doc = "At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] # [inline (always)] pub fn is_faulty (& self) -> bool { * self == Seis :: Faulty } } # [doc = "Field `SEIS` writer - Seed error interrupt status"] pub type SeisW < 'a , REG > = crate :: BitWriter < 'a , REG , Seis > ; impl < 'a , REG > SeisW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No faulty sequence detected"] # [inline (always)] pub fn no_faulty (self) -> & 'a mut crate :: W < REG > { self . variant (Seis :: NoFaulty) } # [doc = "At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] # [inline (always)] pub fn faulty (self) -> & 'a mut crate :: W < REG > { self . variant (Seis :: Faulty) } } impl R { # [doc = "Bit 0 - Data ready"] # [inline (always)] pub fn drdy (& self) -> DrdyR { DrdyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Clock error current status"] # [inline (always)] pub fn cecs (& self) -> CecsR { CecsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Seed error current status"] # [inline (always)] pub fn secs (& self) -> SecsR { SecsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - Clock error interrupt status"] # [inline (always)] pub fn ceis (& self) -> CeisR { CeisR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Seed error interrupt status"] # [inline (always)] pub fn seis (& self) -> SeisR { SeisR :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bit 5 - Clock error interrupt status"] # [inline (always)] pub fn ceis (& mut self) -> CeisW <'_, SrSpec > { CeisW :: new (self , 5) } # [doc = "Bit 6 - Seed error interrupt status"] # [inline (always)] pub fn seis (& mut self) -> SeisW < SrSpec > { SeisW :: new (self , 6) } } # [doc = "status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SrSpec ; impl crate :: RegisterSpec for SrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sr::R`](R) reader structure"] impl crate :: Readable for SrSpec { } # [doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] impl crate :: Writable for SrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SR to value 0"] impl crate :: Resettable for SrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rng/sr.rs:1:8465 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn seis (& mut self) -> SeisW < SrSpec > { SeisW :: new (self , 6) } } # [doc = "status register\n\nYou can ... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SR` reader"] pub type R = crate :: R < SrSpec > ; # [doc = "Register `SR` writer"] pub type W = crate :: W < SrSpec > ; # [doc = "Data ready\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Drdy { # [doc = "0: The RNG_DR register is not yet valid, no random data is available"] NotValid = 0 , # [doc = "1: The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated."] Valid = 1 , } impl From < Drdy > for bool { # [inline (always)] fn from (variant : Drdy) -> Self { variant as u8 != 0 } } # [doc = "Field `DRDY` reader - Data ready"] pub type DrdyR = crate :: BitReader < Drdy > ; impl DrdyR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Drdy { match self . bits { false => Drdy :: NotValid , true => Drdy :: Valid , } } # [doc = "The RNG_DR register is not yet valid, no random data is available"] # [inline (always)] pub fn is_not_valid (& self) -> bool { * self == Drdy :: NotValid } # [doc = "The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated."] # [inline (always)] pub fn is_valid (& self) -> bool { * self == Drdy :: Valid } } # [doc = "Clock error current status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cecs { # [doc = "0: The RNG clock is correct (fRNGCLK> fHCLK/16). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered."] Correct = 0 , # [doc = "1: The RNG clock is too slow (fRNGCLK< fHCLK/16)"] TooSlow = 1 , } impl From < Cecs > for bool { # [inline (always)] fn from (variant : Cecs) -> Self { variant as u8 != 0 } } # [doc = "Field `CECS` reader - Clock error current status"] pub type CecsR = crate :: BitReader < Cecs > ; impl CecsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cecs { match self . bits { false => Cecs :: Correct , true => Cecs :: TooSlow , } } # [doc = "The RNG clock is correct (fRNGCLK> fHCLK/16). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered."] # [inline (always)] pub fn is_correct (& self) -> bool { * self == Cecs :: Correct } # [doc = "The RNG clock is too slow (fRNGCLK< fHCLK/16)"] # [inline (always)] pub fn is_too_slow (& self) -> bool { * self == Cecs :: TooSlow } } # [doc = "Seed error current status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Secs { # [doc = "0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered."] NoFaulty = 0 , # [doc = "1: One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bits patterns (“01” or “10”)"] Faulty = 1 , } impl From < Secs > for bool { # [inline (always)] fn from (variant : Secs) -> Self { variant as u8 != 0 } } # [doc = "Field `SECS` reader - Seed error current status"] pub type SecsR = crate :: BitReader < Secs > ; impl SecsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Secs { match self . bits { false => Secs :: NoFaulty , true => Secs :: Faulty , } } # [doc = "No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered."] # [inline (always)] pub fn is_no_faulty (& self) -> bool { * self == Secs :: NoFaulty } # [doc = "One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bits patterns (“01” or “10”)"] # [inline (always)] pub fn is_faulty (& self) -> bool { * self == Secs :: Faulty } } # [doc = "Clock error interrupt status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ceis { # [doc = "0: The RNG clock is correct (fRNGCLK > fHCLK/16)"] Correct = 0 , # [doc = "1: The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] TooSlow = 1 , } impl From < Ceis > for bool { # [inline (always)] fn from (variant : Ceis) -> Self { variant as u8 != 0 } } # [doc = "Field `CEIS` reader - Clock error interrupt status"] pub type CeisR = crate :: BitReader < Ceis > ; impl CeisR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ceis { match self . bits { false => Ceis :: Correct , true => Ceis :: TooSlow , } } # [doc = "The RNG clock is correct (fRNGCLK > fHCLK/16)"] # [inline (always)] pub fn is_correct (& self) -> bool { * self == Ceis :: Correct } # [doc = "The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] # [inline (always)] pub fn is_too_slow (& self) -> bool { * self == Ceis :: TooSlow } } # [doc = "Field `CEIS` writer - Clock error interrupt status"] pub type CeisW < 'a , REG > = crate :: BitWriter < 'a , REG , Ceis > ; impl < 'a , REG > CeisW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The RNG clock is correct (fRNGCLK > fHCLK/16)"] # [inline (always)] pub fn correct (self) -> & 'a mut crate :: W < REG > { self . variant (Ceis :: Correct) } # [doc = "The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] # [inline (always)] pub fn too_slow (self) -> & 'a mut crate :: W < REG > { self . variant (Ceis :: TooSlow) } } # [doc = "Seed error interrupt status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Seis { # [doc = "0: No faulty sequence detected"] NoFaulty = 0 , # [doc = "1: At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] Faulty = 1 , } impl From < Seis > for bool { # [inline (always)] fn from (variant : Seis) -> Self { variant as u8 != 0 } } # [doc = "Field `SEIS` reader - Seed error interrupt status"] pub type SeisR = crate :: BitReader < Seis > ; impl SeisR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Seis { match self . bits { false => Seis :: NoFaulty , true => Seis :: Faulty , } } # [doc = "No faulty sequence detected"] # [inline (always)] pub fn is_no_faulty (& self) -> bool { * self == Seis :: NoFaulty } # [doc = "At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] # [inline (always)] pub fn is_faulty (& self) -> bool { * self == Seis :: Faulty } } # [doc = "Field `SEIS` writer - Seed error interrupt status"] pub type SeisW < 'a , REG > = crate :: BitWriter < 'a , REG , Seis > ; impl < 'a , REG > SeisW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No faulty sequence detected"] # [inline (always)] pub fn no_faulty (self) -> & 'a mut crate :: W < REG > { self . variant (Seis :: NoFaulty) } # [doc = "At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] # [inline (always)] pub fn faulty (self) -> & 'a mut crate :: W < REG > { self . variant (Seis :: Faulty) } } impl R { # [doc = "Bit 0 - Data ready"] # [inline (always)] pub fn drdy (& self) -> DrdyR { DrdyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Clock error current status"] # [inline (always)] pub fn cecs (& self) -> CecsR { CecsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Seed error current status"] # [inline (always)] pub fn secs (& self) -> SecsR { SecsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - Clock error interrupt status"] # [inline (always)] pub fn ceis (& self) -> CeisR { CeisR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Seed error interrupt status"] # [inline (always)] pub fn seis (& self) -> SeisR { SeisR :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bit 5 - Clock error interrupt status"] # [inline (always)] pub fn ceis (& mut self) -> CeisW < SrSpec > { CeisW :: new (self , 5) } # [doc = "Bit 6 - Seed error interrupt status"] # [inline (always)] pub fn seis (& mut self) -> SeisW <'_, SrSpec > { SeisW :: new (self , 6) } } # [doc = "status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SrSpec ; impl crate :: RegisterSpec for SrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sr::R`](R) reader structure"] impl crate :: Readable for SrSpec { } # [doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] impl crate :: Writable for SrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SR to value 0"] impl crate :: Resettable for SrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4170 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # ... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW <'_, CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4300 [INFO] [stdout] | [INFO] [stdout] 1 | ...de"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline... [INFO] [stdout] | ^^^^^^^^^^ -------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW <'_, CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4422 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inli... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW <'_, CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4547 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronizat... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW <'_, CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4691 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] ... [INFO] [stdout] | ^^^^^^^^^^ --------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW <'_, CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4825 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchro... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW <'_, CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4979 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchroniza... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW <'_, CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:5129 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rat... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW <'_, CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:5274 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mo... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW <'_, CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:5410 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inli... [INFO] [stdout] | ^^^^^^^^^^ --------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW <'_, CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:5537 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nY... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW <'_, CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/ier.rs:1:2208 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn frame_ie (& mut self) -> FrameIeW < IerSpec > { FrameIeW :: new (self , 0) } # [doc = "Bit 1 - Overrun interrup... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `IER` reader"] pub type R = crate :: R < IerSpec > ; # [doc = "Register `IER` writer"] pub type W = crate :: W < IerSpec > ; # [doc = "Field `FRAME_IE` reader - Capture complete interrupt enable"] pub type FrameIeR = crate :: BitReader ; # [doc = "Field `FRAME_IE` writer - Capture complete interrupt enable"] pub type FrameIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVR_IE` reader - Overrun interrupt enable"] pub type OvrIeR = crate :: BitReader ; # [doc = "Field `OVR_IE` writer - Overrun interrupt enable"] pub type OvrIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERR_IE` reader - Synchronization error interrupt enable"] pub type ErrIeR = crate :: BitReader ; # [doc = "Field `ERR_IE` writer - Synchronization error interrupt enable"] pub type ErrIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSYNC_IE` reader - VSYNC interrupt enable"] pub type VsyncIeR = crate :: BitReader ; # [doc = "Field `VSYNC_IE` writer - VSYNC interrupt enable"] pub type VsyncIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LINE_IE` reader - Line interrupt enable"] pub type LineIeR = crate :: BitReader ; # [doc = "Field `LINE_IE` writer - Line interrupt enable"] pub type LineIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture complete interrupt enable"] # [inline (always)] pub fn frame_ie (& self) -> FrameIeR { FrameIeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Overrun interrupt enable"] # [inline (always)] pub fn ovr_ie (& self) -> OvrIeR { OvrIeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Synchronization error interrupt enable"] # [inline (always)] pub fn err_ie (& self) -> ErrIeR { ErrIeR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - VSYNC interrupt enable"] # [inline (always)] pub fn vsync_ie (& self) -> VsyncIeR { VsyncIeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Line interrupt enable"] # [inline (always)] pub fn line_ie (& self) -> LineIeR { LineIeR :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture complete interrupt enable"] # [inline (always)] pub fn frame_ie (& mut self) -> FrameIeW <'_, IerSpec > { FrameIeW :: new (self , 0) } # [doc = "Bit 1 - Overrun interrupt enable"] # [inline (always)] pub fn ovr_ie (& mut self) -> OvrIeW < IerSpec > { OvrIeW :: new (self , 1) } # [doc = "Bit 2 - Synchronization error interrupt enable"] # [inline (always)] pub fn err_ie (& mut self) -> ErrIeW < IerSpec > { ErrIeW :: new (self , 2) } # [doc = "Bit 3 - VSYNC interrupt enable"] # [inline (always)] pub fn vsync_ie (& mut self) -> VsyncIeW < IerSpec > { VsyncIeW :: new (self , 3) } # [doc = "Bit 4 - Line interrupt enable"] # [inline (always)] pub fn line_ie (& mut self) -> LineIeW < IerSpec > { LineIeW :: new (self , 4) } } # [doc = "interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IerSpec ; impl crate :: RegisterSpec for IerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ier::R`](R) reader structure"] impl crate :: Readable for IerSpec { } # [doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate :: Writable for IerSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets IER to value 0"] impl crate :: Resettable for IerSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/ier.rs:1:2355 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn ovr_ie (& mut self) -> OvrIeW < IerSpec > { OvrIeW :: new (self , 1) } # [doc = "Bit 2 - Synchronization err... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `IER` reader"] pub type R = crate :: R < IerSpec > ; # [doc = "Register `IER` writer"] pub type W = crate :: W < IerSpec > ; # [doc = "Field `FRAME_IE` reader - Capture complete interrupt enable"] pub type FrameIeR = crate :: BitReader ; # [doc = "Field `FRAME_IE` writer - Capture complete interrupt enable"] pub type FrameIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVR_IE` reader - Overrun interrupt enable"] pub type OvrIeR = crate :: BitReader ; # [doc = "Field `OVR_IE` writer - Overrun interrupt enable"] pub type OvrIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERR_IE` reader - Synchronization error interrupt enable"] pub type ErrIeR = crate :: BitReader ; # [doc = "Field `ERR_IE` writer - Synchronization error interrupt enable"] pub type ErrIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSYNC_IE` reader - VSYNC interrupt enable"] pub type VsyncIeR = crate :: BitReader ; # [doc = "Field `VSYNC_IE` writer - VSYNC interrupt enable"] pub type VsyncIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LINE_IE` reader - Line interrupt enable"] pub type LineIeR = crate :: BitReader ; # [doc = "Field `LINE_IE` writer - Line interrupt enable"] pub type LineIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture complete interrupt enable"] # [inline (always)] pub fn frame_ie (& self) -> FrameIeR { FrameIeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Overrun interrupt enable"] # [inline (always)] pub fn ovr_ie (& self) -> OvrIeR { OvrIeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Synchronization error interrupt enable"] # [inline (always)] pub fn err_ie (& self) -> ErrIeR { ErrIeR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - VSYNC interrupt enable"] # [inline (always)] pub fn vsync_ie (& self) -> VsyncIeR { VsyncIeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Line interrupt enable"] # [inline (always)] pub fn line_ie (& self) -> LineIeR { LineIeR :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture complete interrupt enable"] # [inline (always)] pub fn frame_ie (& mut self) -> FrameIeW < IerSpec > { FrameIeW :: new (self , 0) } # [doc = "Bit 1 - Overrun interrupt enable"] # [inline (always)] pub fn ovr_ie (& mut self) -> OvrIeW <'_, IerSpec > { OvrIeW :: new (self , 1) } # [doc = "Bit 2 - Synchronization error interrupt enable"] # [inline (always)] pub fn err_ie (& mut self) -> ErrIeW < IerSpec > { ErrIeW :: new (self , 2) } # [doc = "Bit 3 - VSYNC interrupt enable"] # [inline (always)] pub fn vsync_ie (& mut self) -> VsyncIeW < IerSpec > { VsyncIeW :: new (self , 3) } # [doc = "Bit 4 - Line interrupt enable"] # [inline (always)] pub fn line_ie (& mut self) -> LineIeW < IerSpec > { LineIeW :: new (self , 4) } } # [doc = "interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IerSpec ; impl crate :: RegisterSpec for IerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ier::R`](R) reader structure"] impl crate :: Readable for IerSpec { } # [doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate :: Writable for IerSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets IER to value 0"] impl crate :: Resettable for IerSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/ier.rs:1:2512 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn err_ie (& mut self) -> ErrIeW < IerSpec > { ErrIeW :: new (self , 2) } # [doc = "Bit 3 - VSYNC interrupt ena... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `IER` reader"] pub type R = crate :: R < IerSpec > ; # [doc = "Register `IER` writer"] pub type W = crate :: W < IerSpec > ; # [doc = "Field `FRAME_IE` reader - Capture complete interrupt enable"] pub type FrameIeR = crate :: BitReader ; # [doc = "Field `FRAME_IE` writer - Capture complete interrupt enable"] pub type FrameIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVR_IE` reader - Overrun interrupt enable"] pub type OvrIeR = crate :: BitReader ; # [doc = "Field `OVR_IE` writer - Overrun interrupt enable"] pub type OvrIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERR_IE` reader - Synchronization error interrupt enable"] pub type ErrIeR = crate :: BitReader ; # [doc = "Field `ERR_IE` writer - Synchronization error interrupt enable"] pub type ErrIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSYNC_IE` reader - VSYNC interrupt enable"] pub type VsyncIeR = crate :: BitReader ; # [doc = "Field `VSYNC_IE` writer - VSYNC interrupt enable"] pub type VsyncIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LINE_IE` reader - Line interrupt enable"] pub type LineIeR = crate :: BitReader ; # [doc = "Field `LINE_IE` writer - Line interrupt enable"] pub type LineIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture complete interrupt enable"] # [inline (always)] pub fn frame_ie (& self) -> FrameIeR { FrameIeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Overrun interrupt enable"] # [inline (always)] pub fn ovr_ie (& self) -> OvrIeR { OvrIeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Synchronization error interrupt enable"] # [inline (always)] pub fn err_ie (& self) -> ErrIeR { ErrIeR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - VSYNC interrupt enable"] # [inline (always)] pub fn vsync_ie (& self) -> VsyncIeR { VsyncIeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Line interrupt enable"] # [inline (always)] pub fn line_ie (& self) -> LineIeR { LineIeR :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture complete interrupt enable"] # [inline (always)] pub fn frame_ie (& mut self) -> FrameIeW < IerSpec > { FrameIeW :: new (self , 0) } # [doc = "Bit 1 - Overrun interrupt enable"] # [inline (always)] pub fn ovr_ie (& mut self) -> OvrIeW < IerSpec > { OvrIeW :: new (self , 1) } # [doc = "Bit 2 - Synchronization error interrupt enable"] # [inline (always)] pub fn err_ie (& mut self) -> ErrIeW <'_, IerSpec > { ErrIeW :: new (self , 2) } # [doc = "Bit 3 - VSYNC interrupt enable"] # [inline (always)] pub fn vsync_ie (& mut self) -> VsyncIeW < IerSpec > { VsyncIeW :: new (self , 3) } # [doc = "Bit 4 - Line interrupt enable"] # [inline (always)] pub fn line_ie (& mut self) -> LineIeW < IerSpec > { LineIeW :: new (self , 4) } } # [doc = "interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IerSpec ; impl crate :: RegisterSpec for IerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ier::R`](R) reader structure"] impl crate :: Readable for IerSpec { } # [doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate :: Writable for IerSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets IER to value 0"] impl crate :: Resettable for IerSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/ier.rs:1:2655 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn vsync_ie (& mut self) -> VsyncIeW < IerSpec > { VsyncIeW :: new (self , 3) } # [doc = "Bit 4 - Line interrupt e... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `IER` reader"] pub type R = crate :: R < IerSpec > ; # [doc = "Register `IER` writer"] pub type W = crate :: W < IerSpec > ; # [doc = "Field `FRAME_IE` reader - Capture complete interrupt enable"] pub type FrameIeR = crate :: BitReader ; # [doc = "Field `FRAME_IE` writer - Capture complete interrupt enable"] pub type FrameIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVR_IE` reader - Overrun interrupt enable"] pub type OvrIeR = crate :: BitReader ; # [doc = "Field `OVR_IE` writer - Overrun interrupt enable"] pub type OvrIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERR_IE` reader - Synchronization error interrupt enable"] pub type ErrIeR = crate :: BitReader ; # [doc = "Field `ERR_IE` writer - Synchronization error interrupt enable"] pub type ErrIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSYNC_IE` reader - VSYNC interrupt enable"] pub type VsyncIeR = crate :: BitReader ; # [doc = "Field `VSYNC_IE` writer - VSYNC interrupt enable"] pub type VsyncIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LINE_IE` reader - Line interrupt enable"] pub type LineIeR = crate :: BitReader ; # [doc = "Field `LINE_IE` writer - Line interrupt enable"] pub type LineIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture complete interrupt enable"] # [inline (always)] pub fn frame_ie (& self) -> FrameIeR { FrameIeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Overrun interrupt enable"] # [inline (always)] pub fn ovr_ie (& self) -> OvrIeR { OvrIeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Synchronization error interrupt enable"] # [inline (always)] pub fn err_ie (& self) -> ErrIeR { ErrIeR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - VSYNC interrupt enable"] # [inline (always)] pub fn vsync_ie (& self) -> VsyncIeR { VsyncIeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Line interrupt enable"] # [inline (always)] pub fn line_ie (& self) -> LineIeR { LineIeR :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture complete interrupt enable"] # [inline (always)] pub fn frame_ie (& mut self) -> FrameIeW < IerSpec > { FrameIeW :: new (self , 0) } # [doc = "Bit 1 - Overrun interrupt enable"] # [inline (always)] pub fn ovr_ie (& mut self) -> OvrIeW < IerSpec > { OvrIeW :: new (self , 1) } # [doc = "Bit 2 - Synchronization error interrupt enable"] # [inline (always)] pub fn err_ie (& mut self) -> ErrIeW < IerSpec > { ErrIeW :: new (self , 2) } # [doc = "Bit 3 - VSYNC interrupt enable"] # [inline (always)] pub fn vsync_ie (& mut self) -> VsyncIeW <'_, IerSpec > { VsyncIeW :: new (self , 3) } # [doc = "Bit 4 - Line interrupt enable"] # [inline (always)] pub fn line_ie (& mut self) -> LineIeW < IerSpec > { LineIeW :: new (self , 4) } } # [doc = "interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IerSpec ; impl crate :: RegisterSpec for IerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ier::R`](R) reader structure"] impl crate :: Readable for IerSpec { } # [doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate :: Writable for IerSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets IER to value 0"] impl crate :: Resettable for IerSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/ier.rs:1:2800 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn line_ie (& mut self) -> LineIeW < IerSpec > { LineIeW :: new (self , 4) } } # [doc = "interrupt enable registe... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `IER` reader"] pub type R = crate :: R < IerSpec > ; # [doc = "Register `IER` writer"] pub type W = crate :: W < IerSpec > ; # [doc = "Field `FRAME_IE` reader - Capture complete interrupt enable"] pub type FrameIeR = crate :: BitReader ; # [doc = "Field `FRAME_IE` writer - Capture complete interrupt enable"] pub type FrameIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVR_IE` reader - Overrun interrupt enable"] pub type OvrIeR = crate :: BitReader ; # [doc = "Field `OVR_IE` writer - Overrun interrupt enable"] pub type OvrIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERR_IE` reader - Synchronization error interrupt enable"] pub type ErrIeR = crate :: BitReader ; # [doc = "Field `ERR_IE` writer - Synchronization error interrupt enable"] pub type ErrIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSYNC_IE` reader - VSYNC interrupt enable"] pub type VsyncIeR = crate :: BitReader ; # [doc = "Field `VSYNC_IE` writer - VSYNC interrupt enable"] pub type VsyncIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LINE_IE` reader - Line interrupt enable"] pub type LineIeR = crate :: BitReader ; # [doc = "Field `LINE_IE` writer - Line interrupt enable"] pub type LineIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture complete interrupt enable"] # [inline (always)] pub fn frame_ie (& self) -> FrameIeR { FrameIeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Overrun interrupt enable"] # [inline (always)] pub fn ovr_ie (& self) -> OvrIeR { OvrIeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Synchronization error interrupt enable"] # [inline (always)] pub fn err_ie (& self) -> ErrIeR { ErrIeR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - VSYNC interrupt enable"] # [inline (always)] pub fn vsync_ie (& self) -> VsyncIeR { VsyncIeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Line interrupt enable"] # [inline (always)] pub fn line_ie (& self) -> LineIeR { LineIeR :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture complete interrupt enable"] # [inline (always)] pub fn frame_ie (& mut self) -> FrameIeW < IerSpec > { FrameIeW :: new (self , 0) } # [doc = "Bit 1 - Overrun interrupt enable"] # [inline (always)] pub fn ovr_ie (& mut self) -> OvrIeW < IerSpec > { OvrIeW :: new (self , 1) } # [doc = "Bit 2 - Synchronization error interrupt enable"] # [inline (always)] pub fn err_ie (& mut self) -> ErrIeW < IerSpec > { ErrIeW :: new (self , 2) } # [doc = "Bit 3 - VSYNC interrupt enable"] # [inline (always)] pub fn vsync_ie (& mut self) -> VsyncIeW < IerSpec > { VsyncIeW :: new (self , 3) } # [doc = "Bit 4 - Line interrupt enable"] # [inline (always)] pub fn line_ie (& mut self) -> LineIeW <'_, IerSpec > { LineIeW :: new (self , 4) } } # [doc = "interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IerSpec ; impl crate :: RegisterSpec for IerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ier::R`](R) reader structure"] impl crate :: Readable for IerSpec { } # [doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate :: Writable for IerSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets IER to value 0"] impl crate :: Resettable for IerSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/icr.rs:1:887 [INFO] [stdout] | [INFO] [stdout] 1 | ...ine (always)] pub fn frame_isc (& mut self) -> FrameIscW < IcrSpec > { FrameIscW :: new (self , 0) } # [doc = "Bit 1 - Overrun interru... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ICR` writer"] pub type W = crate :: W < IcrSpec > ; # [doc = "Field `FRAME_ISC` writer - Capture complete interrupt status clear"] pub type FrameIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVR_ISC` writer - Overrun interrupt status clear"] pub type OvrIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERR_ISC` writer - Synchronization error interrupt status clear"] pub type ErrIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSYNC_ISC` writer - Vertical synch interrupt status clear"] pub type VsyncIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LINE_ISC` writer - line interrupt status clear"] pub type LineIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Capture complete interrupt status clear"] # [inline (always)] pub fn frame_isc (& mut self) -> FrameIscW <'_, IcrSpec > { FrameIscW :: new (self , 0) } # [doc = "Bit 1 - Overrun interrupt status clear"] # [inline (always)] pub fn ovr_isc (& mut self) -> OvrIscW < IcrSpec > { OvrIscW :: new (self , 1) } # [doc = "Bit 2 - Synchronization error interrupt status clear"] # [inline (always)] pub fn err_isc (& mut self) -> ErrIscW < IcrSpec > { ErrIscW :: new (self , 2) } # [doc = "Bit 3 - Vertical synch interrupt status clear"] # [inline (always)] pub fn vsync_isc (& mut self) -> VsyncIscW < IcrSpec > { VsyncIscW :: new (self , 3) } # [doc = "Bit 4 - line interrupt status clear"] # [inline (always)] pub fn line_isc (& mut self) -> LineIscW < IcrSpec > { LineIscW :: new (self , 4) } } # [doc = "interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IcrSpec ; impl crate :: RegisterSpec for IcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] impl crate :: Writable for IcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ICR to value 0"] impl crate :: Resettable for IcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/icr.rs:1:1043 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn ovr_isc (& mut self) -> OvrIscW < IcrSpec > { OvrIscW :: new (self , 1) } # [doc = "Bit 2 - Synchronization er... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ICR` writer"] pub type W = crate :: W < IcrSpec > ; # [doc = "Field `FRAME_ISC` writer - Capture complete interrupt status clear"] pub type FrameIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVR_ISC` writer - Overrun interrupt status clear"] pub type OvrIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERR_ISC` writer - Synchronization error interrupt status clear"] pub type ErrIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSYNC_ISC` writer - Vertical synch interrupt status clear"] pub type VsyncIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LINE_ISC` writer - line interrupt status clear"] pub type LineIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Capture complete interrupt status clear"] # [inline (always)] pub fn frame_isc (& mut self) -> FrameIscW < IcrSpec > { FrameIscW :: new (self , 0) } # [doc = "Bit 1 - Overrun interrupt status clear"] # [inline (always)] pub fn ovr_isc (& mut self) -> OvrIscW <'_, IcrSpec > { OvrIscW :: new (self , 1) } # [doc = "Bit 2 - Synchronization error interrupt status clear"] # [inline (always)] pub fn err_isc (& mut self) -> ErrIscW < IcrSpec > { ErrIscW :: new (self , 2) } # [doc = "Bit 3 - Vertical synch interrupt status clear"] # [inline (always)] pub fn vsync_isc (& mut self) -> VsyncIscW < IcrSpec > { VsyncIscW :: new (self , 3) } # [doc = "Bit 4 - line interrupt status clear"] # [inline (always)] pub fn line_isc (& mut self) -> LineIscW < IcrSpec > { LineIscW :: new (self , 4) } } # [doc = "interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IcrSpec ; impl crate :: RegisterSpec for IcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] impl crate :: Writable for IcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ICR to value 0"] impl crate :: Resettable for IcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/icr.rs:1:1209 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn err_isc (& mut self) -> ErrIscW < IcrSpec > { ErrIscW :: new (self , 2) } # [doc = "Bit 3 - Vertical synch int... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ICR` writer"] pub type W = crate :: W < IcrSpec > ; # [doc = "Field `FRAME_ISC` writer - Capture complete interrupt status clear"] pub type FrameIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVR_ISC` writer - Overrun interrupt status clear"] pub type OvrIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERR_ISC` writer - Synchronization error interrupt status clear"] pub type ErrIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSYNC_ISC` writer - Vertical synch interrupt status clear"] pub type VsyncIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LINE_ISC` writer - line interrupt status clear"] pub type LineIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Capture complete interrupt status clear"] # [inline (always)] pub fn frame_isc (& mut self) -> FrameIscW < IcrSpec > { FrameIscW :: new (self , 0) } # [doc = "Bit 1 - Overrun interrupt status clear"] # [inline (always)] pub fn ovr_isc (& mut self) -> OvrIscW < IcrSpec > { OvrIscW :: new (self , 1) } # [doc = "Bit 2 - Synchronization error interrupt status clear"] # [inline (always)] pub fn err_isc (& mut self) -> ErrIscW <'_, IcrSpec > { ErrIscW :: new (self , 2) } # [doc = "Bit 3 - Vertical synch interrupt status clear"] # [inline (always)] pub fn vsync_isc (& mut self) -> VsyncIscW < IcrSpec > { VsyncIscW :: new (self , 3) } # [doc = "Bit 4 - line interrupt status clear"] # [inline (always)] pub fn line_isc (& mut self) -> LineIscW < IcrSpec > { LineIscW :: new (self , 4) } } # [doc = "interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IcrSpec ; impl crate :: RegisterSpec for IcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] impl crate :: Writable for IcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ICR to value 0"] impl crate :: Resettable for IcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/icr.rs:1:1370 [INFO] [stdout] | [INFO] [stdout] 1 | ...ine (always)] pub fn vsync_isc (& mut self) -> VsyncIscW < IcrSpec > { VsyncIscW :: new (self , 3) } # [doc = "Bit 4 - line interrupt ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ICR` writer"] pub type W = crate :: W < IcrSpec > ; # [doc = "Field `FRAME_ISC` writer - Capture complete interrupt status clear"] pub type FrameIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVR_ISC` writer - Overrun interrupt status clear"] pub type OvrIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERR_ISC` writer - Synchronization error interrupt status clear"] pub type ErrIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSYNC_ISC` writer - Vertical synch interrupt status clear"] pub type VsyncIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LINE_ISC` writer - line interrupt status clear"] pub type LineIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Capture complete interrupt status clear"] # [inline (always)] pub fn frame_isc (& mut self) -> FrameIscW < IcrSpec > { FrameIscW :: new (self , 0) } # [doc = "Bit 1 - Overrun interrupt status clear"] # [inline (always)] pub fn ovr_isc (& mut self) -> OvrIscW < IcrSpec > { OvrIscW :: new (self , 1) } # [doc = "Bit 2 - Synchronization error interrupt status clear"] # [inline (always)] pub fn err_isc (& mut self) -> ErrIscW < IcrSpec > { ErrIscW :: new (self , 2) } # [doc = "Bit 3 - Vertical synch interrupt status clear"] # [inline (always)] pub fn vsync_isc (& mut self) -> VsyncIscW <'_, IcrSpec > { VsyncIscW :: new (self , 3) } # [doc = "Bit 4 - line interrupt status clear"] # [inline (always)] pub fn line_isc (& mut self) -> LineIscW < IcrSpec > { LineIscW :: new (self , 4) } } # [doc = "interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IcrSpec ; impl crate :: RegisterSpec for IcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] impl crate :: Writable for IcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ICR to value 0"] impl crate :: Resettable for IcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/icr.rs:1:1524 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn line_isc (& mut self) -> LineIscW < IcrSpec > { LineIscW :: new (self , 4) } } # [doc = "interrupt clear regist... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ICR` writer"] pub type W = crate :: W < IcrSpec > ; # [doc = "Field `FRAME_ISC` writer - Capture complete interrupt status clear"] pub type FrameIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVR_ISC` writer - Overrun interrupt status clear"] pub type OvrIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERR_ISC` writer - Synchronization error interrupt status clear"] pub type ErrIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSYNC_ISC` writer - Vertical synch interrupt status clear"] pub type VsyncIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LINE_ISC` writer - line interrupt status clear"] pub type LineIscW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Capture complete interrupt status clear"] # [inline (always)] pub fn frame_isc (& mut self) -> FrameIscW < IcrSpec > { FrameIscW :: new (self , 0) } # [doc = "Bit 1 - Overrun interrupt status clear"] # [inline (always)] pub fn ovr_isc (& mut self) -> OvrIscW < IcrSpec > { OvrIscW :: new (self , 1) } # [doc = "Bit 2 - Synchronization error interrupt status clear"] # [inline (always)] pub fn err_isc (& mut self) -> ErrIscW < IcrSpec > { ErrIscW :: new (self , 2) } # [doc = "Bit 3 - Vertical synch interrupt status clear"] # [inline (always)] pub fn vsync_isc (& mut self) -> VsyncIscW < IcrSpec > { VsyncIscW :: new (self , 3) } # [doc = "Bit 4 - line interrupt status clear"] # [inline (always)] pub fn line_isc (& mut self) -> LineIscW <'_, IcrSpec > { LineIscW :: new (self , 4) } } # [doc = "interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IcrSpec ; impl crate :: RegisterSpec for IcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] impl crate :: Writable for IcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ICR to value 0"] impl crate :: Resettable for IcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/escr.rs:1:1745 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn fsc (& mut self) -> FscW < EscrSpec > { FscW :: new (self , 0) } # [doc = "Bits 8:15 - Line start delimit... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ESCR` reader"] pub type R = crate :: R < EscrSpec > ; # [doc = "Register `ESCR` writer"] pub type W = crate :: W < EscrSpec > ; # [doc = "Field `FSC` reader - Frame start delimiter code"] pub type FscR = crate :: FieldReader ; # [doc = "Field `FSC` writer - Frame start delimiter code"] pub type FscW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LSC` reader - Line start delimiter code"] pub type LscR = crate :: FieldReader ; # [doc = "Field `LSC` writer - Line start delimiter code"] pub type LscW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LEC` reader - Line end delimiter code"] pub type LecR = crate :: FieldReader ; # [doc = "Field `LEC` writer - Line end delimiter code"] pub type LecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `FEC` reader - Frame end delimiter code"] pub type FecR = crate :: FieldReader ; # [doc = "Field `FEC` writer - Frame end delimiter code"] pub type FecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - Frame start delimiter code"] # [inline (always)] pub fn fsc (& self) -> FscR { FscR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - Line start delimiter code"] # [inline (always)] pub fn lsc (& self) -> LscR { LscR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - Line end delimiter code"] # [inline (always)] pub fn lec (& self) -> LecR { LecR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - Frame end delimiter code"] # [inline (always)] pub fn fec (& self) -> FecR { FecR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Frame start delimiter code"] # [inline (always)] pub fn fsc (& mut self) -> FscW <'_, EscrSpec > { FscW :: new (self , 0) } # [doc = "Bits 8:15 - Line start delimiter code"] # [inline (always)] pub fn lsc (& mut self) -> LscW < EscrSpec > { LscW :: new (self , 8) } # [doc = "Bits 16:23 - Line end delimiter code"] # [inline (always)] pub fn lec (& mut self) -> LecW < EscrSpec > { LecW :: new (self , 16) } # [doc = "Bits 24:31 - Frame end delimiter code"] # [inline (always)] pub fn fec (& mut self) -> FecW < EscrSpec > { FecW :: new (self , 24) } } # [doc = "embedded synchronization code register\n\nYou can [`read`](crate::Reg::read) this register and get [`escr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`escr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EscrSpec ; impl crate :: RegisterSpec for EscrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`escr::R`](R) reader structure"] impl crate :: Readable for EscrSpec { } # [doc = "`write(|w| ..)` method takes [`escr::W`](W) writer structure"] impl crate :: Writable for EscrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ESCR to value 0"] impl crate :: Resettable for EscrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/escr.rs:1:1887 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn lsc (& mut self) -> LscW < EscrSpec > { LscW :: new (self , 8) } # [doc = "Bits 16:23 - Line end delimite... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ESCR` reader"] pub type R = crate :: R < EscrSpec > ; # [doc = "Register `ESCR` writer"] pub type W = crate :: W < EscrSpec > ; # [doc = "Field `FSC` reader - Frame start delimiter code"] pub type FscR = crate :: FieldReader ; # [doc = "Field `FSC` writer - Frame start delimiter code"] pub type FscW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LSC` reader - Line start delimiter code"] pub type LscR = crate :: FieldReader ; # [doc = "Field `LSC` writer - Line start delimiter code"] pub type LscW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LEC` reader - Line end delimiter code"] pub type LecR = crate :: FieldReader ; # [doc = "Field `LEC` writer - Line end delimiter code"] pub type LecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `FEC` reader - Frame end delimiter code"] pub type FecR = crate :: FieldReader ; # [doc = "Field `FEC` writer - Frame end delimiter code"] pub type FecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - Frame start delimiter code"] # [inline (always)] pub fn fsc (& self) -> FscR { FscR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - Line start delimiter code"] # [inline (always)] pub fn lsc (& self) -> LscR { LscR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - Line end delimiter code"] # [inline (always)] pub fn lec (& self) -> LecR { LecR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - Frame end delimiter code"] # [inline (always)] pub fn fec (& self) -> FecR { FecR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Frame start delimiter code"] # [inline (always)] pub fn fsc (& mut self) -> FscW < EscrSpec > { FscW :: new (self , 0) } # [doc = "Bits 8:15 - Line start delimiter code"] # [inline (always)] pub fn lsc (& mut self) -> LscW <'_, EscrSpec > { LscW :: new (self , 8) } # [doc = "Bits 16:23 - Line end delimiter code"] # [inline (always)] pub fn lec (& mut self) -> LecW < EscrSpec > { LecW :: new (self , 16) } # [doc = "Bits 24:31 - Frame end delimiter code"] # [inline (always)] pub fn fec (& mut self) -> FecW < EscrSpec > { FecW :: new (self , 24) } } # [doc = "embedded synchronization code register\n\nYou can [`read`](crate::Reg::read) this register and get [`escr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`escr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EscrSpec ; impl crate :: RegisterSpec for EscrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`escr::R`](R) reader structure"] impl crate :: Readable for EscrSpec { } # [doc = "`write(|w| ..)` method takes [`escr::W`](W) writer structure"] impl crate :: Writable for EscrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ESCR to value 0"] impl crate :: Resettable for EscrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/escr.rs:1:2028 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn lec (& mut self) -> LecW < EscrSpec > { LecW :: new (self , 16) } # [doc = "Bits 24:31 - Frame end delimi... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ESCR` reader"] pub type R = crate :: R < EscrSpec > ; # [doc = "Register `ESCR` writer"] pub type W = crate :: W < EscrSpec > ; # [doc = "Field `FSC` reader - Frame start delimiter code"] pub type FscR = crate :: FieldReader ; # [doc = "Field `FSC` writer - Frame start delimiter code"] pub type FscW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LSC` reader - Line start delimiter code"] pub type LscR = crate :: FieldReader ; # [doc = "Field `LSC` writer - Line start delimiter code"] pub type LscW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LEC` reader - Line end delimiter code"] pub type LecR = crate :: FieldReader ; # [doc = "Field `LEC` writer - Line end delimiter code"] pub type LecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `FEC` reader - Frame end delimiter code"] pub type FecR = crate :: FieldReader ; # [doc = "Field `FEC` writer - Frame end delimiter code"] pub type FecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - Frame start delimiter code"] # [inline (always)] pub fn fsc (& self) -> FscR { FscR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - Line start delimiter code"] # [inline (always)] pub fn lsc (& self) -> LscR { LscR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - Line end delimiter code"] # [inline (always)] pub fn lec (& self) -> LecR { LecR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - Frame end delimiter code"] # [inline (always)] pub fn fec (& self) -> FecR { FecR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Frame start delimiter code"] # [inline (always)] pub fn fsc (& mut self) -> FscW < EscrSpec > { FscW :: new (self , 0) } # [doc = "Bits 8:15 - Line start delimiter code"] # [inline (always)] pub fn lsc (& mut self) -> LscW < EscrSpec > { LscW :: new (self , 8) } # [doc = "Bits 16:23 - Line end delimiter code"] # [inline (always)] pub fn lec (& mut self) -> LecW <'_, EscrSpec > { LecW :: new (self , 16) } # [doc = "Bits 24:31 - Frame end delimiter code"] # [inline (always)] pub fn fec (& mut self) -> FecW < EscrSpec > { FecW :: new (self , 24) } } # [doc = "embedded synchronization code register\n\nYou can [`read`](crate::Reg::read) this register and get [`escr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`escr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EscrSpec ; impl crate :: RegisterSpec for EscrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`escr::R`](R) reader structure"] impl crate :: Readable for EscrSpec { } # [doc = "`write(|w| ..)` method takes [`escr::W`](W) writer structure"] impl crate :: Writable for EscrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ESCR to value 0"] impl crate :: Resettable for EscrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/escr.rs:1:2171 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn fec (& mut self) -> FecW < EscrSpec > { FecW :: new (self , 24) } } # [doc = "embedded synchronization co... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ESCR` reader"] pub type R = crate :: R < EscrSpec > ; # [doc = "Register `ESCR` writer"] pub type W = crate :: W < EscrSpec > ; # [doc = "Field `FSC` reader - Frame start delimiter code"] pub type FscR = crate :: FieldReader ; # [doc = "Field `FSC` writer - Frame start delimiter code"] pub type FscW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LSC` reader - Line start delimiter code"] pub type LscR = crate :: FieldReader ; # [doc = "Field `LSC` writer - Line start delimiter code"] pub type LscW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LEC` reader - Line end delimiter code"] pub type LecR = crate :: FieldReader ; # [doc = "Field `LEC` writer - Line end delimiter code"] pub type LecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `FEC` reader - Frame end delimiter code"] pub type FecR = crate :: FieldReader ; # [doc = "Field `FEC` writer - Frame end delimiter code"] pub type FecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - Frame start delimiter code"] # [inline (always)] pub fn fsc (& self) -> FscR { FscR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - Line start delimiter code"] # [inline (always)] pub fn lsc (& self) -> LscR { LscR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - Line end delimiter code"] # [inline (always)] pub fn lec (& self) -> LecR { LecR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - Frame end delimiter code"] # [inline (always)] pub fn fec (& self) -> FecR { FecR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Frame start delimiter code"] # [inline (always)] pub fn fsc (& mut self) -> FscW < EscrSpec > { FscW :: new (self , 0) } # [doc = "Bits 8:15 - Line start delimiter code"] # [inline (always)] pub fn lsc (& mut self) -> LscW < EscrSpec > { LscW :: new (self , 8) } # [doc = "Bits 16:23 - Line end delimiter code"] # [inline (always)] pub fn lec (& mut self) -> LecW < EscrSpec > { LecW :: new (self , 16) } # [doc = "Bits 24:31 - Frame end delimiter code"] # [inline (always)] pub fn fec (& mut self) -> FecW <'_, EscrSpec > { FecW :: new (self , 24) } } # [doc = "embedded synchronization code register\n\nYou can [`read`](crate::Reg::read) this register and get [`escr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`escr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EscrSpec ; impl crate :: RegisterSpec for EscrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`escr::R`](R) reader structure"] impl crate :: Readable for EscrSpec { } # [doc = "`write(|w| ..)` method takes [`escr::W`](W) writer structure"] impl crate :: Writable for EscrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ESCR to value 0"] impl crate :: Resettable for EscrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/esur.rs:1:1771 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn fsu (& mut self) -> FsuW < EsurSpec > { FsuW :: new (self , 0) } # [doc = "Bits 8:15 - Line start delimit... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ESUR` reader"] pub type R = crate :: R < EsurSpec > ; # [doc = "Register `ESUR` writer"] pub type W = crate :: W < EsurSpec > ; # [doc = "Field `FSU` reader - Frame start delimiter unmask"] pub type FsuR = crate :: FieldReader ; # [doc = "Field `FSU` writer - Frame start delimiter unmask"] pub type FsuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LSU` reader - Line start delimiter unmask"] pub type LsuR = crate :: FieldReader ; # [doc = "Field `LSU` writer - Line start delimiter unmask"] pub type LsuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LEU` reader - Line end delimiter unmask"] pub type LeuR = crate :: FieldReader ; # [doc = "Field `LEU` writer - Line end delimiter unmask"] pub type LeuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `FEU` reader - Frame end delimiter unmask"] pub type FeuR = crate :: FieldReader ; # [doc = "Field `FEU` writer - Frame end delimiter unmask"] pub type FeuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - Frame start delimiter unmask"] # [inline (always)] pub fn fsu (& self) -> FsuR { FsuR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - Line start delimiter unmask"] # [inline (always)] pub fn lsu (& self) -> LsuR { LsuR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - Line end delimiter unmask"] # [inline (always)] pub fn leu (& self) -> LeuR { LeuR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - Frame end delimiter unmask"] # [inline (always)] pub fn feu (& self) -> FeuR { FeuR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Frame start delimiter unmask"] # [inline (always)] pub fn fsu (& mut self) -> FsuW <'_, EsurSpec > { FsuW :: new (self , 0) } # [doc = "Bits 8:15 - Line start delimiter unmask"] # [inline (always)] pub fn lsu (& mut self) -> LsuW < EsurSpec > { LsuW :: new (self , 8) } # [doc = "Bits 16:23 - Line end delimiter unmask"] # [inline (always)] pub fn leu (& mut self) -> LeuW < EsurSpec > { LeuW :: new (self , 16) } # [doc = "Bits 24:31 - Frame end delimiter unmask"] # [inline (always)] pub fn feu (& mut self) -> FeuW < EsurSpec > { FeuW :: new (self , 24) } } # [doc = "embedded synchronization unmask register\n\nYou can [`read`](crate::Reg::read) this register and get [`esur::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esur::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EsurSpec ; impl crate :: RegisterSpec for EsurSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esur::R`](R) reader structure"] impl crate :: Readable for EsurSpec { } # [doc = "`write(|w| ..)` method takes [`esur::W`](W) writer structure"] impl crate :: Writable for EsurSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ESUR to value 0"] impl crate :: Resettable for EsurSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/esur.rs:1:1915 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn lsu (& mut self) -> LsuW < EsurSpec > { LsuW :: new (self , 8) } # [doc = "Bits 16:23 - Line end delimite... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ESUR` reader"] pub type R = crate :: R < EsurSpec > ; # [doc = "Register `ESUR` writer"] pub type W = crate :: W < EsurSpec > ; # [doc = "Field `FSU` reader - Frame start delimiter unmask"] pub type FsuR = crate :: FieldReader ; # [doc = "Field `FSU` writer - Frame start delimiter unmask"] pub type FsuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LSU` reader - Line start delimiter unmask"] pub type LsuR = crate :: FieldReader ; # [doc = "Field `LSU` writer - Line start delimiter unmask"] pub type LsuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LEU` reader - Line end delimiter unmask"] pub type LeuR = crate :: FieldReader ; # [doc = "Field `LEU` writer - Line end delimiter unmask"] pub type LeuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `FEU` reader - Frame end delimiter unmask"] pub type FeuR = crate :: FieldReader ; # [doc = "Field `FEU` writer - Frame end delimiter unmask"] pub type FeuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - Frame start delimiter unmask"] # [inline (always)] pub fn fsu (& self) -> FsuR { FsuR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - Line start delimiter unmask"] # [inline (always)] pub fn lsu (& self) -> LsuR { LsuR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - Line end delimiter unmask"] # [inline (always)] pub fn leu (& self) -> LeuR { LeuR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - Frame end delimiter unmask"] # [inline (always)] pub fn feu (& self) -> FeuR { FeuR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Frame start delimiter unmask"] # [inline (always)] pub fn fsu (& mut self) -> FsuW < EsurSpec > { FsuW :: new (self , 0) } # [doc = "Bits 8:15 - Line start delimiter unmask"] # [inline (always)] pub fn lsu (& mut self) -> LsuW <'_, EsurSpec > { LsuW :: new (self , 8) } # [doc = "Bits 16:23 - Line end delimiter unmask"] # [inline (always)] pub fn leu (& mut self) -> LeuW < EsurSpec > { LeuW :: new (self , 16) } # [doc = "Bits 24:31 - Frame end delimiter unmask"] # [inline (always)] pub fn feu (& mut self) -> FeuW < EsurSpec > { FeuW :: new (self , 24) } } # [doc = "embedded synchronization unmask register\n\nYou can [`read`](crate::Reg::read) this register and get [`esur::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esur::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EsurSpec ; impl crate :: RegisterSpec for EsurSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esur::R`](R) reader structure"] impl crate :: Readable for EsurSpec { } # [doc = "`write(|w| ..)` method takes [`esur::W`](W) writer structure"] impl crate :: Writable for EsurSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ESUR to value 0"] impl crate :: Resettable for EsurSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/esur.rs:1:2058 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn leu (& mut self) -> LeuW < EsurSpec > { LeuW :: new (self , 16) } # [doc = "Bits 24:31 - Frame end delimi... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ESUR` reader"] pub type R = crate :: R < EsurSpec > ; # [doc = "Register `ESUR` writer"] pub type W = crate :: W < EsurSpec > ; # [doc = "Field `FSU` reader - Frame start delimiter unmask"] pub type FsuR = crate :: FieldReader ; # [doc = "Field `FSU` writer - Frame start delimiter unmask"] pub type FsuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LSU` reader - Line start delimiter unmask"] pub type LsuR = crate :: FieldReader ; # [doc = "Field `LSU` writer - Line start delimiter unmask"] pub type LsuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LEU` reader - Line end delimiter unmask"] pub type LeuR = crate :: FieldReader ; # [doc = "Field `LEU` writer - Line end delimiter unmask"] pub type LeuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `FEU` reader - Frame end delimiter unmask"] pub type FeuR = crate :: FieldReader ; # [doc = "Field `FEU` writer - Frame end delimiter unmask"] pub type FeuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - Frame start delimiter unmask"] # [inline (always)] pub fn fsu (& self) -> FsuR { FsuR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - Line start delimiter unmask"] # [inline (always)] pub fn lsu (& self) -> LsuR { LsuR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - Line end delimiter unmask"] # [inline (always)] pub fn leu (& self) -> LeuR { LeuR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - Frame end delimiter unmask"] # [inline (always)] pub fn feu (& self) -> FeuR { FeuR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Frame start delimiter unmask"] # [inline (always)] pub fn fsu (& mut self) -> FsuW < EsurSpec > { FsuW :: new (self , 0) } # [doc = "Bits 8:15 - Line start delimiter unmask"] # [inline (always)] pub fn lsu (& mut self) -> LsuW < EsurSpec > { LsuW :: new (self , 8) } # [doc = "Bits 16:23 - Line end delimiter unmask"] # [inline (always)] pub fn leu (& mut self) -> LeuW <'_, EsurSpec > { LeuW :: new (self , 16) } # [doc = "Bits 24:31 - Frame end delimiter unmask"] # [inline (always)] pub fn feu (& mut self) -> FeuW < EsurSpec > { FeuW :: new (self , 24) } } # [doc = "embedded synchronization unmask register\n\nYou can [`read`](crate::Reg::read) this register and get [`esur::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esur::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EsurSpec ; impl crate :: RegisterSpec for EsurSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esur::R`](R) reader structure"] impl crate :: Readable for EsurSpec { } # [doc = "`write(|w| ..)` method takes [`esur::W`](W) writer structure"] impl crate :: Writable for EsurSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ESUR to value 0"] impl crate :: Resettable for EsurSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/esur.rs:1:2203 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn feu (& mut self) -> FeuW < EsurSpec > { FeuW :: new (self , 24) } } # [doc = "embedded synchronization un... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `ESUR` reader"] pub type R = crate :: R < EsurSpec > ; # [doc = "Register `ESUR` writer"] pub type W = crate :: W < EsurSpec > ; # [doc = "Field `FSU` reader - Frame start delimiter unmask"] pub type FsuR = crate :: FieldReader ; # [doc = "Field `FSU` writer - Frame start delimiter unmask"] pub type FsuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LSU` reader - Line start delimiter unmask"] pub type LsuR = crate :: FieldReader ; # [doc = "Field `LSU` writer - Line start delimiter unmask"] pub type LsuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LEU` reader - Line end delimiter unmask"] pub type LeuR = crate :: FieldReader ; # [doc = "Field `LEU` writer - Line end delimiter unmask"] pub type LeuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `FEU` reader - Frame end delimiter unmask"] pub type FeuR = crate :: FieldReader ; # [doc = "Field `FEU` writer - Frame end delimiter unmask"] pub type FeuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - Frame start delimiter unmask"] # [inline (always)] pub fn fsu (& self) -> FsuR { FsuR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - Line start delimiter unmask"] # [inline (always)] pub fn lsu (& self) -> LsuR { LsuR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - Line end delimiter unmask"] # [inline (always)] pub fn leu (& self) -> LeuR { LeuR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - Frame end delimiter unmask"] # [inline (always)] pub fn feu (& self) -> FeuR { FeuR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Frame start delimiter unmask"] # [inline (always)] pub fn fsu (& mut self) -> FsuW < EsurSpec > { FsuW :: new (self , 0) } # [doc = "Bits 8:15 - Line start delimiter unmask"] # [inline (always)] pub fn lsu (& mut self) -> LsuW < EsurSpec > { LsuW :: new (self , 8) } # [doc = "Bits 16:23 - Line end delimiter unmask"] # [inline (always)] pub fn leu (& mut self) -> LeuW < EsurSpec > { LeuW :: new (self , 16) } # [doc = "Bits 24:31 - Frame end delimiter unmask"] # [inline (always)] pub fn feu (& mut self) -> FeuW <'_, EsurSpec > { FeuW :: new (self , 24) } } # [doc = "embedded synchronization unmask register\n\nYou can [`read`](crate::Reg::read) this register and get [`esur::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esur::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EsurSpec ; impl crate :: RegisterSpec for EsurSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esur::R`](R) reader structure"] impl crate :: Readable for EsurSpec { } # [doc = "`write(|w| ..)` method takes [`esur::W`](W) writer structure"] impl crate :: Writable for EsurSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets ESUR to value 0"] impl crate :: Resettable for EsurSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cwstrt.rs:1:1066 [INFO] [stdout] | [INFO] [stdout] 1 | ...line (always)] pub fn hoffcnt (& mut self) -> HoffcntW < CwstrtSpec > { HoffcntW :: new (self , 0) } # [doc = "Bits 16:28 - Vertical s... [INFO] [stdout] | ^^^^^^^^^^ ----------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CWSTRT` reader"] pub type R = crate :: R < CwstrtSpec > ; # [doc = "Register `CWSTRT` writer"] pub type W = crate :: W < CwstrtSpec > ; # [doc = "Field `HOFFCNT` reader - Horizontal offset count"] pub type HoffcntR = crate :: FieldReader < u16 > ; # [doc = "Field `HOFFCNT` writer - Horizontal offset count"] pub type HoffcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; # [doc = "Field `VST` reader - Vertical start line count"] pub type VstR = crate :: FieldReader < u16 > ; # [doc = "Field `VST` writer - Vertical start line count"] pub type VstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bits 0:13 - Horizontal offset count"] # [inline (always)] pub fn hoffcnt (& self) -> HoffcntR { HoffcntR :: new ((self . bits & 0x3fff) as u16) } # [doc = "Bits 16:28 - Vertical start line count"] # [inline (always)] pub fn vst (& self) -> VstR { VstR :: new (((self . bits >> 16) & 0x1fff) as u16) } } impl W { # [doc = "Bits 0:13 - Horizontal offset count"] # [inline (always)] pub fn hoffcnt (& mut self) -> HoffcntW <'_, CwstrtSpec > { HoffcntW :: new (self , 0) } # [doc = "Bits 16:28 - Vertical start line count"] # [inline (always)] pub fn vst (& mut self) -> VstW < CwstrtSpec > { VstW :: new (self , 16) } } # [doc = "crop window start\n\nYou can [`read`](crate::Reg::read) this register and get [`cwstrt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cwstrt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CwstrtSpec ; impl crate :: RegisterSpec for CwstrtSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cwstrt::R`](R) reader structure"] impl crate :: Readable for CwstrtSpec { } # [doc = "`write(|w| ..)` method takes [`cwstrt::W`](W) writer structure"] impl crate :: Writable for CwstrtSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CWSTRT to value 0"] impl crate :: Resettable for CwstrtSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cwstrt.rs:1:1219 [INFO] [stdout] | [INFO] [stdout] 1 | ... # [inline (always)] pub fn vst (& mut self) -> VstW < CwstrtSpec > { VstW :: new (self , 16) } } # [doc = "crop window start\n\nYou c... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CWSTRT` reader"] pub type R = crate :: R < CwstrtSpec > ; # [doc = "Register `CWSTRT` writer"] pub type W = crate :: W < CwstrtSpec > ; # [doc = "Field `HOFFCNT` reader - Horizontal offset count"] pub type HoffcntR = crate :: FieldReader < u16 > ; # [doc = "Field `HOFFCNT` writer - Horizontal offset count"] pub type HoffcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; # [doc = "Field `VST` reader - Vertical start line count"] pub type VstR = crate :: FieldReader < u16 > ; # [doc = "Field `VST` writer - Vertical start line count"] pub type VstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bits 0:13 - Horizontal offset count"] # [inline (always)] pub fn hoffcnt (& self) -> HoffcntR { HoffcntR :: new ((self . bits & 0x3fff) as u16) } # [doc = "Bits 16:28 - Vertical start line count"] # [inline (always)] pub fn vst (& self) -> VstR { VstR :: new (((self . bits >> 16) & 0x1fff) as u16) } } impl W { # [doc = "Bits 0:13 - Horizontal offset count"] # [inline (always)] pub fn hoffcnt (& mut self) -> HoffcntW < CwstrtSpec > { HoffcntW :: new (self , 0) } # [doc = "Bits 16:28 - Vertical start line count"] # [inline (always)] pub fn vst (& mut self) -> VstW <'_, CwstrtSpec > { VstW :: new (self , 16) } } # [doc = "crop window start\n\nYou can [`read`](crate::Reg::read) this register and get [`cwstrt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cwstrt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CwstrtSpec ; impl crate :: RegisterSpec for CwstrtSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cwstrt::R`](R) reader structure"] impl crate :: Readable for CwstrtSpec { } # [doc = "`write(|w| ..)` method takes [`cwstrt::W`](W) writer structure"] impl crate :: Writable for CwstrtSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CWSTRT to value 0"] impl crate :: Resettable for CwstrtSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cwsize.rs:1:1014 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn capcnt (& mut self) -> CapcntW < CwsizeSpec > { CapcntW :: new (self , 0) } # [doc = "Bits 16:29 - Vertical li... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CWSIZE` reader"] pub type R = crate :: R < CwsizeSpec > ; # [doc = "Register `CWSIZE` writer"] pub type W = crate :: W < CwsizeSpec > ; # [doc = "Field `CAPCNT` reader - Capture count"] pub type CapcntR = crate :: FieldReader < u16 > ; # [doc = "Field `CAPCNT` writer - Capture count"] pub type CapcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; # [doc = "Field `VLINE` reader - Vertical line count"] pub type VlineR = crate :: FieldReader < u16 > ; # [doc = "Field `VLINE` writer - Vertical line count"] pub type VlineW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; impl R { # [doc = "Bits 0:13 - Capture count"] # [inline (always)] pub fn capcnt (& self) -> CapcntR { CapcntR :: new ((self . bits & 0x3fff) as u16) } # [doc = "Bits 16:29 - Vertical line count"] # [inline (always)] pub fn vline (& self) -> VlineR { VlineR :: new (((self . bits >> 16) & 0x3fff) as u16) } } impl W { # [doc = "Bits 0:13 - Capture count"] # [inline (always)] pub fn capcnt (& mut self) -> CapcntW <'_, CwsizeSpec > { CapcntW :: new (self , 0) } # [doc = "Bits 16:29 - Vertical line count"] # [inline (always)] pub fn vline (& mut self) -> VlineW < CwsizeSpec > { VlineW :: new (self , 16) } } # [doc = "crop window size\n\nYou can [`read`](crate::Reg::read) this register and get [`cwsize::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cwsize::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CwsizeSpec ; impl crate :: RegisterSpec for CwsizeSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cwsize::R`](R) reader structure"] impl crate :: Readable for CwsizeSpec { } # [doc = "`write(|w| ..)` method takes [`cwsize::W`](W) writer structure"] impl crate :: Writable for CwsizeSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CWSIZE to value 0"] impl crate :: Resettable for CwsizeSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cwsize.rs:1:1161 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn vline (& mut self) -> VlineW < CwsizeSpec > { VlineW :: new (self , 16) } } # [doc = "crop window size\n\nYou... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CWSIZE` reader"] pub type R = crate :: R < CwsizeSpec > ; # [doc = "Register `CWSIZE` writer"] pub type W = crate :: W < CwsizeSpec > ; # [doc = "Field `CAPCNT` reader - Capture count"] pub type CapcntR = crate :: FieldReader < u16 > ; # [doc = "Field `CAPCNT` writer - Capture count"] pub type CapcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; # [doc = "Field `VLINE` reader - Vertical line count"] pub type VlineR = crate :: FieldReader < u16 > ; # [doc = "Field `VLINE` writer - Vertical line count"] pub type VlineW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; impl R { # [doc = "Bits 0:13 - Capture count"] # [inline (always)] pub fn capcnt (& self) -> CapcntR { CapcntR :: new ((self . bits & 0x3fff) as u16) } # [doc = "Bits 16:29 - Vertical line count"] # [inline (always)] pub fn vline (& self) -> VlineR { VlineR :: new (((self . bits >> 16) & 0x3fff) as u16) } } impl W { # [doc = "Bits 0:13 - Capture count"] # [inline (always)] pub fn capcnt (& mut self) -> CapcntW < CwsizeSpec > { CapcntW :: new (self , 0) } # [doc = "Bits 16:29 - Vertical line count"] # [inline (always)] pub fn vline (& mut self) -> VlineW <'_, CwsizeSpec > { VlineW :: new (self , 16) } } # [doc = "crop window size\n\nYou can [`read`](crate::Reg::read) this register and get [`cwsize::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cwsize::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CwsizeSpec ; impl crate :: RegisterSpec for CwsizeSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cwsize::R`](R) reader structure"] impl crate :: Readable for CwsizeSpec { } # [doc = "`write(|w| ..)` method takes [`cwsize::W`](W) writer structure"] impl crate :: Writable for CwsizeSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CWSIZE to value 0"] impl crate :: Resettable for CwsizeSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/btr.rs:1:4462 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn addset (& mut self) -> AddsetW < BtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inl... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BTR%s` reader"] pub type R = crate :: R < BtrSpec > ; # [doc = "Register `BTR%s` writer"] pub type W = crate :: W < BtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `CLKDIV` reader - CLKDIV"] pub type ClkdivR = crate :: FieldReader ; # [doc = "Field `CLKDIV` writer - CLKDIV"] pub type ClkdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATLAT` reader - DATLAT"] pub type DatlatR = crate :: FieldReader ; # [doc = "Field `DATLAT` writer - DATLAT"] pub type DatlatW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 3"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& self) -> ClkdivR { ClkdivR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& self) -> DatlatR { DatlatR :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW <'_, BtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW < BtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW < BtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW < BtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& mut self) -> ClkdivW < BtrSpec > { ClkdivW :: new (self , 20) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& mut self) -> DatlatW < BtrSpec > { DatlatW :: new (self , 24) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW < BtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash chip-select timing register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`btr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BtrSpec ; impl crate :: RegisterSpec for BtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`btr::R`](R) reader structure"] impl crate :: Readable for BtrSpec { } # [doc = "`write(|w| ..)` method takes [`btr::W`](W) writer structure"] impl crate :: Writable for BtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BTR%s to value 0xffff_ffff"] impl crate :: Resettable for BtrSpec { const RESET_VALUE : u32 = 0xffff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/btr.rs:1:4592 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn addhld (& mut self) -> AddhldW < BtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [in... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BTR%s` reader"] pub type R = crate :: R < BtrSpec > ; # [doc = "Register `BTR%s` writer"] pub type W = crate :: W < BtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `CLKDIV` reader - CLKDIV"] pub type ClkdivR = crate :: FieldReader ; # [doc = "Field `CLKDIV` writer - CLKDIV"] pub type ClkdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATLAT` reader - DATLAT"] pub type DatlatR = crate :: FieldReader ; # [doc = "Field `DATLAT` writer - DATLAT"] pub type DatlatW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 3"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& self) -> ClkdivR { ClkdivR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& self) -> DatlatR { DatlatR :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW < BtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW <'_, BtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW < BtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW < BtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& mut self) -> ClkdivW < BtrSpec > { ClkdivW :: new (self , 20) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& mut self) -> DatlatW < BtrSpec > { DatlatW :: new (self , 24) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW < BtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash chip-select timing register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`btr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BtrSpec ; impl crate :: RegisterSpec for BtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`btr::R`](R) reader structure"] impl crate :: Readable for BtrSpec { } # [doc = "`write(|w| ..)` method takes [`btr::W`](W) writer structure"] impl crate :: Writable for BtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BTR%s to value 0xffff_ffff"] impl crate :: Resettable for BtrSpec { const RESET_VALUE : u32 = 0xffff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/btr.rs:1:4723 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn datast (& mut self) -> DatastW < BtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BTR%s` reader"] pub type R = crate :: R < BtrSpec > ; # [doc = "Register `BTR%s` writer"] pub type W = crate :: W < BtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `CLKDIV` reader - CLKDIV"] pub type ClkdivR = crate :: FieldReader ; # [doc = "Field `CLKDIV` writer - CLKDIV"] pub type ClkdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATLAT` reader - DATLAT"] pub type DatlatR = crate :: FieldReader ; # [doc = "Field `DATLAT` writer - DATLAT"] pub type DatlatW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 3"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& self) -> ClkdivR { ClkdivR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& self) -> DatlatR { DatlatR :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW < BtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW < BtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW <'_, BtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW < BtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& mut self) -> ClkdivW < BtrSpec > { ClkdivW :: new (self , 20) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& mut self) -> DatlatW < BtrSpec > { DatlatW :: new (self , 24) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW < BtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash chip-select timing register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`btr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BtrSpec ; impl crate :: RegisterSpec for BtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`btr::R`](R) reader structure"] impl crate :: Readable for BtrSpec { } # [doc = "`write(|w| ..)` method takes [`btr::W`](W) writer structure"] impl crate :: Writable for BtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BTR%s to value 0xffff_ffff"] impl crate :: Resettable for BtrSpec { const RESET_VALUE : u32 = 0xffff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/btr.rs:1:4857 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn busturn (& mut self) -> BusturnW < BtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 20:23 - CLKDIV"] #... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BTR%s` reader"] pub type R = crate :: R < BtrSpec > ; # [doc = "Register `BTR%s` writer"] pub type W = crate :: W < BtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `CLKDIV` reader - CLKDIV"] pub type ClkdivR = crate :: FieldReader ; # [doc = "Field `CLKDIV` writer - CLKDIV"] pub type ClkdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATLAT` reader - DATLAT"] pub type DatlatR = crate :: FieldReader ; # [doc = "Field `DATLAT` writer - DATLAT"] pub type DatlatW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 3"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& self) -> ClkdivR { ClkdivR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& self) -> DatlatR { DatlatR :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW < BtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW < BtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW < BtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW <'_, BtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& mut self) -> ClkdivW < BtrSpec > { ClkdivW :: new (self , 20) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& mut self) -> DatlatW < BtrSpec > { DatlatW :: new (self , 24) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW < BtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash chip-select timing register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`btr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BtrSpec ; impl crate :: RegisterSpec for BtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`btr::R`](R) reader structure"] impl crate :: Readable for BtrSpec { } # [doc = "`write(|w| ..)` method takes [`btr::W`](W) writer structure"] impl crate :: Writable for BtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BTR%s to value 0xffff_ffff"] impl crate :: Resettable for BtrSpec { const RESET_VALUE : u32 = 0xffff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/btr.rs:1:4992 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn clkdiv (& mut self) -> ClkdivW < BtrSpec > { ClkdivW :: new (self , 20) } # [doc = "Bits 24:27 - DATLAT"] # [... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BTR%s` reader"] pub type R = crate :: R < BtrSpec > ; # [doc = "Register `BTR%s` writer"] pub type W = crate :: W < BtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `CLKDIV` reader - CLKDIV"] pub type ClkdivR = crate :: FieldReader ; # [doc = "Field `CLKDIV` writer - CLKDIV"] pub type ClkdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATLAT` reader - DATLAT"] pub type DatlatR = crate :: FieldReader ; # [doc = "Field `DATLAT` writer - DATLAT"] pub type DatlatW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 3"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& self) -> ClkdivR { ClkdivR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& self) -> DatlatR { DatlatR :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW < BtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW < BtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW < BtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW < BtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& mut self) -> ClkdivW <'_, BtrSpec > { ClkdivW :: new (self , 20) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& mut self) -> DatlatW < BtrSpec > { DatlatW :: new (self , 24) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW < BtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash chip-select timing register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`btr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BtrSpec ; impl crate :: RegisterSpec for BtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`btr::R`](R) reader structure"] impl crate :: Readable for BtrSpec { } # [doc = "`write(|w| ..)` method takes [`btr::W`](W) writer structure"] impl crate :: Writable for BtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BTR%s to value 0xffff_ffff"] impl crate :: Resettable for BtrSpec { const RESET_VALUE : u32 = 0xffff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/btr.rs:1:5125 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn datlat (& mut self) -> DatlatW < BtrSpec > { DatlatW :: new (self , 24) } # [doc = "Bits 28:29 - ACCMOD"] # [... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BTR%s` reader"] pub type R = crate :: R < BtrSpec > ; # [doc = "Register `BTR%s` writer"] pub type W = crate :: W < BtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `CLKDIV` reader - CLKDIV"] pub type ClkdivR = crate :: FieldReader ; # [doc = "Field `CLKDIV` writer - CLKDIV"] pub type ClkdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATLAT` reader - DATLAT"] pub type DatlatR = crate :: FieldReader ; # [doc = "Field `DATLAT` writer - DATLAT"] pub type DatlatW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 3"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& self) -> ClkdivR { ClkdivR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& self) -> DatlatR { DatlatR :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW < BtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW < BtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW < BtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW < BtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& mut self) -> ClkdivW < BtrSpec > { ClkdivW :: new (self , 20) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& mut self) -> DatlatW <'_, BtrSpec > { DatlatW :: new (self , 24) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW < BtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash chip-select timing register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`btr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BtrSpec ; impl crate :: RegisterSpec for BtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`btr::R`](R) reader structure"] impl crate :: Readable for BtrSpec { } # [doc = "`write(|w| ..)` method takes [`btr::W`](W) writer structure"] impl crate :: Writable for BtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BTR%s to value 0xffff_ffff"] impl crate :: Resettable for BtrSpec { const RESET_VALUE : u32 = 0xffff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/btr.rs:1:5258 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn accmod (& mut self) -> AccmodW < BtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash chip-sel... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BTR%s` reader"] pub type R = crate :: R < BtrSpec > ; # [doc = "Register `BTR%s` writer"] pub type W = crate :: W < BtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `CLKDIV` reader - CLKDIV"] pub type ClkdivR = crate :: FieldReader ; # [doc = "Field `CLKDIV` writer - CLKDIV"] pub type ClkdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATLAT` reader - DATLAT"] pub type DatlatR = crate :: FieldReader ; # [doc = "Field `DATLAT` writer - DATLAT"] pub type DatlatW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 3"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& self) -> ClkdivR { ClkdivR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& self) -> DatlatR { DatlatR :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW < BtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW < BtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW < BtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW < BtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 20:23 - CLKDIV"] # [inline (always)] pub fn clkdiv (& mut self) -> ClkdivW < BtrSpec > { ClkdivW :: new (self , 20) } # [doc = "Bits 24:27 - DATLAT"] # [inline (always)] pub fn datlat (& mut self) -> DatlatW < BtrSpec > { DatlatW :: new (self , 24) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW <'_, BtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash chip-select timing register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`btr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BtrSpec ; impl crate :: RegisterSpec for BtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`btr::R`](R) reader structure"] impl crate :: Readable for BtrSpec { } # [doc = "`write(|w| ..)` method takes [`btr::W`](W) writer structure"] impl crate :: Writable for BtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BTR%s to value 0xffff_ffff"] impl crate :: Resettable for BtrSpec { const RESET_VALUE : u32 = 0xffff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:25391 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW <'_, BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:25514 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW <'_, BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:25638 [INFO] [stdout] | [INFO] [stdout] 1 | ... # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW <'_, BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:25760 [INFO] [stdout] | [INFO] [stdout] 1 | ... # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (a... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW <'_, BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:25883 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inlin... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW <'_, BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:26012 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inl... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW <'_, BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:26143 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [in... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW <'_, BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:26275 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [i... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW <'_, BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:26408 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inli... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW <'_, BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:26535 [INFO] [stdout] | [INFO] [stdout] 1 | ... # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline ... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW <'_, BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:26660 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inli... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW <'_, BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:26789 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [i... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW <'_, BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:26924 [INFO] [stdout] | [INFO] [stdout] 1 | ...ine (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW <'_, BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:27063 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [in... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW <'_, BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bcr.rs:1:27196 [INFO] [stdout] | [INFO] [stdout] 1 | ...line (always)] pub fn cburstrw (& mut self) -> CburstrwW < BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BCR%s` reader"] pub type R = crate :: R < BcrSpec > ; # [doc = "Register `BCR%s` writer"] pub type W = crate :: W < BcrSpec > ; # [doc = "MBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Mbken > for bool { # [inline (always)] fn from (variant : Mbken) -> Self { variant as u8 != 0 } } # [doc = "Field `MBKEN` reader - MBKEN"] pub type MbkenR = crate :: BitReader < Mbken > ; impl MbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mbken { match self . bits { false => Mbken :: Disabled , true => Mbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Mbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Mbken :: Enabled } } # [doc = "Field `MBKEN` writer - MBKEN"] pub type MbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Mbken > ; impl < 'a , REG > MbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Mbken :: Enabled) } } # [doc = "MUXEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Muxen { # [doc = "0: Address/Data non-multiplexed"] Disabled = 0 , # [doc = "1: Address/Data multiplexed on databus"] Enabled = 1 , } impl From < Muxen > for bool { # [inline (always)] fn from (variant : Muxen) -> Self { variant as u8 != 0 } } # [doc = "Field `MUXEN` reader - MUXEN"] pub type MuxenR = crate :: BitReader < Muxen > ; impl MuxenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Muxen { match self . bits { false => Muxen :: Disabled , true => Muxen :: Enabled , } } # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Muxen :: Disabled } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Muxen :: Enabled } } # [doc = "Field `MUXEN` writer - MUXEN"] pub type MuxenW < 'a , REG > = crate :: BitWriter < 'a , REG , Muxen > ; impl < 'a , REG > MuxenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address/Data non-multiplexed"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Disabled) } # [doc = "Address/Data multiplexed on databus"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Muxen :: Enabled) } } # [doc = "MTYP\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mtyp { # [doc = "0: SRAM memory type"] Sram = 0 , # [doc = "1: PSRAM (CRAM) memory type"] Psram = 1 , # [doc = "2: NOR Flash/OneNAND Flash"] Flash = 2 , } impl From < Mtyp > for u8 { # [inline (always)] fn from (variant : Mtyp) -> Self { variant as _ } } impl crate :: FieldSpec for Mtyp { type Ux = u8 ; } impl crate :: IsEnum for Mtyp { } # [doc = "Field `MTYP` reader - MTYP"] pub type MtypR = crate :: FieldReader < Mtyp > ; impl MtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mtyp > { match self . bits { 0 => Some (Mtyp :: Sram) , 1 => Some (Mtyp :: Psram) , 2 => Some (Mtyp :: Flash) , _ => None , } } # [doc = "SRAM memory type"] # [inline (always)] pub fn is_sram (& self) -> bool { * self == Mtyp :: Sram } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn is_psram (& self) -> bool { * self == Mtyp :: Psram } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn is_flash (& self) -> bool { * self == Mtyp :: Flash } } # [doc = "Field `MTYP` writer - MTYP"] pub type MtypW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mtyp > ; impl < 'a , REG > MtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SRAM memory type"] # [inline (always)] pub fn sram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Sram) } # [doc = "PSRAM (CRAM) memory type"] # [inline (always)] pub fn psram (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Psram) } # [doc = "NOR Flash/OneNAND Flash"] # [inline (always)] pub fn flash (self) -> & 'a mut crate :: W < REG > { self . variant (Mtyp :: Flash) } } # [doc = "MWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mwid { # [doc = "0: Memory data bus width 8 bits"] Bits8 = 0 , # [doc = "1: Memory data bus width 16 bits"] Bits16 = 1 , # [doc = "2: Memory data bus width 32 bits"] Bits32 = 2 , } impl From < Mwid > for u8 { # [inline (always)] fn from (variant : Mwid) -> Self { variant as _ } } impl crate :: FieldSpec for Mwid { type Ux = u8 ; } impl crate :: IsEnum for Mwid { } # [doc = "Field `MWID` reader - MWID"] pub type MwidR = crate :: FieldReader < Mwid > ; impl MwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Mwid > { match self . bits { 0 => Some (Mwid :: Bits8) , 1 => Some (Mwid :: Bits16) , 2 => Some (Mwid :: Bits32) , _ => None , } } # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Mwid :: Bits8 } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Mwid :: Bits16 } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Mwid :: Bits32 } } # [doc = "Field `MWID` writer - MWID"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mwid > ; impl < 'a , REG > MwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Memory data bus width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits8) } # [doc = "Memory data bus width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits16) } # [doc = "Memory data bus width 32 bits"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Mwid :: Bits32) } } # [doc = "FACCEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Faccen { # [doc = "0: Corresponding NOR Flash memory access is disabled"] Disabled = 0 , # [doc = "1: Corresponding NOR Flash memory access is enabled"] Enabled = 1 , } impl From < Faccen > for bool { # [inline (always)] fn from (variant : Faccen) -> Self { variant as u8 != 0 } } # [doc = "Field `FACCEN` reader - FACCEN"] pub type FaccenR = crate :: BitReader < Faccen > ; impl FaccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Faccen { match self . bits { false => Faccen :: Disabled , true => Faccen :: Enabled , } } # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Faccen :: Disabled } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Faccen :: Enabled } } # [doc = "Field `FACCEN` writer - FACCEN"] pub type FaccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Faccen > ; impl < 'a , REG > FaccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding NOR Flash memory access is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Disabled) } # [doc = "Corresponding NOR Flash memory access is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Faccen :: Enabled) } } # [doc = "BURSTEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Bursten { # [doc = "0: Burst mode disabled"] Disabled = 0 , # [doc = "1: Burst mode enabled"] Enabled = 1 , } impl From < Bursten > for bool { # [inline (always)] fn from (variant : Bursten) -> Self { variant as u8 != 0 } } # [doc = "Field `BURSTEN` reader - BURSTEN"] pub type BurstenR = crate :: BitReader < Bursten > ; impl BurstenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Bursten { match self . bits { false => Bursten :: Disabled , true => Bursten :: Enabled , } } # [doc = "Burst mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Bursten :: Disabled } # [doc = "Burst mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Bursten :: Enabled } } # [doc = "Field `BURSTEN` writer - BURSTEN"] pub type BurstenW < 'a , REG > = crate :: BitWriter < 'a , REG , Bursten > ; impl < 'a , REG > BurstenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Burst mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Disabled) } # [doc = "Burst mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Bursten :: Enabled) } } # [doc = "WAITPOL\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitpol { # [doc = "0: NWAIT active low"] ActiveLow = 0 , # [doc = "1: NWAIT active high"] ActiveHigh = 1 , } impl From < Waitpol > for bool { # [inline (always)] fn from (variant : Waitpol) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITPOL` reader - WAITPOL"] pub type WaitpolR = crate :: BitReader < Waitpol > ; impl WaitpolR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitpol { match self . bits { false => Waitpol :: ActiveLow , true => Waitpol :: ActiveHigh , } } # [doc = "NWAIT active low"] # [inline (always)] pub fn is_active_low (& self) -> bool { * self == Waitpol :: ActiveLow } # [doc = "NWAIT active high"] # [inline (always)] pub fn is_active_high (& self) -> bool { * self == Waitpol :: ActiveHigh } } # [doc = "Field `WAITPOL` writer - WAITPOL"] pub type WaitpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitpol > ; impl < 'a , REG > WaitpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT active low"] # [inline (always)] pub fn active_low (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveLow) } # [doc = "NWAIT active high"] # [inline (always)] pub fn active_high (self) -> & 'a mut crate :: W < REG > { self . variant (Waitpol :: ActiveHigh) } } # [doc = "Field `WRAPMOD` reader - WRAPMOD"] pub type WrapmodR = crate :: BitReader ; # [doc = "Field `WRAPMOD` writer - WRAPMOD"] pub type WrapmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "WAITCFG\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waitcfg { # [doc = "0: NWAIT signal is active one data cycle before wait state"] BeforeWaitState = 0 , # [doc = "1: NWAIT signal is active during wait state"] DuringWaitState = 1 , } impl From < Waitcfg > for bool { # [inline (always)] fn from (variant : Waitcfg) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITCFG` reader - WAITCFG"] pub type WaitcfgR = crate :: BitReader < Waitcfg > ; impl WaitcfgR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waitcfg { match self . bits { false => Waitcfg :: BeforeWaitState , true => Waitcfg :: DuringWaitState , } } # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn is_before_wait_state (& self) -> bool { * self == Waitcfg :: BeforeWaitState } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn is_during_wait_state (& self) -> bool { * self == Waitcfg :: DuringWaitState } } # [doc = "Field `WAITCFG` writer - WAITCFG"] pub type WaitcfgW < 'a , REG > = crate :: BitWriter < 'a , REG , Waitcfg > ; impl < 'a , REG > WaitcfgW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NWAIT signal is active one data cycle before wait state"] # [inline (always)] pub fn before_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: BeforeWaitState) } # [doc = "NWAIT signal is active during wait state"] # [inline (always)] pub fn during_wait_state (self) -> & 'a mut crate :: W < REG > { self . variant (Waitcfg :: DuringWaitState) } } # [doc = "WREN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Wren { # [doc = "0: Write operations disabled for the bank by the FMC"] Disabled = 0 , # [doc = "1: Write operations enabled for the bank by the FMC"] Enabled = 1 , } impl From < Wren > for bool { # [inline (always)] fn from (variant : Wren) -> Self { variant as u8 != 0 } } # [doc = "Field `WREN` reader - WREN"] pub type WrenR = crate :: BitReader < Wren > ; impl WrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Wren { match self . bits { false => Wren :: Disabled , true => Wren :: Enabled , } } # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Wren :: Disabled } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Wren :: Enabled } } # [doc = "Field `WREN` writer - WREN"] pub type WrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Wren > ; impl < 'a , REG > WrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations disabled for the bank by the FMC"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Disabled) } # [doc = "Write operations enabled for the bank by the FMC"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Wren :: Enabled) } } # [doc = "WAITEN\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Waiten { # [doc = "0: Values inside the FMC_BWTR are taken into account"] Disabled = 0 , # [doc = "1: NWAIT signal enabled"] Enabled = 1 , } impl From < Waiten > for bool { # [inline (always)] fn from (variant : Waiten) -> Self { variant as u8 != 0 } } # [doc = "Field `WAITEN` reader - WAITEN"] pub type WaitenR = crate :: BitReader < Waiten > ; impl WaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Waiten { match self . bits { false => Waiten :: Disabled , true => Waiten :: Enabled , } } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Waiten :: Disabled } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Waiten :: Enabled } } # [doc = "Field `WAITEN` writer - WAITEN"] pub type WaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Waiten > ; impl < 'a , REG > WaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Disabled) } # [doc = "NWAIT signal enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Waiten :: Enabled) } } # [doc = "EXTMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Extmod { # [doc = "0: Values inside the FMC_BWTR are not taken into account"] Disabled = 0 , # [doc = "1: Values inside the FMC_BWTR are taken into account"] Enabled = 1 , } impl From < Extmod > for bool { # [inline (always)] fn from (variant : Extmod) -> Self { variant as u8 != 0 } } # [doc = "Field `EXTMOD` reader - EXTMOD"] pub type ExtmodR = crate :: BitReader < Extmod > ; impl ExtmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Extmod { match self . bits { false => Extmod :: Disabled , true => Extmod :: Enabled , } } # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Extmod :: Disabled } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Extmod :: Enabled } } # [doc = "Field `EXTMOD` writer - EXTMOD"] pub type ExtmodW < 'a , REG > = crate :: BitWriter < 'a , REG , Extmod > ; impl < 'a , REG > ExtmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Values inside the FMC_BWTR are not taken into account"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Disabled) } # [doc = "Values inside the FMC_BWTR are taken into account"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Extmod :: Enabled) } } # [doc = "ASYNCWAIT\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Asyncwait { # [doc = "0: Wait signal not used in asynchronous mode"] Disabled = 0 , # [doc = "1: Wait signal used even in asynchronous mode"] Enabled = 1 , } impl From < Asyncwait > for bool { # [inline (always)] fn from (variant : Asyncwait) -> Self { variant as u8 != 0 } } # [doc = "Field `ASYNCWAIT` reader - ASYNCWAIT"] pub type AsyncwaitR = crate :: BitReader < Asyncwait > ; impl AsyncwaitR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Asyncwait { match self . bits { false => Asyncwait :: Disabled , true => Asyncwait :: Enabled , } } # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Asyncwait :: Disabled } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Asyncwait :: Enabled } } # [doc = "Field `ASYNCWAIT` writer - ASYNCWAIT"] pub type AsyncwaitW < 'a , REG > = crate :: BitWriter < 'a , REG , Asyncwait > ; impl < 'a , REG > AsyncwaitW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait signal not used in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Disabled) } # [doc = "Wait signal used even in asynchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Asyncwait :: Enabled) } } # [doc = "CPSIZE\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Cpsize { # [doc = "0: No burst split when crossing page boundary"] NoBurstSplit = 0 , # [doc = "1: 128 bytes CRAM page size"] Bytes128 = 1 , # [doc = "2: 256 bytes CRAM page size"] Bytes256 = 2 , # [doc = "3: 512 bytes CRAM page size"] Bytes512 = 3 , # [doc = "4: 1024 bytes CRAM page size"] Bytes1024 = 4 , } impl From < Cpsize > for u8 { # [inline (always)] fn from (variant : Cpsize) -> Self { variant as _ } } impl crate :: FieldSpec for Cpsize { type Ux = u8 ; } impl crate :: IsEnum for Cpsize { } # [doc = "Field `CPSIZE` reader - CPSIZE"] pub type CpsizeR = crate :: FieldReader < Cpsize > ; impl CpsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Cpsize > { match self . bits { 0 => Some (Cpsize :: NoBurstSplit) , 1 => Some (Cpsize :: Bytes128) , 2 => Some (Cpsize :: Bytes256) , 3 => Some (Cpsize :: Bytes512) , 4 => Some (Cpsize :: Bytes1024) , _ => None , } } # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn is_no_burst_split (& self) -> bool { * self == Cpsize :: NoBurstSplit } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn is_bytes128 (& self) -> bool { * self == Cpsize :: Bytes128 } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Cpsize :: Bytes256 } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Cpsize :: Bytes512 } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Cpsize :: Bytes1024 } } # [doc = "Field `CPSIZE` writer - CPSIZE"] pub type CpsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Cpsize > ; impl < 'a , REG > CpsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "No burst split when crossing page boundary"] # [inline (always)] pub fn no_burst_split (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: NoBurstSplit) } # [doc = "128 bytes CRAM page size"] # [inline (always)] pub fn bytes128 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes128) } # [doc = "256 bytes CRAM page size"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes256) } # [doc = "512 bytes CRAM page size"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes512) } # [doc = "1024 bytes CRAM page size"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Cpsize :: Bytes1024) } } # [doc = "CBURSTRW\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cburstrw { # [doc = "0: Write operations are always performed in asynchronous mode"] Disabled = 0 , # [doc = "1: Write operations are performed in synchronous mode"] Enabled = 1 , } impl From < Cburstrw > for bool { # [inline (always)] fn from (variant : Cburstrw) -> Self { variant as u8 != 0 } } # [doc = "Field `CBURSTRW` reader - CBURSTRW"] pub type CburstrwR = crate :: BitReader < Cburstrw > ; impl CburstrwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cburstrw { match self . bits { false => Cburstrw :: Disabled , true => Cburstrw :: Enabled , } } # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Cburstrw :: Disabled } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Cburstrw :: Enabled } } # [doc = "Field `CBURSTRW` writer - CBURSTRW"] pub type CburstrwW < 'a , REG > = crate :: BitWriter < 'a , REG , Cburstrw > ; impl < 'a , REG > CburstrwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Write operations are always performed in asynchronous mode"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Disabled) } # [doc = "Write operations are performed in synchronous mode"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Cburstrw :: Enabled) } } impl R { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& self) -> MbkenR { MbkenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& self) -> MuxenR { MuxenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& self) -> MtypR { MtypR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& self) -> FaccenR { FaccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& self) -> BurstenR { BurstenR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& self) -> WaitpolR { WaitpolR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& self) -> WrapmodR { WrapmodR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& self) -> WaitcfgR { WaitcfgR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& self) -> WrenR { WrenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& self) -> WaitenR { WaitenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& self) -> ExtmodR { ExtmodR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& self) -> AsyncwaitR { AsyncwaitR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& self) -> CpsizeR { CpsizeR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& self) -> CburstrwR { CburstrwR :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - MBKEN"] # [inline (always)] pub fn mbken (& mut self) -> MbkenW < BcrSpec > { MbkenW :: new (self , 0) } # [doc = "Bit 1 - MUXEN"] # [inline (always)] pub fn muxen (& mut self) -> MuxenW < BcrSpec > { MuxenW :: new (self , 1) } # [doc = "Bits 2:3 - MTYP"] # [inline (always)] pub fn mtyp (& mut self) -> MtypW < BcrSpec > { MtypW :: new (self , 2) } # [doc = "Bits 4:5 - MWID"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < BcrSpec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - FACCEN"] # [inline (always)] pub fn faccen (& mut self) -> FaccenW < BcrSpec > { FaccenW :: new (self , 6) } # [doc = "Bit 8 - BURSTEN"] # [inline (always)] pub fn bursten (& mut self) -> BurstenW < BcrSpec > { BurstenW :: new (self , 8) } # [doc = "Bit 9 - WAITPOL"] # [inline (always)] pub fn waitpol (& mut self) -> WaitpolW < BcrSpec > { WaitpolW :: new (self , 9) } # [doc = "Bit 10 - WRAPMOD"] # [inline (always)] pub fn wrapmod (& mut self) -> WrapmodW < BcrSpec > { WrapmodW :: new (self , 10) } # [doc = "Bit 11 - WAITCFG"] # [inline (always)] pub fn waitcfg (& mut self) -> WaitcfgW < BcrSpec > { WaitcfgW :: new (self , 11) } # [doc = "Bit 12 - WREN"] # [inline (always)] pub fn wren (& mut self) -> WrenW < BcrSpec > { WrenW :: new (self , 12) } # [doc = "Bit 13 - WAITEN"] # [inline (always)] pub fn waiten (& mut self) -> WaitenW < BcrSpec > { WaitenW :: new (self , 13) } # [doc = "Bit 14 - EXTMOD"] # [inline (always)] pub fn extmod (& mut self) -> ExtmodW < BcrSpec > { ExtmodW :: new (self , 14) } # [doc = "Bit 15 - ASYNCWAIT"] # [inline (always)] pub fn asyncwait (& mut self) -> AsyncwaitW < BcrSpec > { AsyncwaitW :: new (self , 15) } # [doc = "Bits 16:18 - CPSIZE"] # [inline (always)] pub fn cpsize (& mut self) -> CpsizeW < BcrSpec > { CpsizeW :: new (self , 16) } # [doc = "Bit 19 - CBURSTRW"] # [inline (always)] pub fn cburstrw (& mut self) -> CburstrwW <'_, BcrSpec > { CburstrwW :: new (self , 19) } } # [doc = "SRAM/NOR-Flash chip-select control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcrSpec ; impl crate :: RegisterSpec for BcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bcr::R`](R) reader structure"] impl crate :: Readable for BcrSpec { } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate :: Writable for BcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BCR%s to value 0x30d0"] impl crate :: Resettable for BcrSpec { const RESET_VALUE : u32 = 0x30d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pcr.rs:1:11470 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn pwaiten (& mut self) -> PwaitenW < PcrSpec > { PwaitenW :: new (self , 1) } # [doc = "Bit 2 - PBKEN"] # [inlin... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PCR%s` reader"] pub type R = crate :: R < PcrSpec > ; # [doc = "Register `PCR%s` writer"] pub type W = crate :: W < PcrSpec > ; # [doc = "PWAITEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pwaiten { # [doc = "0: Wait feature disabled"] Disabled = 0 , # [doc = "1: Wait feature enabled"] Enabled = 1 , } impl From < Pwaiten > for bool { # [inline (always)] fn from (variant : Pwaiten) -> Self { variant as u8 != 0 } } # [doc = "Field `PWAITEN` reader - PWAITEN"] pub type PwaitenR = crate :: BitReader < Pwaiten > ; impl PwaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pwaiten { match self . bits { false => Pwaiten :: Disabled , true => Pwaiten :: Enabled , } } # [doc = "Wait feature disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pwaiten :: Disabled } # [doc = "Wait feature enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pwaiten :: Enabled } } # [doc = "Field `PWAITEN` writer - PWAITEN"] pub type PwaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pwaiten > ; impl < 'a , REG > PwaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait feature disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Disabled) } # [doc = "Wait feature enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Enabled) } } # [doc = "PBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Pbken > for bool { # [inline (always)] fn from (variant : Pbken) -> Self { variant as u8 != 0 } } # [doc = "Field `PBKEN` reader - PBKEN"] pub type PbkenR = crate :: BitReader < Pbken > ; impl PbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pbken { match self . bits { false => Pbken :: Disabled , true => Pbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pbken :: Enabled } } # [doc = "Field `PBKEN` writer - PBKEN"] pub type PbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pbken > ; impl < 'a , REG > PbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Enabled) } } # [doc = "PTYP\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ptyp { # [doc = "1: NAND Flash"] Nandflash = 1 , } impl From < Ptyp > for bool { # [inline (always)] fn from (variant : Ptyp) -> Self { variant as u8 != 0 } } # [doc = "Field `PTYP` reader - PTYP"] pub type PtypR = crate :: BitReader < Ptyp > ; impl PtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Ptyp > { match self . bits { true => Some (Ptyp :: Nandflash) , _ => None , } } # [doc = "NAND Flash"] # [inline (always)] pub fn is_nandflash (& self) -> bool { * self == Ptyp :: Nandflash } } # [doc = "Field `PTYP` writer - PTYP"] pub type PtypW < 'a , REG > = crate :: BitWriter < 'a , REG , Ptyp > ; impl < 'a , REG > PtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NAND Flash"] # [inline (always)] pub fn nandflash (self) -> & 'a mut crate :: W < REG > { self . variant (Ptyp :: Nandflash) } } # [doc = "PWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pwid { # [doc = "0: External memory device width 8 bits"] Bits8 = 0 , # [doc = "1: External memory device width 16 bits"] Bits16 = 1 , } impl From < Pwid > for u8 { # [inline (always)] fn from (variant : Pwid) -> Self { variant as _ } } impl crate :: FieldSpec for Pwid { type Ux = u8 ; } impl crate :: IsEnum for Pwid { } # [doc = "Field `PWID` reader - PWID"] pub type PwidR = crate :: FieldReader < Pwid > ; impl PwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Pwid > { match self . bits { 0 => Some (Pwid :: Bits8) , 1 => Some (Pwid :: Bits16) , _ => None , } } # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Pwid :: Bits8 } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Pwid :: Bits16 } } # [doc = "Field `PWID` writer - PWID"] pub type PwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pwid > ; impl < 'a , REG > PwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits8) } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits16) } } # [doc = "ECCEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Eccen { # [doc = "0: ECC logic is disabled and reset"] Disabled = 0 , # [doc = "1: ECC logic is enabled"] Enabled = 1 , } impl From < Eccen > for bool { # [inline (always)] fn from (variant : Eccen) -> Self { variant as u8 != 0 } } # [doc = "Field `ECCEN` reader - ECCEN"] pub type EccenR = crate :: BitReader < Eccen > ; impl EccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Eccen { match self . bits { false => Eccen :: Disabled , true => Eccen :: Enabled , } } # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Eccen :: Disabled } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Eccen :: Enabled } } # [doc = "Field `ECCEN` writer - ECCEN"] pub type EccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Eccen > ; impl < 'a , REG > EccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Disabled) } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Enabled) } } # [doc = "Field `TCLR` reader - TCLR"] pub type TclrR = crate :: FieldReader ; # [doc = "Field `TCLR` writer - TCLR"] pub type TclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `TAR` reader - TAR"] pub type TarR = crate :: FieldReader ; # [doc = "Field `TAR` writer - TAR"] pub type TarW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ECCPS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Eccps { # [doc = "0: ECC page size 256 bytes"] Bytes256 = 0 , # [doc = "1: ECC page size 512 bytes"] Bytes512 = 1 , # [doc = "2: ECC page size 1024 bytes"] Bytes1024 = 2 , # [doc = "3: ECC page size 2048 bytes"] Bytes2048 = 3 , # [doc = "4: ECC page size 4096 bytes"] Bytes4096 = 4 , # [doc = "5: ECC page size 8192 bytes"] Bytes8192 = 5 , } impl From < Eccps > for u8 { # [inline (always)] fn from (variant : Eccps) -> Self { variant as _ } } impl crate :: FieldSpec for Eccps { type Ux = u8 ; } impl crate :: IsEnum for Eccps { } # [doc = "Field `ECCPS` reader - ECCPS"] pub type EccpsR = crate :: FieldReader < Eccps > ; impl EccpsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Eccps > { match self . bits { 0 => Some (Eccps :: Bytes256) , 1 => Some (Eccps :: Bytes512) , 2 => Some (Eccps :: Bytes1024) , 3 => Some (Eccps :: Bytes2048) , 4 => Some (Eccps :: Bytes4096) , 5 => Some (Eccps :: Bytes8192) , _ => None , } } # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Eccps :: Bytes256 } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Eccps :: Bytes512 } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Eccps :: Bytes1024 } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn is_bytes2048 (& self) -> bool { * self == Eccps :: Bytes2048 } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn is_bytes4096 (& self) -> bool { * self == Eccps :: Bytes4096 } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn is_bytes8192 (& self) -> bool { * self == Eccps :: Bytes8192 } } # [doc = "Field `ECCPS` writer - ECCPS"] pub type EccpsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Eccps > ; impl < 'a , REG > EccpsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes256) } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes512) } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes1024) } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn bytes2048 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes2048) } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn bytes4096 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes4096) } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn bytes8192 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes8192) } } impl R { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& self) -> PwaitenR { PwaitenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& self) -> PbkenR { PbkenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& self) -> PtypR { PtypR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& self) -> PwidR { PwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& self) -> EccenR { EccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& self) -> TclrR { TclrR :: new (((self . bits >> 9) & 0x0f) as u8) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& self) -> TarR { TarR :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& self) -> EccpsR { EccpsR :: new (((self . bits >> 17) & 7) as u8) } } impl W { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& mut self) -> PwaitenW <'_, PcrSpec > { PwaitenW :: new (self , 1) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& mut self) -> PbkenW < PcrSpec > { PbkenW :: new (self , 2) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& mut self) -> PtypW < PcrSpec > { PtypW :: new (self , 3) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& mut self) -> PwidW < PcrSpec > { PwidW :: new (self , 4) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& mut self) -> EccenW < PcrSpec > { EccenW :: new (self , 6) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& mut self) -> TclrW < PcrSpec > { TclrW :: new (self , 9) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& mut self) -> TarW < PcrSpec > { TarW :: new (self , 13) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& mut self) -> EccpsW < PcrSpec > { EccpsW :: new (self , 17) } } # [doc = "PC Card/NAND Flash control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PcrSpec ; impl crate :: RegisterSpec for PcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcr::R`](R) reader structure"] impl crate :: Readable for PcrSpec { } # [doc = "`write(|w| ..)` method takes [`pcr::W`](W) writer structure"] impl crate :: Writable for PcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PCR%s to value 0x18"] impl crate :: Resettable for PcrSpec { const RESET_VALUE : u32 = 0x18 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pcr.rs:1:11597 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn pbken (& mut self) -> PbkenW < PcrSpec > { PbkenW :: new (self , 2) } # [doc = "Bit 3 - PTYP"] # [inline (a... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PCR%s` reader"] pub type R = crate :: R < PcrSpec > ; # [doc = "Register `PCR%s` writer"] pub type W = crate :: W < PcrSpec > ; # [doc = "PWAITEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pwaiten { # [doc = "0: Wait feature disabled"] Disabled = 0 , # [doc = "1: Wait feature enabled"] Enabled = 1 , } impl From < Pwaiten > for bool { # [inline (always)] fn from (variant : Pwaiten) -> Self { variant as u8 != 0 } } # [doc = "Field `PWAITEN` reader - PWAITEN"] pub type PwaitenR = crate :: BitReader < Pwaiten > ; impl PwaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pwaiten { match self . bits { false => Pwaiten :: Disabled , true => Pwaiten :: Enabled , } } # [doc = "Wait feature disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pwaiten :: Disabled } # [doc = "Wait feature enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pwaiten :: Enabled } } # [doc = "Field `PWAITEN` writer - PWAITEN"] pub type PwaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pwaiten > ; impl < 'a , REG > PwaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait feature disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Disabled) } # [doc = "Wait feature enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Enabled) } } # [doc = "PBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Pbken > for bool { # [inline (always)] fn from (variant : Pbken) -> Self { variant as u8 != 0 } } # [doc = "Field `PBKEN` reader - PBKEN"] pub type PbkenR = crate :: BitReader < Pbken > ; impl PbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pbken { match self . bits { false => Pbken :: Disabled , true => Pbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pbken :: Enabled } } # [doc = "Field `PBKEN` writer - PBKEN"] pub type PbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pbken > ; impl < 'a , REG > PbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Enabled) } } # [doc = "PTYP\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ptyp { # [doc = "1: NAND Flash"] Nandflash = 1 , } impl From < Ptyp > for bool { # [inline (always)] fn from (variant : Ptyp) -> Self { variant as u8 != 0 } } # [doc = "Field `PTYP` reader - PTYP"] pub type PtypR = crate :: BitReader < Ptyp > ; impl PtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Ptyp > { match self . bits { true => Some (Ptyp :: Nandflash) , _ => None , } } # [doc = "NAND Flash"] # [inline (always)] pub fn is_nandflash (& self) -> bool { * self == Ptyp :: Nandflash } } # [doc = "Field `PTYP` writer - PTYP"] pub type PtypW < 'a , REG > = crate :: BitWriter < 'a , REG , Ptyp > ; impl < 'a , REG > PtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NAND Flash"] # [inline (always)] pub fn nandflash (self) -> & 'a mut crate :: W < REG > { self . variant (Ptyp :: Nandflash) } } # [doc = "PWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pwid { # [doc = "0: External memory device width 8 bits"] Bits8 = 0 , # [doc = "1: External memory device width 16 bits"] Bits16 = 1 , } impl From < Pwid > for u8 { # [inline (always)] fn from (variant : Pwid) -> Self { variant as _ } } impl crate :: FieldSpec for Pwid { type Ux = u8 ; } impl crate :: IsEnum for Pwid { } # [doc = "Field `PWID` reader - PWID"] pub type PwidR = crate :: FieldReader < Pwid > ; impl PwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Pwid > { match self . bits { 0 => Some (Pwid :: Bits8) , 1 => Some (Pwid :: Bits16) , _ => None , } } # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Pwid :: Bits8 } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Pwid :: Bits16 } } # [doc = "Field `PWID` writer - PWID"] pub type PwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pwid > ; impl < 'a , REG > PwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits8) } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits16) } } # [doc = "ECCEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Eccen { # [doc = "0: ECC logic is disabled and reset"] Disabled = 0 , # [doc = "1: ECC logic is enabled"] Enabled = 1 , } impl From < Eccen > for bool { # [inline (always)] fn from (variant : Eccen) -> Self { variant as u8 != 0 } } # [doc = "Field `ECCEN` reader - ECCEN"] pub type EccenR = crate :: BitReader < Eccen > ; impl EccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Eccen { match self . bits { false => Eccen :: Disabled , true => Eccen :: Enabled , } } # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Eccen :: Disabled } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Eccen :: Enabled } } # [doc = "Field `ECCEN` writer - ECCEN"] pub type EccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Eccen > ; impl < 'a , REG > EccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Disabled) } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Enabled) } } # [doc = "Field `TCLR` reader - TCLR"] pub type TclrR = crate :: FieldReader ; # [doc = "Field `TCLR` writer - TCLR"] pub type TclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `TAR` reader - TAR"] pub type TarR = crate :: FieldReader ; # [doc = "Field `TAR` writer - TAR"] pub type TarW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ECCPS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Eccps { # [doc = "0: ECC page size 256 bytes"] Bytes256 = 0 , # [doc = "1: ECC page size 512 bytes"] Bytes512 = 1 , # [doc = "2: ECC page size 1024 bytes"] Bytes1024 = 2 , # [doc = "3: ECC page size 2048 bytes"] Bytes2048 = 3 , # [doc = "4: ECC page size 4096 bytes"] Bytes4096 = 4 , # [doc = "5: ECC page size 8192 bytes"] Bytes8192 = 5 , } impl From < Eccps > for u8 { # [inline (always)] fn from (variant : Eccps) -> Self { variant as _ } } impl crate :: FieldSpec for Eccps { type Ux = u8 ; } impl crate :: IsEnum for Eccps { } # [doc = "Field `ECCPS` reader - ECCPS"] pub type EccpsR = crate :: FieldReader < Eccps > ; impl EccpsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Eccps > { match self . bits { 0 => Some (Eccps :: Bytes256) , 1 => Some (Eccps :: Bytes512) , 2 => Some (Eccps :: Bytes1024) , 3 => Some (Eccps :: Bytes2048) , 4 => Some (Eccps :: Bytes4096) , 5 => Some (Eccps :: Bytes8192) , _ => None , } } # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Eccps :: Bytes256 } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Eccps :: Bytes512 } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Eccps :: Bytes1024 } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn is_bytes2048 (& self) -> bool { * self == Eccps :: Bytes2048 } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn is_bytes4096 (& self) -> bool { * self == Eccps :: Bytes4096 } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn is_bytes8192 (& self) -> bool { * self == Eccps :: Bytes8192 } } # [doc = "Field `ECCPS` writer - ECCPS"] pub type EccpsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Eccps > ; impl < 'a , REG > EccpsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes256) } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes512) } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes1024) } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn bytes2048 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes2048) } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn bytes4096 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes4096) } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn bytes8192 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes8192) } } impl R { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& self) -> PwaitenR { PwaitenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& self) -> PbkenR { PbkenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& self) -> PtypR { PtypR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& self) -> PwidR { PwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& self) -> EccenR { EccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& self) -> TclrR { TclrR :: new (((self . bits >> 9) & 0x0f) as u8) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& self) -> TarR { TarR :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& self) -> EccpsR { EccpsR :: new (((self . bits >> 17) & 7) as u8) } } impl W { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& mut self) -> PwaitenW < PcrSpec > { PwaitenW :: new (self , 1) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& mut self) -> PbkenW <'_, PcrSpec > { PbkenW :: new (self , 2) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& mut self) -> PtypW < PcrSpec > { PtypW :: new (self , 3) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& mut self) -> PwidW < PcrSpec > { PwidW :: new (self , 4) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& mut self) -> EccenW < PcrSpec > { EccenW :: new (self , 6) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& mut self) -> TclrW < PcrSpec > { TclrW :: new (self , 9) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& mut self) -> TarW < PcrSpec > { TarW :: new (self , 13) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& mut self) -> EccpsW < PcrSpec > { EccpsW :: new (self , 17) } } # [doc = "PC Card/NAND Flash control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PcrSpec ; impl crate :: RegisterSpec for PcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcr::R`](R) reader structure"] impl crate :: Readable for PcrSpec { } # [doc = "`write(|w| ..)` method takes [`pcr::W`](W) writer structure"] impl crate :: Writable for PcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PCR%s to value 0x18"] impl crate :: Resettable for PcrSpec { const RESET_VALUE : u32 = 0x18 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pcr.rs:1:11718 [INFO] [stdout] | [INFO] [stdout] 1 | ... # [inline (always)] pub fn ptyp (& mut self) -> PtypW < PcrSpec > { PtypW :: new (self , 3) } # [doc = "Bits 4:5 - PWID"] # [inline (... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PCR%s` reader"] pub type R = crate :: R < PcrSpec > ; # [doc = "Register `PCR%s` writer"] pub type W = crate :: W < PcrSpec > ; # [doc = "PWAITEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pwaiten { # [doc = "0: Wait feature disabled"] Disabled = 0 , # [doc = "1: Wait feature enabled"] Enabled = 1 , } impl From < Pwaiten > for bool { # [inline (always)] fn from (variant : Pwaiten) -> Self { variant as u8 != 0 } } # [doc = "Field `PWAITEN` reader - PWAITEN"] pub type PwaitenR = crate :: BitReader < Pwaiten > ; impl PwaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pwaiten { match self . bits { false => Pwaiten :: Disabled , true => Pwaiten :: Enabled , } } # [doc = "Wait feature disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pwaiten :: Disabled } # [doc = "Wait feature enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pwaiten :: Enabled } } # [doc = "Field `PWAITEN` writer - PWAITEN"] pub type PwaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pwaiten > ; impl < 'a , REG > PwaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait feature disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Disabled) } # [doc = "Wait feature enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Enabled) } } # [doc = "PBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Pbken > for bool { # [inline (always)] fn from (variant : Pbken) -> Self { variant as u8 != 0 } } # [doc = "Field `PBKEN` reader - PBKEN"] pub type PbkenR = crate :: BitReader < Pbken > ; impl PbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pbken { match self . bits { false => Pbken :: Disabled , true => Pbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pbken :: Enabled } } # [doc = "Field `PBKEN` writer - PBKEN"] pub type PbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pbken > ; impl < 'a , REG > PbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Enabled) } } # [doc = "PTYP\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ptyp { # [doc = "1: NAND Flash"] Nandflash = 1 , } impl From < Ptyp > for bool { # [inline (always)] fn from (variant : Ptyp) -> Self { variant as u8 != 0 } } # [doc = "Field `PTYP` reader - PTYP"] pub type PtypR = crate :: BitReader < Ptyp > ; impl PtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Ptyp > { match self . bits { true => Some (Ptyp :: Nandflash) , _ => None , } } # [doc = "NAND Flash"] # [inline (always)] pub fn is_nandflash (& self) -> bool { * self == Ptyp :: Nandflash } } # [doc = "Field `PTYP` writer - PTYP"] pub type PtypW < 'a , REG > = crate :: BitWriter < 'a , REG , Ptyp > ; impl < 'a , REG > PtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NAND Flash"] # [inline (always)] pub fn nandflash (self) -> & 'a mut crate :: W < REG > { self . variant (Ptyp :: Nandflash) } } # [doc = "PWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pwid { # [doc = "0: External memory device width 8 bits"] Bits8 = 0 , # [doc = "1: External memory device width 16 bits"] Bits16 = 1 , } impl From < Pwid > for u8 { # [inline (always)] fn from (variant : Pwid) -> Self { variant as _ } } impl crate :: FieldSpec for Pwid { type Ux = u8 ; } impl crate :: IsEnum for Pwid { } # [doc = "Field `PWID` reader - PWID"] pub type PwidR = crate :: FieldReader < Pwid > ; impl PwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Pwid > { match self . bits { 0 => Some (Pwid :: Bits8) , 1 => Some (Pwid :: Bits16) , _ => None , } } # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Pwid :: Bits8 } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Pwid :: Bits16 } } # [doc = "Field `PWID` writer - PWID"] pub type PwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pwid > ; impl < 'a , REG > PwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits8) } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits16) } } # [doc = "ECCEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Eccen { # [doc = "0: ECC logic is disabled and reset"] Disabled = 0 , # [doc = "1: ECC logic is enabled"] Enabled = 1 , } impl From < Eccen > for bool { # [inline (always)] fn from (variant : Eccen) -> Self { variant as u8 != 0 } } # [doc = "Field `ECCEN` reader - ECCEN"] pub type EccenR = crate :: BitReader < Eccen > ; impl EccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Eccen { match self . bits { false => Eccen :: Disabled , true => Eccen :: Enabled , } } # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Eccen :: Disabled } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Eccen :: Enabled } } # [doc = "Field `ECCEN` writer - ECCEN"] pub type EccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Eccen > ; impl < 'a , REG > EccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Disabled) } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Enabled) } } # [doc = "Field `TCLR` reader - TCLR"] pub type TclrR = crate :: FieldReader ; # [doc = "Field `TCLR` writer - TCLR"] pub type TclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `TAR` reader - TAR"] pub type TarR = crate :: FieldReader ; # [doc = "Field `TAR` writer - TAR"] pub type TarW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ECCPS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Eccps { # [doc = "0: ECC page size 256 bytes"] Bytes256 = 0 , # [doc = "1: ECC page size 512 bytes"] Bytes512 = 1 , # [doc = "2: ECC page size 1024 bytes"] Bytes1024 = 2 , # [doc = "3: ECC page size 2048 bytes"] Bytes2048 = 3 , # [doc = "4: ECC page size 4096 bytes"] Bytes4096 = 4 , # [doc = "5: ECC page size 8192 bytes"] Bytes8192 = 5 , } impl From < Eccps > for u8 { # [inline (always)] fn from (variant : Eccps) -> Self { variant as _ } } impl crate :: FieldSpec for Eccps { type Ux = u8 ; } impl crate :: IsEnum for Eccps { } # [doc = "Field `ECCPS` reader - ECCPS"] pub type EccpsR = crate :: FieldReader < Eccps > ; impl EccpsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Eccps > { match self . bits { 0 => Some (Eccps :: Bytes256) , 1 => Some (Eccps :: Bytes512) , 2 => Some (Eccps :: Bytes1024) , 3 => Some (Eccps :: Bytes2048) , 4 => Some (Eccps :: Bytes4096) , 5 => Some (Eccps :: Bytes8192) , _ => None , } } # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Eccps :: Bytes256 } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Eccps :: Bytes512 } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Eccps :: Bytes1024 } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn is_bytes2048 (& self) -> bool { * self == Eccps :: Bytes2048 } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn is_bytes4096 (& self) -> bool { * self == Eccps :: Bytes4096 } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn is_bytes8192 (& self) -> bool { * self == Eccps :: Bytes8192 } } # [doc = "Field `ECCPS` writer - ECCPS"] pub type EccpsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Eccps > ; impl < 'a , REG > EccpsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes256) } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes512) } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes1024) } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn bytes2048 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes2048) } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn bytes4096 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes4096) } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn bytes8192 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes8192) } } impl R { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& self) -> PwaitenR { PwaitenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& self) -> PbkenR { PbkenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& self) -> PtypR { PtypR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& self) -> PwidR { PwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& self) -> EccenR { EccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& self) -> TclrR { TclrR :: new (((self . bits >> 9) & 0x0f) as u8) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& self) -> TarR { TarR :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& self) -> EccpsR { EccpsR :: new (((self . bits >> 17) & 7) as u8) } } impl W { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& mut self) -> PwaitenW < PcrSpec > { PwaitenW :: new (self , 1) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& mut self) -> PbkenW < PcrSpec > { PbkenW :: new (self , 2) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& mut self) -> PtypW <'_, PcrSpec > { PtypW :: new (self , 3) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& mut self) -> PwidW < PcrSpec > { PwidW :: new (self , 4) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& mut self) -> EccenW < PcrSpec > { EccenW :: new (self , 6) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& mut self) -> TclrW < PcrSpec > { TclrW :: new (self , 9) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& mut self) -> TarW < PcrSpec > { TarW :: new (self , 13) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& mut self) -> EccpsW < PcrSpec > { EccpsW :: new (self , 17) } } # [doc = "PC Card/NAND Flash control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PcrSpec ; impl crate :: RegisterSpec for PcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcr::R`](R) reader structure"] impl crate :: Readable for PcrSpec { } # [doc = "`write(|w| ..)` method takes [`pcr::W`](W) writer structure"] impl crate :: Writable for PcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PCR%s to value 0x18"] impl crate :: Resettable for PcrSpec { const RESET_VALUE : u32 = 0x18 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pcr.rs:1:11840 [INFO] [stdout] | [INFO] [stdout] 1 | ... # [inline (always)] pub fn pwid (& mut self) -> PwidW < PcrSpec > { PwidW :: new (self , 4) } # [doc = "Bit 6 - ECCEN"] # [inline (al... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PCR%s` reader"] pub type R = crate :: R < PcrSpec > ; # [doc = "Register `PCR%s` writer"] pub type W = crate :: W < PcrSpec > ; # [doc = "PWAITEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pwaiten { # [doc = "0: Wait feature disabled"] Disabled = 0 , # [doc = "1: Wait feature enabled"] Enabled = 1 , } impl From < Pwaiten > for bool { # [inline (always)] fn from (variant : Pwaiten) -> Self { variant as u8 != 0 } } # [doc = "Field `PWAITEN` reader - PWAITEN"] pub type PwaitenR = crate :: BitReader < Pwaiten > ; impl PwaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pwaiten { match self . bits { false => Pwaiten :: Disabled , true => Pwaiten :: Enabled , } } # [doc = "Wait feature disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pwaiten :: Disabled } # [doc = "Wait feature enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pwaiten :: Enabled } } # [doc = "Field `PWAITEN` writer - PWAITEN"] pub type PwaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pwaiten > ; impl < 'a , REG > PwaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait feature disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Disabled) } # [doc = "Wait feature enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Enabled) } } # [doc = "PBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Pbken > for bool { # [inline (always)] fn from (variant : Pbken) -> Self { variant as u8 != 0 } } # [doc = "Field `PBKEN` reader - PBKEN"] pub type PbkenR = crate :: BitReader < Pbken > ; impl PbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pbken { match self . bits { false => Pbken :: Disabled , true => Pbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pbken :: Enabled } } # [doc = "Field `PBKEN` writer - PBKEN"] pub type PbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pbken > ; impl < 'a , REG > PbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Enabled) } } # [doc = "PTYP\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ptyp { # [doc = "1: NAND Flash"] Nandflash = 1 , } impl From < Ptyp > for bool { # [inline (always)] fn from (variant : Ptyp) -> Self { variant as u8 != 0 } } # [doc = "Field `PTYP` reader - PTYP"] pub type PtypR = crate :: BitReader < Ptyp > ; impl PtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Ptyp > { match self . bits { true => Some (Ptyp :: Nandflash) , _ => None , } } # [doc = "NAND Flash"] # [inline (always)] pub fn is_nandflash (& self) -> bool { * self == Ptyp :: Nandflash } } # [doc = "Field `PTYP` writer - PTYP"] pub type PtypW < 'a , REG > = crate :: BitWriter < 'a , REG , Ptyp > ; impl < 'a , REG > PtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NAND Flash"] # [inline (always)] pub fn nandflash (self) -> & 'a mut crate :: W < REG > { self . variant (Ptyp :: Nandflash) } } # [doc = "PWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pwid { # [doc = "0: External memory device width 8 bits"] Bits8 = 0 , # [doc = "1: External memory device width 16 bits"] Bits16 = 1 , } impl From < Pwid > for u8 { # [inline (always)] fn from (variant : Pwid) -> Self { variant as _ } } impl crate :: FieldSpec for Pwid { type Ux = u8 ; } impl crate :: IsEnum for Pwid { } # [doc = "Field `PWID` reader - PWID"] pub type PwidR = crate :: FieldReader < Pwid > ; impl PwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Pwid > { match self . bits { 0 => Some (Pwid :: Bits8) , 1 => Some (Pwid :: Bits16) , _ => None , } } # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Pwid :: Bits8 } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Pwid :: Bits16 } } # [doc = "Field `PWID` writer - PWID"] pub type PwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pwid > ; impl < 'a , REG > PwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits8) } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits16) } } # [doc = "ECCEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Eccen { # [doc = "0: ECC logic is disabled and reset"] Disabled = 0 , # [doc = "1: ECC logic is enabled"] Enabled = 1 , } impl From < Eccen > for bool { # [inline (always)] fn from (variant : Eccen) -> Self { variant as u8 != 0 } } # [doc = "Field `ECCEN` reader - ECCEN"] pub type EccenR = crate :: BitReader < Eccen > ; impl EccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Eccen { match self . bits { false => Eccen :: Disabled , true => Eccen :: Enabled , } } # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Eccen :: Disabled } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Eccen :: Enabled } } # [doc = "Field `ECCEN` writer - ECCEN"] pub type EccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Eccen > ; impl < 'a , REG > EccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Disabled) } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Enabled) } } # [doc = "Field `TCLR` reader - TCLR"] pub type TclrR = crate :: FieldReader ; # [doc = "Field `TCLR` writer - TCLR"] pub type TclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `TAR` reader - TAR"] pub type TarR = crate :: FieldReader ; # [doc = "Field `TAR` writer - TAR"] pub type TarW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ECCPS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Eccps { # [doc = "0: ECC page size 256 bytes"] Bytes256 = 0 , # [doc = "1: ECC page size 512 bytes"] Bytes512 = 1 , # [doc = "2: ECC page size 1024 bytes"] Bytes1024 = 2 , # [doc = "3: ECC page size 2048 bytes"] Bytes2048 = 3 , # [doc = "4: ECC page size 4096 bytes"] Bytes4096 = 4 , # [doc = "5: ECC page size 8192 bytes"] Bytes8192 = 5 , } impl From < Eccps > for u8 { # [inline (always)] fn from (variant : Eccps) -> Self { variant as _ } } impl crate :: FieldSpec for Eccps { type Ux = u8 ; } impl crate :: IsEnum for Eccps { } # [doc = "Field `ECCPS` reader - ECCPS"] pub type EccpsR = crate :: FieldReader < Eccps > ; impl EccpsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Eccps > { match self . bits { 0 => Some (Eccps :: Bytes256) , 1 => Some (Eccps :: Bytes512) , 2 => Some (Eccps :: Bytes1024) , 3 => Some (Eccps :: Bytes2048) , 4 => Some (Eccps :: Bytes4096) , 5 => Some (Eccps :: Bytes8192) , _ => None , } } # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Eccps :: Bytes256 } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Eccps :: Bytes512 } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Eccps :: Bytes1024 } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn is_bytes2048 (& self) -> bool { * self == Eccps :: Bytes2048 } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn is_bytes4096 (& self) -> bool { * self == Eccps :: Bytes4096 } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn is_bytes8192 (& self) -> bool { * self == Eccps :: Bytes8192 } } # [doc = "Field `ECCPS` writer - ECCPS"] pub type EccpsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Eccps > ; impl < 'a , REG > EccpsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes256) } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes512) } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes1024) } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn bytes2048 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes2048) } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn bytes4096 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes4096) } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn bytes8192 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes8192) } } impl R { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& self) -> PwaitenR { PwaitenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& self) -> PbkenR { PbkenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& self) -> PtypR { PtypR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& self) -> PwidR { PwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& self) -> EccenR { EccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& self) -> TclrR { TclrR :: new (((self . bits >> 9) & 0x0f) as u8) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& self) -> TarR { TarR :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& self) -> EccpsR { EccpsR :: new (((self . bits >> 17) & 7) as u8) } } impl W { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& mut self) -> PwaitenW < PcrSpec > { PwaitenW :: new (self , 1) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& mut self) -> PbkenW < PcrSpec > { PbkenW :: new (self , 2) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& mut self) -> PtypW < PcrSpec > { PtypW :: new (self , 3) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& mut self) -> PwidW <'_, PcrSpec > { PwidW :: new (self , 4) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& mut self) -> EccenW < PcrSpec > { EccenW :: new (self , 6) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& mut self) -> TclrW < PcrSpec > { TclrW :: new (self , 9) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& mut self) -> TarW < PcrSpec > { TarW :: new (self , 13) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& mut self) -> EccpsW < PcrSpec > { EccpsW :: new (self , 17) } } # [doc = "PC Card/NAND Flash control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PcrSpec ; impl crate :: RegisterSpec for PcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcr::R`](R) reader structure"] impl crate :: Readable for PcrSpec { } # [doc = "`write(|w| ..)` method takes [`pcr::W`](W) writer structure"] impl crate :: Writable for PcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PCR%s to value 0x18"] impl crate :: Resettable for PcrSpec { const RESET_VALUE : u32 = 0x18 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pcr.rs:1:11961 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn eccen (& mut self) -> EccenW < PcrSpec > { EccenW :: new (self , 6) } # [doc = "Bits 9:12 - TCLR"] # [inlin... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PCR%s` reader"] pub type R = crate :: R < PcrSpec > ; # [doc = "Register `PCR%s` writer"] pub type W = crate :: W < PcrSpec > ; # [doc = "PWAITEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pwaiten { # [doc = "0: Wait feature disabled"] Disabled = 0 , # [doc = "1: Wait feature enabled"] Enabled = 1 , } impl From < Pwaiten > for bool { # [inline (always)] fn from (variant : Pwaiten) -> Self { variant as u8 != 0 } } # [doc = "Field `PWAITEN` reader - PWAITEN"] pub type PwaitenR = crate :: BitReader < Pwaiten > ; impl PwaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pwaiten { match self . bits { false => Pwaiten :: Disabled , true => Pwaiten :: Enabled , } } # [doc = "Wait feature disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pwaiten :: Disabled } # [doc = "Wait feature enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pwaiten :: Enabled } } # [doc = "Field `PWAITEN` writer - PWAITEN"] pub type PwaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pwaiten > ; impl < 'a , REG > PwaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait feature disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Disabled) } # [doc = "Wait feature enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Enabled) } } # [doc = "PBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Pbken > for bool { # [inline (always)] fn from (variant : Pbken) -> Self { variant as u8 != 0 } } # [doc = "Field `PBKEN` reader - PBKEN"] pub type PbkenR = crate :: BitReader < Pbken > ; impl PbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pbken { match self . bits { false => Pbken :: Disabled , true => Pbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pbken :: Enabled } } # [doc = "Field `PBKEN` writer - PBKEN"] pub type PbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pbken > ; impl < 'a , REG > PbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Enabled) } } # [doc = "PTYP\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ptyp { # [doc = "1: NAND Flash"] Nandflash = 1 , } impl From < Ptyp > for bool { # [inline (always)] fn from (variant : Ptyp) -> Self { variant as u8 != 0 } } # [doc = "Field `PTYP` reader - PTYP"] pub type PtypR = crate :: BitReader < Ptyp > ; impl PtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Ptyp > { match self . bits { true => Some (Ptyp :: Nandflash) , _ => None , } } # [doc = "NAND Flash"] # [inline (always)] pub fn is_nandflash (& self) -> bool { * self == Ptyp :: Nandflash } } # [doc = "Field `PTYP` writer - PTYP"] pub type PtypW < 'a , REG > = crate :: BitWriter < 'a , REG , Ptyp > ; impl < 'a , REG > PtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NAND Flash"] # [inline (always)] pub fn nandflash (self) -> & 'a mut crate :: W < REG > { self . variant (Ptyp :: Nandflash) } } # [doc = "PWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pwid { # [doc = "0: External memory device width 8 bits"] Bits8 = 0 , # [doc = "1: External memory device width 16 bits"] Bits16 = 1 , } impl From < Pwid > for u8 { # [inline (always)] fn from (variant : Pwid) -> Self { variant as _ } } impl crate :: FieldSpec for Pwid { type Ux = u8 ; } impl crate :: IsEnum for Pwid { } # [doc = "Field `PWID` reader - PWID"] pub type PwidR = crate :: FieldReader < Pwid > ; impl PwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Pwid > { match self . bits { 0 => Some (Pwid :: Bits8) , 1 => Some (Pwid :: Bits16) , _ => None , } } # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Pwid :: Bits8 } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Pwid :: Bits16 } } # [doc = "Field `PWID` writer - PWID"] pub type PwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pwid > ; impl < 'a , REG > PwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits8) } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits16) } } # [doc = "ECCEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Eccen { # [doc = "0: ECC logic is disabled and reset"] Disabled = 0 , # [doc = "1: ECC logic is enabled"] Enabled = 1 , } impl From < Eccen > for bool { # [inline (always)] fn from (variant : Eccen) -> Self { variant as u8 != 0 } } # [doc = "Field `ECCEN` reader - ECCEN"] pub type EccenR = crate :: BitReader < Eccen > ; impl EccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Eccen { match self . bits { false => Eccen :: Disabled , true => Eccen :: Enabled , } } # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Eccen :: Disabled } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Eccen :: Enabled } } # [doc = "Field `ECCEN` writer - ECCEN"] pub type EccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Eccen > ; impl < 'a , REG > EccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Disabled) } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Enabled) } } # [doc = "Field `TCLR` reader - TCLR"] pub type TclrR = crate :: FieldReader ; # [doc = "Field `TCLR` writer - TCLR"] pub type TclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `TAR` reader - TAR"] pub type TarR = crate :: FieldReader ; # [doc = "Field `TAR` writer - TAR"] pub type TarW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ECCPS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Eccps { # [doc = "0: ECC page size 256 bytes"] Bytes256 = 0 , # [doc = "1: ECC page size 512 bytes"] Bytes512 = 1 , # [doc = "2: ECC page size 1024 bytes"] Bytes1024 = 2 , # [doc = "3: ECC page size 2048 bytes"] Bytes2048 = 3 , # [doc = "4: ECC page size 4096 bytes"] Bytes4096 = 4 , # [doc = "5: ECC page size 8192 bytes"] Bytes8192 = 5 , } impl From < Eccps > for u8 { # [inline (always)] fn from (variant : Eccps) -> Self { variant as _ } } impl crate :: FieldSpec for Eccps { type Ux = u8 ; } impl crate :: IsEnum for Eccps { } # [doc = "Field `ECCPS` reader - ECCPS"] pub type EccpsR = crate :: FieldReader < Eccps > ; impl EccpsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Eccps > { match self . bits { 0 => Some (Eccps :: Bytes256) , 1 => Some (Eccps :: Bytes512) , 2 => Some (Eccps :: Bytes1024) , 3 => Some (Eccps :: Bytes2048) , 4 => Some (Eccps :: Bytes4096) , 5 => Some (Eccps :: Bytes8192) , _ => None , } } # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Eccps :: Bytes256 } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Eccps :: Bytes512 } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Eccps :: Bytes1024 } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn is_bytes2048 (& self) -> bool { * self == Eccps :: Bytes2048 } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn is_bytes4096 (& self) -> bool { * self == Eccps :: Bytes4096 } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn is_bytes8192 (& self) -> bool { * self == Eccps :: Bytes8192 } } # [doc = "Field `ECCPS` writer - ECCPS"] pub type EccpsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Eccps > ; impl < 'a , REG > EccpsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes256) } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes512) } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes1024) } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn bytes2048 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes2048) } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn bytes4096 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes4096) } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn bytes8192 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes8192) } } impl R { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& self) -> PwaitenR { PwaitenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& self) -> PbkenR { PbkenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& self) -> PtypR { PtypR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& self) -> PwidR { PwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& self) -> EccenR { EccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& self) -> TclrR { TclrR :: new (((self . bits >> 9) & 0x0f) as u8) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& self) -> TarR { TarR :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& self) -> EccpsR { EccpsR :: new (((self . bits >> 17) & 7) as u8) } } impl W { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& mut self) -> PwaitenW < PcrSpec > { PwaitenW :: new (self , 1) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& mut self) -> PbkenW < PcrSpec > { PbkenW :: new (self , 2) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& mut self) -> PtypW < PcrSpec > { PtypW :: new (self , 3) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& mut self) -> PwidW < PcrSpec > { PwidW :: new (self , 4) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& mut self) -> EccenW <'_, PcrSpec > { EccenW :: new (self , 6) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& mut self) -> TclrW < PcrSpec > { TclrW :: new (self , 9) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& mut self) -> TarW < PcrSpec > { TarW :: new (self , 13) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& mut self) -> EccpsW < PcrSpec > { EccpsW :: new (self , 17) } } # [doc = "PC Card/NAND Flash control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PcrSpec ; impl crate :: RegisterSpec for PcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcr::R`](R) reader structure"] impl crate :: Readable for PcrSpec { } # [doc = "`write(|w| ..)` method takes [`pcr::W`](W) writer structure"] impl crate :: Writable for PcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PCR%s to value 0x18"] impl crate :: Resettable for PcrSpec { const RESET_VALUE : u32 = 0x18 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pcr.rs:1:12086 [INFO] [stdout] | [INFO] [stdout] 1 | ... # [inline (always)] pub fn tclr (& mut self) -> TclrW < PcrSpec > { TclrW :: new (self , 9) } # [doc = "Bits 13:16 - TAR"] # [inline ... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PCR%s` reader"] pub type R = crate :: R < PcrSpec > ; # [doc = "Register `PCR%s` writer"] pub type W = crate :: W < PcrSpec > ; # [doc = "PWAITEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pwaiten { # [doc = "0: Wait feature disabled"] Disabled = 0 , # [doc = "1: Wait feature enabled"] Enabled = 1 , } impl From < Pwaiten > for bool { # [inline (always)] fn from (variant : Pwaiten) -> Self { variant as u8 != 0 } } # [doc = "Field `PWAITEN` reader - PWAITEN"] pub type PwaitenR = crate :: BitReader < Pwaiten > ; impl PwaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pwaiten { match self . bits { false => Pwaiten :: Disabled , true => Pwaiten :: Enabled , } } # [doc = "Wait feature disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pwaiten :: Disabled } # [doc = "Wait feature enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pwaiten :: Enabled } } # [doc = "Field `PWAITEN` writer - PWAITEN"] pub type PwaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pwaiten > ; impl < 'a , REG > PwaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait feature disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Disabled) } # [doc = "Wait feature enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Enabled) } } # [doc = "PBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Pbken > for bool { # [inline (always)] fn from (variant : Pbken) -> Self { variant as u8 != 0 } } # [doc = "Field `PBKEN` reader - PBKEN"] pub type PbkenR = crate :: BitReader < Pbken > ; impl PbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pbken { match self . bits { false => Pbken :: Disabled , true => Pbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pbken :: Enabled } } # [doc = "Field `PBKEN` writer - PBKEN"] pub type PbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pbken > ; impl < 'a , REG > PbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Enabled) } } # [doc = "PTYP\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ptyp { # [doc = "1: NAND Flash"] Nandflash = 1 , } impl From < Ptyp > for bool { # [inline (always)] fn from (variant : Ptyp) -> Self { variant as u8 != 0 } } # [doc = "Field `PTYP` reader - PTYP"] pub type PtypR = crate :: BitReader < Ptyp > ; impl PtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Ptyp > { match self . bits { true => Some (Ptyp :: Nandflash) , _ => None , } } # [doc = "NAND Flash"] # [inline (always)] pub fn is_nandflash (& self) -> bool { * self == Ptyp :: Nandflash } } # [doc = "Field `PTYP` writer - PTYP"] pub type PtypW < 'a , REG > = crate :: BitWriter < 'a , REG , Ptyp > ; impl < 'a , REG > PtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NAND Flash"] # [inline (always)] pub fn nandflash (self) -> & 'a mut crate :: W < REG > { self . variant (Ptyp :: Nandflash) } } # [doc = "PWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pwid { # [doc = "0: External memory device width 8 bits"] Bits8 = 0 , # [doc = "1: External memory device width 16 bits"] Bits16 = 1 , } impl From < Pwid > for u8 { # [inline (always)] fn from (variant : Pwid) -> Self { variant as _ } } impl crate :: FieldSpec for Pwid { type Ux = u8 ; } impl crate :: IsEnum for Pwid { } # [doc = "Field `PWID` reader - PWID"] pub type PwidR = crate :: FieldReader < Pwid > ; impl PwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Pwid > { match self . bits { 0 => Some (Pwid :: Bits8) , 1 => Some (Pwid :: Bits16) , _ => None , } } # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Pwid :: Bits8 } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Pwid :: Bits16 } } # [doc = "Field `PWID` writer - PWID"] pub type PwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pwid > ; impl < 'a , REG > PwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits8) } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits16) } } # [doc = "ECCEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Eccen { # [doc = "0: ECC logic is disabled and reset"] Disabled = 0 , # [doc = "1: ECC logic is enabled"] Enabled = 1 , } impl From < Eccen > for bool { # [inline (always)] fn from (variant : Eccen) -> Self { variant as u8 != 0 } } # [doc = "Field `ECCEN` reader - ECCEN"] pub type EccenR = crate :: BitReader < Eccen > ; impl EccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Eccen { match self . bits { false => Eccen :: Disabled , true => Eccen :: Enabled , } } # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Eccen :: Disabled } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Eccen :: Enabled } } # [doc = "Field `ECCEN` writer - ECCEN"] pub type EccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Eccen > ; impl < 'a , REG > EccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Disabled) } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Enabled) } } # [doc = "Field `TCLR` reader - TCLR"] pub type TclrR = crate :: FieldReader ; # [doc = "Field `TCLR` writer - TCLR"] pub type TclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `TAR` reader - TAR"] pub type TarR = crate :: FieldReader ; # [doc = "Field `TAR` writer - TAR"] pub type TarW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ECCPS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Eccps { # [doc = "0: ECC page size 256 bytes"] Bytes256 = 0 , # [doc = "1: ECC page size 512 bytes"] Bytes512 = 1 , # [doc = "2: ECC page size 1024 bytes"] Bytes1024 = 2 , # [doc = "3: ECC page size 2048 bytes"] Bytes2048 = 3 , # [doc = "4: ECC page size 4096 bytes"] Bytes4096 = 4 , # [doc = "5: ECC page size 8192 bytes"] Bytes8192 = 5 , } impl From < Eccps > for u8 { # [inline (always)] fn from (variant : Eccps) -> Self { variant as _ } } impl crate :: FieldSpec for Eccps { type Ux = u8 ; } impl crate :: IsEnum for Eccps { } # [doc = "Field `ECCPS` reader - ECCPS"] pub type EccpsR = crate :: FieldReader < Eccps > ; impl EccpsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Eccps > { match self . bits { 0 => Some (Eccps :: Bytes256) , 1 => Some (Eccps :: Bytes512) , 2 => Some (Eccps :: Bytes1024) , 3 => Some (Eccps :: Bytes2048) , 4 => Some (Eccps :: Bytes4096) , 5 => Some (Eccps :: Bytes8192) , _ => None , } } # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Eccps :: Bytes256 } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Eccps :: Bytes512 } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Eccps :: Bytes1024 } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn is_bytes2048 (& self) -> bool { * self == Eccps :: Bytes2048 } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn is_bytes4096 (& self) -> bool { * self == Eccps :: Bytes4096 } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn is_bytes8192 (& self) -> bool { * self == Eccps :: Bytes8192 } } # [doc = "Field `ECCPS` writer - ECCPS"] pub type EccpsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Eccps > ; impl < 'a , REG > EccpsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes256) } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes512) } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes1024) } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn bytes2048 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes2048) } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn bytes4096 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes4096) } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn bytes8192 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes8192) } } impl R { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& self) -> PwaitenR { PwaitenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& self) -> PbkenR { PbkenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& self) -> PtypR { PtypR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& self) -> PwidR { PwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& self) -> EccenR { EccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& self) -> TclrR { TclrR :: new (((self . bits >> 9) & 0x0f) as u8) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& self) -> TarR { TarR :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& self) -> EccpsR { EccpsR :: new (((self . bits >> 17) & 7) as u8) } } impl W { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& mut self) -> PwaitenW < PcrSpec > { PwaitenW :: new (self , 1) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& mut self) -> PbkenW < PcrSpec > { PbkenW :: new (self , 2) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& mut self) -> PtypW < PcrSpec > { PtypW :: new (self , 3) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& mut self) -> PwidW < PcrSpec > { PwidW :: new (self , 4) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& mut self) -> EccenW < PcrSpec > { EccenW :: new (self , 6) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& mut self) -> TclrW <'_, PcrSpec > { TclrW :: new (self , 9) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& mut self) -> TarW < PcrSpec > { TarW :: new (self , 13) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& mut self) -> EccpsW < PcrSpec > { EccpsW :: new (self , 17) } } # [doc = "PC Card/NAND Flash control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PcrSpec ; impl crate :: RegisterSpec for PcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcr::R`](R) reader structure"] impl crate :: Readable for PcrSpec { } # [doc = "`write(|w| ..)` method takes [`pcr::W`](W) writer structure"] impl crate :: Writable for PcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PCR%s to value 0x18"] impl crate :: Resettable for PcrSpec { const RESET_VALUE : u32 = 0x18 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pcr.rs:1:12208 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn tar (& mut self) -> TarW < PcrSpec > { TarW :: new (self , 13) } # [doc = "Bits 17:19 - ECCPS"] # [inlin... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PCR%s` reader"] pub type R = crate :: R < PcrSpec > ; # [doc = "Register `PCR%s` writer"] pub type W = crate :: W < PcrSpec > ; # [doc = "PWAITEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pwaiten { # [doc = "0: Wait feature disabled"] Disabled = 0 , # [doc = "1: Wait feature enabled"] Enabled = 1 , } impl From < Pwaiten > for bool { # [inline (always)] fn from (variant : Pwaiten) -> Self { variant as u8 != 0 } } # [doc = "Field `PWAITEN` reader - PWAITEN"] pub type PwaitenR = crate :: BitReader < Pwaiten > ; impl PwaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pwaiten { match self . bits { false => Pwaiten :: Disabled , true => Pwaiten :: Enabled , } } # [doc = "Wait feature disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pwaiten :: Disabled } # [doc = "Wait feature enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pwaiten :: Enabled } } # [doc = "Field `PWAITEN` writer - PWAITEN"] pub type PwaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pwaiten > ; impl < 'a , REG > PwaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait feature disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Disabled) } # [doc = "Wait feature enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Enabled) } } # [doc = "PBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Pbken > for bool { # [inline (always)] fn from (variant : Pbken) -> Self { variant as u8 != 0 } } # [doc = "Field `PBKEN` reader - PBKEN"] pub type PbkenR = crate :: BitReader < Pbken > ; impl PbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pbken { match self . bits { false => Pbken :: Disabled , true => Pbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pbken :: Enabled } } # [doc = "Field `PBKEN` writer - PBKEN"] pub type PbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pbken > ; impl < 'a , REG > PbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Enabled) } } # [doc = "PTYP\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ptyp { # [doc = "1: NAND Flash"] Nandflash = 1 , } impl From < Ptyp > for bool { # [inline (always)] fn from (variant : Ptyp) -> Self { variant as u8 != 0 } } # [doc = "Field `PTYP` reader - PTYP"] pub type PtypR = crate :: BitReader < Ptyp > ; impl PtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Ptyp > { match self . bits { true => Some (Ptyp :: Nandflash) , _ => None , } } # [doc = "NAND Flash"] # [inline (always)] pub fn is_nandflash (& self) -> bool { * self == Ptyp :: Nandflash } } # [doc = "Field `PTYP` writer - PTYP"] pub type PtypW < 'a , REG > = crate :: BitWriter < 'a , REG , Ptyp > ; impl < 'a , REG > PtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NAND Flash"] # [inline (always)] pub fn nandflash (self) -> & 'a mut crate :: W < REG > { self . variant (Ptyp :: Nandflash) } } # [doc = "PWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pwid { # [doc = "0: External memory device width 8 bits"] Bits8 = 0 , # [doc = "1: External memory device width 16 bits"] Bits16 = 1 , } impl From < Pwid > for u8 { # [inline (always)] fn from (variant : Pwid) -> Self { variant as _ } } impl crate :: FieldSpec for Pwid { type Ux = u8 ; } impl crate :: IsEnum for Pwid { } # [doc = "Field `PWID` reader - PWID"] pub type PwidR = crate :: FieldReader < Pwid > ; impl PwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Pwid > { match self . bits { 0 => Some (Pwid :: Bits8) , 1 => Some (Pwid :: Bits16) , _ => None , } } # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Pwid :: Bits8 } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Pwid :: Bits16 } } # [doc = "Field `PWID` writer - PWID"] pub type PwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pwid > ; impl < 'a , REG > PwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits8) } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits16) } } # [doc = "ECCEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Eccen { # [doc = "0: ECC logic is disabled and reset"] Disabled = 0 , # [doc = "1: ECC logic is enabled"] Enabled = 1 , } impl From < Eccen > for bool { # [inline (always)] fn from (variant : Eccen) -> Self { variant as u8 != 0 } } # [doc = "Field `ECCEN` reader - ECCEN"] pub type EccenR = crate :: BitReader < Eccen > ; impl EccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Eccen { match self . bits { false => Eccen :: Disabled , true => Eccen :: Enabled , } } # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Eccen :: Disabled } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Eccen :: Enabled } } # [doc = "Field `ECCEN` writer - ECCEN"] pub type EccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Eccen > ; impl < 'a , REG > EccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Disabled) } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Enabled) } } # [doc = "Field `TCLR` reader - TCLR"] pub type TclrR = crate :: FieldReader ; # [doc = "Field `TCLR` writer - TCLR"] pub type TclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `TAR` reader - TAR"] pub type TarR = crate :: FieldReader ; # [doc = "Field `TAR` writer - TAR"] pub type TarW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ECCPS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Eccps { # [doc = "0: ECC page size 256 bytes"] Bytes256 = 0 , # [doc = "1: ECC page size 512 bytes"] Bytes512 = 1 , # [doc = "2: ECC page size 1024 bytes"] Bytes1024 = 2 , # [doc = "3: ECC page size 2048 bytes"] Bytes2048 = 3 , # [doc = "4: ECC page size 4096 bytes"] Bytes4096 = 4 , # [doc = "5: ECC page size 8192 bytes"] Bytes8192 = 5 , } impl From < Eccps > for u8 { # [inline (always)] fn from (variant : Eccps) -> Self { variant as _ } } impl crate :: FieldSpec for Eccps { type Ux = u8 ; } impl crate :: IsEnum for Eccps { } # [doc = "Field `ECCPS` reader - ECCPS"] pub type EccpsR = crate :: FieldReader < Eccps > ; impl EccpsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Eccps > { match self . bits { 0 => Some (Eccps :: Bytes256) , 1 => Some (Eccps :: Bytes512) , 2 => Some (Eccps :: Bytes1024) , 3 => Some (Eccps :: Bytes2048) , 4 => Some (Eccps :: Bytes4096) , 5 => Some (Eccps :: Bytes8192) , _ => None , } } # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Eccps :: Bytes256 } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Eccps :: Bytes512 } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Eccps :: Bytes1024 } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn is_bytes2048 (& self) -> bool { * self == Eccps :: Bytes2048 } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn is_bytes4096 (& self) -> bool { * self == Eccps :: Bytes4096 } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn is_bytes8192 (& self) -> bool { * self == Eccps :: Bytes8192 } } # [doc = "Field `ECCPS` writer - ECCPS"] pub type EccpsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Eccps > ; impl < 'a , REG > EccpsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes256) } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes512) } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes1024) } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn bytes2048 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes2048) } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn bytes4096 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes4096) } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn bytes8192 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes8192) } } impl R { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& self) -> PwaitenR { PwaitenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& self) -> PbkenR { PbkenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& self) -> PtypR { PtypR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& self) -> PwidR { PwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& self) -> EccenR { EccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& self) -> TclrR { TclrR :: new (((self . bits >> 9) & 0x0f) as u8) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& self) -> TarR { TarR :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& self) -> EccpsR { EccpsR :: new (((self . bits >> 17) & 7) as u8) } } impl W { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& mut self) -> PwaitenW < PcrSpec > { PwaitenW :: new (self , 1) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& mut self) -> PbkenW < PcrSpec > { PbkenW :: new (self , 2) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& mut self) -> PtypW < PcrSpec > { PtypW :: new (self , 3) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& mut self) -> PwidW < PcrSpec > { PwidW :: new (self , 4) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& mut self) -> EccenW < PcrSpec > { EccenW :: new (self , 6) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& mut self) -> TclrW < PcrSpec > { TclrW :: new (self , 9) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& mut self) -> TarW <'_, PcrSpec > { TarW :: new (self , 13) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& mut self) -> EccpsW < PcrSpec > { EccpsW :: new (self , 17) } } # [doc = "PC Card/NAND Flash control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PcrSpec ; impl crate :: RegisterSpec for PcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcr::R`](R) reader structure"] impl crate :: Readable for PcrSpec { } # [doc = "`write(|w| ..)` method takes [`pcr::W`](W) writer structure"] impl crate :: Writable for PcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PCR%s to value 0x18"] impl crate :: Resettable for PcrSpec { const RESET_VALUE : u32 = 0x18 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pcr.rs:1:12333 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn eccps (& mut self) -> EccpsW < PcrSpec > { EccpsW :: new (self , 17) } } # [doc = "PC Card/NAND Flash contr... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PCR%s` reader"] pub type R = crate :: R < PcrSpec > ; # [doc = "Register `PCR%s` writer"] pub type W = crate :: W < PcrSpec > ; # [doc = "PWAITEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pwaiten { # [doc = "0: Wait feature disabled"] Disabled = 0 , # [doc = "1: Wait feature enabled"] Enabled = 1 , } impl From < Pwaiten > for bool { # [inline (always)] fn from (variant : Pwaiten) -> Self { variant as u8 != 0 } } # [doc = "Field `PWAITEN` reader - PWAITEN"] pub type PwaitenR = crate :: BitReader < Pwaiten > ; impl PwaitenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pwaiten { match self . bits { false => Pwaiten :: Disabled , true => Pwaiten :: Enabled , } } # [doc = "Wait feature disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pwaiten :: Disabled } # [doc = "Wait feature enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pwaiten :: Enabled } } # [doc = "Field `PWAITEN` writer - PWAITEN"] pub type PwaitenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pwaiten > ; impl < 'a , REG > PwaitenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Wait feature disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Disabled) } # [doc = "Wait feature enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pwaiten :: Enabled) } } # [doc = "PBKEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pbken { # [doc = "0: Corresponding memory bank is disabled"] Disabled = 0 , # [doc = "1: Corresponding memory bank is enabled"] Enabled = 1 , } impl From < Pbken > for bool { # [inline (always)] fn from (variant : Pbken) -> Self { variant as u8 != 0 } } # [doc = "Field `PBKEN` reader - PBKEN"] pub type PbkenR = crate :: BitReader < Pbken > ; impl PbkenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pbken { match self . bits { false => Pbken :: Disabled , true => Pbken :: Enabled , } } # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Pbken :: Disabled } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Pbken :: Enabled } } # [doc = "Field `PBKEN` writer - PBKEN"] pub type PbkenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pbken > ; impl < 'a , REG > PbkenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Corresponding memory bank is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Disabled) } # [doc = "Corresponding memory bank is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pbken :: Enabled) } } # [doc = "PTYP\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ptyp { # [doc = "1: NAND Flash"] Nandflash = 1 , } impl From < Ptyp > for bool { # [inline (always)] fn from (variant : Ptyp) -> Self { variant as u8 != 0 } } # [doc = "Field `PTYP` reader - PTYP"] pub type PtypR = crate :: BitReader < Ptyp > ; impl PtypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Ptyp > { match self . bits { true => Some (Ptyp :: Nandflash) , _ => None , } } # [doc = "NAND Flash"] # [inline (always)] pub fn is_nandflash (& self) -> bool { * self == Ptyp :: Nandflash } } # [doc = "Field `PTYP` writer - PTYP"] pub type PtypW < 'a , REG > = crate :: BitWriter < 'a , REG , Ptyp > ; impl < 'a , REG > PtypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NAND Flash"] # [inline (always)] pub fn nandflash (self) -> & 'a mut crate :: W < REG > { self . variant (Ptyp :: Nandflash) } } # [doc = "PWID\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pwid { # [doc = "0: External memory device width 8 bits"] Bits8 = 0 , # [doc = "1: External memory device width 16 bits"] Bits16 = 1 , } impl From < Pwid > for u8 { # [inline (always)] fn from (variant : Pwid) -> Self { variant as _ } } impl crate :: FieldSpec for Pwid { type Ux = u8 ; } impl crate :: IsEnum for Pwid { } # [doc = "Field `PWID` reader - PWID"] pub type PwidR = crate :: FieldReader < Pwid > ; impl PwidR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Pwid > { match self . bits { 0 => Some (Pwid :: Bits8) , 1 => Some (Pwid :: Bits16) , _ => None , } } # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Pwid :: Bits8 } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Pwid :: Bits16 } } # [doc = "Field `PWID` writer - PWID"] pub type PwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pwid > ; impl < 'a , REG > PwidW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "External memory device width 8 bits"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits8) } # [doc = "External memory device width 16 bits"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pwid :: Bits16) } } # [doc = "ECCEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Eccen { # [doc = "0: ECC logic is disabled and reset"] Disabled = 0 , # [doc = "1: ECC logic is enabled"] Enabled = 1 , } impl From < Eccen > for bool { # [inline (always)] fn from (variant : Eccen) -> Self { variant as u8 != 0 } } # [doc = "Field `ECCEN` reader - ECCEN"] pub type EccenR = crate :: BitReader < Eccen > ; impl EccenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Eccen { match self . bits { false => Eccen :: Disabled , true => Eccen :: Enabled , } } # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Eccen :: Disabled } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Eccen :: Enabled } } # [doc = "Field `ECCEN` writer - ECCEN"] pub type EccenW < 'a , REG > = crate :: BitWriter < 'a , REG , Eccen > ; impl < 'a , REG > EccenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ECC logic is disabled and reset"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Disabled) } # [doc = "ECC logic is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Eccen :: Enabled) } } # [doc = "Field `TCLR` reader - TCLR"] pub type TclrR = crate :: FieldReader ; # [doc = "Field `TCLR` writer - TCLR"] pub type TclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `TAR` reader - TAR"] pub type TarR = crate :: FieldReader ; # [doc = "Field `TAR` writer - TAR"] pub type TarW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ECCPS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Eccps { # [doc = "0: ECC page size 256 bytes"] Bytes256 = 0 , # [doc = "1: ECC page size 512 bytes"] Bytes512 = 1 , # [doc = "2: ECC page size 1024 bytes"] Bytes1024 = 2 , # [doc = "3: ECC page size 2048 bytes"] Bytes2048 = 3 , # [doc = "4: ECC page size 4096 bytes"] Bytes4096 = 4 , # [doc = "5: ECC page size 8192 bytes"] Bytes8192 = 5 , } impl From < Eccps > for u8 { # [inline (always)] fn from (variant : Eccps) -> Self { variant as _ } } impl crate :: FieldSpec for Eccps { type Ux = u8 ; } impl crate :: IsEnum for Eccps { } # [doc = "Field `ECCPS` reader - ECCPS"] pub type EccpsR = crate :: FieldReader < Eccps > ; impl EccpsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Eccps > { match self . bits { 0 => Some (Eccps :: Bytes256) , 1 => Some (Eccps :: Bytes512) , 2 => Some (Eccps :: Bytes1024) , 3 => Some (Eccps :: Bytes2048) , 4 => Some (Eccps :: Bytes4096) , 5 => Some (Eccps :: Bytes8192) , _ => None , } } # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn is_bytes256 (& self) -> bool { * self == Eccps :: Bytes256 } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn is_bytes512 (& self) -> bool { * self == Eccps :: Bytes512 } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn is_bytes1024 (& self) -> bool { * self == Eccps :: Bytes1024 } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn is_bytes2048 (& self) -> bool { * self == Eccps :: Bytes2048 } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn is_bytes4096 (& self) -> bool { * self == Eccps :: Bytes4096 } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn is_bytes8192 (& self) -> bool { * self == Eccps :: Bytes8192 } } # [doc = "Field `ECCPS` writer - ECCPS"] pub type EccpsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Eccps > ; impl < 'a , REG > EccpsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "ECC page size 256 bytes"] # [inline (always)] pub fn bytes256 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes256) } # [doc = "ECC page size 512 bytes"] # [inline (always)] pub fn bytes512 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes512) } # [doc = "ECC page size 1024 bytes"] # [inline (always)] pub fn bytes1024 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes1024) } # [doc = "ECC page size 2048 bytes"] # [inline (always)] pub fn bytes2048 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes2048) } # [doc = "ECC page size 4096 bytes"] # [inline (always)] pub fn bytes4096 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes4096) } # [doc = "ECC page size 8192 bytes"] # [inline (always)] pub fn bytes8192 (self) -> & 'a mut crate :: W < REG > { self . variant (Eccps :: Bytes8192) } } impl R { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& self) -> PwaitenR { PwaitenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& self) -> PbkenR { PbkenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& self) -> PtypR { PtypR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& self) -> PwidR { PwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& self) -> EccenR { EccenR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& self) -> TclrR { TclrR :: new (((self . bits >> 9) & 0x0f) as u8) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& self) -> TarR { TarR :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& self) -> EccpsR { EccpsR :: new (((self . bits >> 17) & 7) as u8) } } impl W { # [doc = "Bit 1 - PWAITEN"] # [inline (always)] pub fn pwaiten (& mut self) -> PwaitenW < PcrSpec > { PwaitenW :: new (self , 1) } # [doc = "Bit 2 - PBKEN"] # [inline (always)] pub fn pbken (& mut self) -> PbkenW < PcrSpec > { PbkenW :: new (self , 2) } # [doc = "Bit 3 - PTYP"] # [inline (always)] pub fn ptyp (& mut self) -> PtypW < PcrSpec > { PtypW :: new (self , 3) } # [doc = "Bits 4:5 - PWID"] # [inline (always)] pub fn pwid (& mut self) -> PwidW < PcrSpec > { PwidW :: new (self , 4) } # [doc = "Bit 6 - ECCEN"] # [inline (always)] pub fn eccen (& mut self) -> EccenW < PcrSpec > { EccenW :: new (self , 6) } # [doc = "Bits 9:12 - TCLR"] # [inline (always)] pub fn tclr (& mut self) -> TclrW < PcrSpec > { TclrW :: new (self , 9) } # [doc = "Bits 13:16 - TAR"] # [inline (always)] pub fn tar (& mut self) -> TarW < PcrSpec > { TarW :: new (self , 13) } # [doc = "Bits 17:19 - ECCPS"] # [inline (always)] pub fn eccps (& mut self) -> EccpsW <'_, PcrSpec > { EccpsW :: new (self , 17) } } # [doc = "PC Card/NAND Flash control register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PcrSpec ; impl crate :: RegisterSpec for PcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcr::R`](R) reader structure"] impl crate :: Readable for PcrSpec { } # [doc = "`write(|w| ..)` method takes [`pcr::W`](W) writer structure"] impl crate :: Writable for PcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PCR%s to value 0x18"] impl crate :: Resettable for PcrSpec { const RESET_VALUE : u32 = 0x18 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sr.rs:1:10605 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn irs (& mut self) -> IrsW < SrSpec > { IrsW :: new (self , 0) } # [doc = "Bit 1 - ILS"] # [inline (always... [INFO] [stdout] | ^^^^^^^^^^ --------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SR%s` reader"] pub type R = crate :: R < SrSpec > ; # [doc = "Register `SR%s` writer"] pub type W = crate :: W < SrSpec > ; # [doc = "IRS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Irs { # [doc = "0: Interrupt rising edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt rising edge occurred"] Occurred = 1 , } impl From < Irs > for bool { # [inline (always)] fn from (variant : Irs) -> Self { variant as u8 != 0 } } # [doc = "Field `IRS` reader - IRS"] pub type IrsR = crate :: BitReader < Irs > ; impl IrsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Irs { match self . bits { false => Irs :: DidNotOccur , true => Irs :: Occurred , } } # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Irs :: DidNotOccur } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Irs :: Occurred } } # [doc = "Field `IRS` writer - IRS"] pub type IrsW < 'a , REG > = crate :: BitWriter < 'a , REG , Irs > ; impl < 'a , REG > IrsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: DidNotOccur) } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: Occurred) } } # [doc = "ILS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ils { # [doc = "0: Interrupt high-level did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt high-level occurred"] Occurred = 1 , } impl From < Ils > for bool { # [inline (always)] fn from (variant : Ils) -> Self { variant as u8 != 0 } } # [doc = "Field `ILS` reader - ILS"] pub type IlsR = crate :: BitReader < Ils > ; impl IlsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ils { match self . bits { false => Ils :: DidNotOccur , true => Ils :: Occurred , } } # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ils :: DidNotOccur } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ils :: Occurred } } # [doc = "Field `ILS` writer - ILS"] pub type IlsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ils > ; impl < 'a , REG > IlsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: DidNotOccur) } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: Occurred) } } # [doc = "IFS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifs { # [doc = "0: Interrupt falling edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt falling edge occurred"] Occurred = 1 , } impl From < Ifs > for bool { # [inline (always)] fn from (variant : Ifs) -> Self { variant as u8 != 0 } } # [doc = "Field `IFS` reader - IFS"] pub type IfsR = crate :: BitReader < Ifs > ; impl IfsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifs { match self . bits { false => Ifs :: DidNotOccur , true => Ifs :: Occurred , } } # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ifs :: DidNotOccur } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ifs :: Occurred } } # [doc = "Field `IFS` writer - IFS"] pub type IfsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifs > ; impl < 'a , REG > IfsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: DidNotOccur) } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: Occurred) } } # [doc = "IREN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Iren { # [doc = "0: Interrupt rising edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt rising edge detection request enabled"] Enabled = 1 , } impl From < Iren > for bool { # [inline (always)] fn from (variant : Iren) -> Self { variant as u8 != 0 } } # [doc = "Field `IREN` reader - IREN"] pub type IrenR = crate :: BitReader < Iren > ; impl IrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Iren { match self . bits { false => Iren :: Disabled , true => Iren :: Enabled , } } # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Iren :: Disabled } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Iren :: Enabled } } # [doc = "Field `IREN` writer - IREN"] pub type IrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Iren > ; impl < 'a , REG > IrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Disabled) } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Enabled) } } # [doc = "ILEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ilen { # [doc = "0: Interrupt high-level detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt high-level detection request enabled"] Enabled = 1 , } impl From < Ilen > for bool { # [inline (always)] fn from (variant : Ilen) -> Self { variant as u8 != 0 } } # [doc = "Field `ILEN` reader - ILEN"] pub type IlenR = crate :: BitReader < Ilen > ; impl IlenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ilen { match self . bits { false => Ilen :: Disabled , true => Ilen :: Enabled , } } # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ilen :: Disabled } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ilen :: Enabled } } # [doc = "Field `ILEN` writer - ILEN"] pub type IlenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ilen > ; impl < 'a , REG > IlenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Disabled) } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Enabled) } } # [doc = "IFEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifen { # [doc = "0: Interrupt falling edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt falling edge detection request enabled"] Enabled = 1 , } impl From < Ifen > for bool { # [inline (always)] fn from (variant : Ifen) -> Self { variant as u8 != 0 } } # [doc = "Field `IFEN` reader - IFEN"] pub type IfenR = crate :: BitReader < Ifen > ; impl IfenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifen { match self . bits { false => Ifen :: Disabled , true => Ifen :: Enabled , } } # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ifen :: Disabled } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ifen :: Enabled } } # [doc = "Field `IFEN` writer - IFEN"] pub type IfenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifen > ; impl < 'a , REG > IfenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Disabled) } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Enabled) } } # [doc = "FEMPT\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Fempt { # [doc = "0: FIFO not empty"] NotEmpty = 0 , # [doc = "1: FIFO empty"] Empty = 1 , } impl From < Fempt > for bool { # [inline (always)] fn from (variant : Fempt) -> Self { variant as u8 != 0 } } # [doc = "Field `FEMPT` reader - FEMPT"] pub type FemptR = crate :: BitReader < Fempt > ; impl FemptR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Fempt { match self . bits { false => Fempt :: NotEmpty , true => Fempt :: Empty , } } # [doc = "FIFO not empty"] # [inline (always)] pub fn is_not_empty (& self) -> bool { * self == Fempt :: NotEmpty } # [doc = "FIFO empty"] # [inline (always)] pub fn is_empty (& self) -> bool { * self == Fempt :: Empty } } impl R { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& self) -> IrsR { IrsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& self) -> IlsR { IlsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& self) -> IfsR { IfsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& self) -> IrenR { IrenR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& self) -> IlenR { IlenR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& self) -> IfenR { IfenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - FEMPT"] # [inline (always)] pub fn fempt (& self) -> FemptR { FemptR :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& mut self) -> IrsW <'_, SrSpec > { IrsW :: new (self , 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& mut self) -> IlsW < SrSpec > { IlsW :: new (self , 1) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& mut self) -> IfsW < SrSpec > { IfsW :: new (self , 2) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& mut self) -> IrenW < SrSpec > { IrenW :: new (self , 3) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& mut self) -> IlenW < SrSpec > { IlenW :: new (self , 4) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& mut self) -> IfenW < SrSpec > { IfenW :: new (self , 5) } } # [doc = "FIFO status and interrupt register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SrSpec ; impl crate :: RegisterSpec for SrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sr::R`](R) reader structure"] impl crate :: Readable for SrSpec { } # [doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] impl crate :: Writable for SrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SR%s to value 0x40"] impl crate :: Resettable for SrSpec { const RESET_VALUE : u32 = 0x40 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sr.rs:1:10719 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn ils (& mut self) -> IlsW < SrSpec > { IlsW :: new (self , 1) } # [doc = "Bit 2 - IFS"] # [inline (always... [INFO] [stdout] | ^^^^^^^^^^ --------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SR%s` reader"] pub type R = crate :: R < SrSpec > ; # [doc = "Register `SR%s` writer"] pub type W = crate :: W < SrSpec > ; # [doc = "IRS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Irs { # [doc = "0: Interrupt rising edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt rising edge occurred"] Occurred = 1 , } impl From < Irs > for bool { # [inline (always)] fn from (variant : Irs) -> Self { variant as u8 != 0 } } # [doc = "Field `IRS` reader - IRS"] pub type IrsR = crate :: BitReader < Irs > ; impl IrsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Irs { match self . bits { false => Irs :: DidNotOccur , true => Irs :: Occurred , } } # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Irs :: DidNotOccur } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Irs :: Occurred } } # [doc = "Field `IRS` writer - IRS"] pub type IrsW < 'a , REG > = crate :: BitWriter < 'a , REG , Irs > ; impl < 'a , REG > IrsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: DidNotOccur) } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: Occurred) } } # [doc = "ILS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ils { # [doc = "0: Interrupt high-level did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt high-level occurred"] Occurred = 1 , } impl From < Ils > for bool { # [inline (always)] fn from (variant : Ils) -> Self { variant as u8 != 0 } } # [doc = "Field `ILS` reader - ILS"] pub type IlsR = crate :: BitReader < Ils > ; impl IlsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ils { match self . bits { false => Ils :: DidNotOccur , true => Ils :: Occurred , } } # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ils :: DidNotOccur } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ils :: Occurred } } # [doc = "Field `ILS` writer - ILS"] pub type IlsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ils > ; impl < 'a , REG > IlsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: DidNotOccur) } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: Occurred) } } # [doc = "IFS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifs { # [doc = "0: Interrupt falling edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt falling edge occurred"] Occurred = 1 , } impl From < Ifs > for bool { # [inline (always)] fn from (variant : Ifs) -> Self { variant as u8 != 0 } } # [doc = "Field `IFS` reader - IFS"] pub type IfsR = crate :: BitReader < Ifs > ; impl IfsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifs { match self . bits { false => Ifs :: DidNotOccur , true => Ifs :: Occurred , } } # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ifs :: DidNotOccur } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ifs :: Occurred } } # [doc = "Field `IFS` writer - IFS"] pub type IfsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifs > ; impl < 'a , REG > IfsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: DidNotOccur) } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: Occurred) } } # [doc = "IREN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Iren { # [doc = "0: Interrupt rising edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt rising edge detection request enabled"] Enabled = 1 , } impl From < Iren > for bool { # [inline (always)] fn from (variant : Iren) -> Self { variant as u8 != 0 } } # [doc = "Field `IREN` reader - IREN"] pub type IrenR = crate :: BitReader < Iren > ; impl IrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Iren { match self . bits { false => Iren :: Disabled , true => Iren :: Enabled , } } # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Iren :: Disabled } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Iren :: Enabled } } # [doc = "Field `IREN` writer - IREN"] pub type IrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Iren > ; impl < 'a , REG > IrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Disabled) } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Enabled) } } # [doc = "ILEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ilen { # [doc = "0: Interrupt high-level detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt high-level detection request enabled"] Enabled = 1 , } impl From < Ilen > for bool { # [inline (always)] fn from (variant : Ilen) -> Self { variant as u8 != 0 } } # [doc = "Field `ILEN` reader - ILEN"] pub type IlenR = crate :: BitReader < Ilen > ; impl IlenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ilen { match self . bits { false => Ilen :: Disabled , true => Ilen :: Enabled , } } # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ilen :: Disabled } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ilen :: Enabled } } # [doc = "Field `ILEN` writer - ILEN"] pub type IlenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ilen > ; impl < 'a , REG > IlenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Disabled) } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Enabled) } } # [doc = "IFEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifen { # [doc = "0: Interrupt falling edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt falling edge detection request enabled"] Enabled = 1 , } impl From < Ifen > for bool { # [inline (always)] fn from (variant : Ifen) -> Self { variant as u8 != 0 } } # [doc = "Field `IFEN` reader - IFEN"] pub type IfenR = crate :: BitReader < Ifen > ; impl IfenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifen { match self . bits { false => Ifen :: Disabled , true => Ifen :: Enabled , } } # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ifen :: Disabled } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ifen :: Enabled } } # [doc = "Field `IFEN` writer - IFEN"] pub type IfenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifen > ; impl < 'a , REG > IfenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Disabled) } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Enabled) } } # [doc = "FEMPT\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Fempt { # [doc = "0: FIFO not empty"] NotEmpty = 0 , # [doc = "1: FIFO empty"] Empty = 1 , } impl From < Fempt > for bool { # [inline (always)] fn from (variant : Fempt) -> Self { variant as u8 != 0 } } # [doc = "Field `FEMPT` reader - FEMPT"] pub type FemptR = crate :: BitReader < Fempt > ; impl FemptR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Fempt { match self . bits { false => Fempt :: NotEmpty , true => Fempt :: Empty , } } # [doc = "FIFO not empty"] # [inline (always)] pub fn is_not_empty (& self) -> bool { * self == Fempt :: NotEmpty } # [doc = "FIFO empty"] # [inline (always)] pub fn is_empty (& self) -> bool { * self == Fempt :: Empty } } impl R { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& self) -> IrsR { IrsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& self) -> IlsR { IlsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& self) -> IfsR { IfsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& self) -> IrenR { IrenR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& self) -> IlenR { IlenR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& self) -> IfenR { IfenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - FEMPT"] # [inline (always)] pub fn fempt (& self) -> FemptR { FemptR :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& mut self) -> IrsW < SrSpec > { IrsW :: new (self , 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& mut self) -> IlsW <'_, SrSpec > { IlsW :: new (self , 1) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& mut self) -> IfsW < SrSpec > { IfsW :: new (self , 2) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& mut self) -> IrenW < SrSpec > { IrenW :: new (self , 3) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& mut self) -> IlenW < SrSpec > { IlenW :: new (self , 4) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& mut self) -> IfenW < SrSpec > { IfenW :: new (self , 5) } } # [doc = "FIFO status and interrupt register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SrSpec ; impl crate :: RegisterSpec for SrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sr::R`](R) reader structure"] impl crate :: Readable for SrSpec { } # [doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] impl crate :: Writable for SrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SR%s to value 0x40"] impl crate :: Resettable for SrSpec { const RESET_VALUE : u32 = 0x40 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sr.rs:1:10833 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn ifs (& mut self) -> IfsW < SrSpec > { IfsW :: new (self , 2) } # [doc = "Bit 3 - IREN"] # [inline (alway... [INFO] [stdout] | ^^^^^^^^^^ --------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SR%s` reader"] pub type R = crate :: R < SrSpec > ; # [doc = "Register `SR%s` writer"] pub type W = crate :: W < SrSpec > ; # [doc = "IRS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Irs { # [doc = "0: Interrupt rising edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt rising edge occurred"] Occurred = 1 , } impl From < Irs > for bool { # [inline (always)] fn from (variant : Irs) -> Self { variant as u8 != 0 } } # [doc = "Field `IRS` reader - IRS"] pub type IrsR = crate :: BitReader < Irs > ; impl IrsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Irs { match self . bits { false => Irs :: DidNotOccur , true => Irs :: Occurred , } } # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Irs :: DidNotOccur } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Irs :: Occurred } } # [doc = "Field `IRS` writer - IRS"] pub type IrsW < 'a , REG > = crate :: BitWriter < 'a , REG , Irs > ; impl < 'a , REG > IrsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: DidNotOccur) } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: Occurred) } } # [doc = "ILS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ils { # [doc = "0: Interrupt high-level did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt high-level occurred"] Occurred = 1 , } impl From < Ils > for bool { # [inline (always)] fn from (variant : Ils) -> Self { variant as u8 != 0 } } # [doc = "Field `ILS` reader - ILS"] pub type IlsR = crate :: BitReader < Ils > ; impl IlsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ils { match self . bits { false => Ils :: DidNotOccur , true => Ils :: Occurred , } } # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ils :: DidNotOccur } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ils :: Occurred } } # [doc = "Field `ILS` writer - ILS"] pub type IlsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ils > ; impl < 'a , REG > IlsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: DidNotOccur) } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: Occurred) } } # [doc = "IFS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifs { # [doc = "0: Interrupt falling edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt falling edge occurred"] Occurred = 1 , } impl From < Ifs > for bool { # [inline (always)] fn from (variant : Ifs) -> Self { variant as u8 != 0 } } # [doc = "Field `IFS` reader - IFS"] pub type IfsR = crate :: BitReader < Ifs > ; impl IfsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifs { match self . bits { false => Ifs :: DidNotOccur , true => Ifs :: Occurred , } } # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ifs :: DidNotOccur } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ifs :: Occurred } } # [doc = "Field `IFS` writer - IFS"] pub type IfsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifs > ; impl < 'a , REG > IfsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: DidNotOccur) } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: Occurred) } } # [doc = "IREN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Iren { # [doc = "0: Interrupt rising edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt rising edge detection request enabled"] Enabled = 1 , } impl From < Iren > for bool { # [inline (always)] fn from (variant : Iren) -> Self { variant as u8 != 0 } } # [doc = "Field `IREN` reader - IREN"] pub type IrenR = crate :: BitReader < Iren > ; impl IrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Iren { match self . bits { false => Iren :: Disabled , true => Iren :: Enabled , } } # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Iren :: Disabled } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Iren :: Enabled } } # [doc = "Field `IREN` writer - IREN"] pub type IrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Iren > ; impl < 'a , REG > IrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Disabled) } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Enabled) } } # [doc = "ILEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ilen { # [doc = "0: Interrupt high-level detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt high-level detection request enabled"] Enabled = 1 , } impl From < Ilen > for bool { # [inline (always)] fn from (variant : Ilen) -> Self { variant as u8 != 0 } } # [doc = "Field `ILEN` reader - ILEN"] pub type IlenR = crate :: BitReader < Ilen > ; impl IlenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ilen { match self . bits { false => Ilen :: Disabled , true => Ilen :: Enabled , } } # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ilen :: Disabled } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ilen :: Enabled } } # [doc = "Field `ILEN` writer - ILEN"] pub type IlenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ilen > ; impl < 'a , REG > IlenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Disabled) } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Enabled) } } # [doc = "IFEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifen { # [doc = "0: Interrupt falling edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt falling edge detection request enabled"] Enabled = 1 , } impl From < Ifen > for bool { # [inline (always)] fn from (variant : Ifen) -> Self { variant as u8 != 0 } } # [doc = "Field `IFEN` reader - IFEN"] pub type IfenR = crate :: BitReader < Ifen > ; impl IfenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifen { match self . bits { false => Ifen :: Disabled , true => Ifen :: Enabled , } } # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ifen :: Disabled } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ifen :: Enabled } } # [doc = "Field `IFEN` writer - IFEN"] pub type IfenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifen > ; impl < 'a , REG > IfenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Disabled) } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Enabled) } } # [doc = "FEMPT\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Fempt { # [doc = "0: FIFO not empty"] NotEmpty = 0 , # [doc = "1: FIFO empty"] Empty = 1 , } impl From < Fempt > for bool { # [inline (always)] fn from (variant : Fempt) -> Self { variant as u8 != 0 } } # [doc = "Field `FEMPT` reader - FEMPT"] pub type FemptR = crate :: BitReader < Fempt > ; impl FemptR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Fempt { match self . bits { false => Fempt :: NotEmpty , true => Fempt :: Empty , } } # [doc = "FIFO not empty"] # [inline (always)] pub fn is_not_empty (& self) -> bool { * self == Fempt :: NotEmpty } # [doc = "FIFO empty"] # [inline (always)] pub fn is_empty (& self) -> bool { * self == Fempt :: Empty } } impl R { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& self) -> IrsR { IrsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& self) -> IlsR { IlsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& self) -> IfsR { IfsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& self) -> IrenR { IrenR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& self) -> IlenR { IlenR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& self) -> IfenR { IfenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - FEMPT"] # [inline (always)] pub fn fempt (& self) -> FemptR { FemptR :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& mut self) -> IrsW < SrSpec > { IrsW :: new (self , 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& mut self) -> IlsW < SrSpec > { IlsW :: new (self , 1) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& mut self) -> IfsW <'_, SrSpec > { IfsW :: new (self , 2) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& mut self) -> IrenW < SrSpec > { IrenW :: new (self , 3) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& mut self) -> IlenW < SrSpec > { IlenW :: new (self , 4) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& mut self) -> IfenW < SrSpec > { IfenW :: new (self , 5) } } # [doc = "FIFO status and interrupt register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SrSpec ; impl crate :: RegisterSpec for SrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sr::R`](R) reader structure"] impl crate :: Readable for SrSpec { } # [doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] impl crate :: Writable for SrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SR%s to value 0x40"] impl crate :: Resettable for SrSpec { const RESET_VALUE : u32 = 0x40 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sr.rs:1:10949 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn iren (& mut self) -> IrenW < SrSpec > { IrenW :: new (self , 3) } # [doc = "Bit 4 - ILEN"] # [inline (alw... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SR%s` reader"] pub type R = crate :: R < SrSpec > ; # [doc = "Register `SR%s` writer"] pub type W = crate :: W < SrSpec > ; # [doc = "IRS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Irs { # [doc = "0: Interrupt rising edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt rising edge occurred"] Occurred = 1 , } impl From < Irs > for bool { # [inline (always)] fn from (variant : Irs) -> Self { variant as u8 != 0 } } # [doc = "Field `IRS` reader - IRS"] pub type IrsR = crate :: BitReader < Irs > ; impl IrsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Irs { match self . bits { false => Irs :: DidNotOccur , true => Irs :: Occurred , } } # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Irs :: DidNotOccur } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Irs :: Occurred } } # [doc = "Field `IRS` writer - IRS"] pub type IrsW < 'a , REG > = crate :: BitWriter < 'a , REG , Irs > ; impl < 'a , REG > IrsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: DidNotOccur) } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: Occurred) } } # [doc = "ILS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ils { # [doc = "0: Interrupt high-level did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt high-level occurred"] Occurred = 1 , } impl From < Ils > for bool { # [inline (always)] fn from (variant : Ils) -> Self { variant as u8 != 0 } } # [doc = "Field `ILS` reader - ILS"] pub type IlsR = crate :: BitReader < Ils > ; impl IlsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ils { match self . bits { false => Ils :: DidNotOccur , true => Ils :: Occurred , } } # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ils :: DidNotOccur } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ils :: Occurred } } # [doc = "Field `ILS` writer - ILS"] pub type IlsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ils > ; impl < 'a , REG > IlsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: DidNotOccur) } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: Occurred) } } # [doc = "IFS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifs { # [doc = "0: Interrupt falling edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt falling edge occurred"] Occurred = 1 , } impl From < Ifs > for bool { # [inline (always)] fn from (variant : Ifs) -> Self { variant as u8 != 0 } } # [doc = "Field `IFS` reader - IFS"] pub type IfsR = crate :: BitReader < Ifs > ; impl IfsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifs { match self . bits { false => Ifs :: DidNotOccur , true => Ifs :: Occurred , } } # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ifs :: DidNotOccur } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ifs :: Occurred } } # [doc = "Field `IFS` writer - IFS"] pub type IfsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifs > ; impl < 'a , REG > IfsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: DidNotOccur) } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: Occurred) } } # [doc = "IREN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Iren { # [doc = "0: Interrupt rising edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt rising edge detection request enabled"] Enabled = 1 , } impl From < Iren > for bool { # [inline (always)] fn from (variant : Iren) -> Self { variant as u8 != 0 } } # [doc = "Field `IREN` reader - IREN"] pub type IrenR = crate :: BitReader < Iren > ; impl IrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Iren { match self . bits { false => Iren :: Disabled , true => Iren :: Enabled , } } # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Iren :: Disabled } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Iren :: Enabled } } # [doc = "Field `IREN` writer - IREN"] pub type IrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Iren > ; impl < 'a , REG > IrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Disabled) } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Enabled) } } # [doc = "ILEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ilen { # [doc = "0: Interrupt high-level detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt high-level detection request enabled"] Enabled = 1 , } impl From < Ilen > for bool { # [inline (always)] fn from (variant : Ilen) -> Self { variant as u8 != 0 } } # [doc = "Field `ILEN` reader - ILEN"] pub type IlenR = crate :: BitReader < Ilen > ; impl IlenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ilen { match self . bits { false => Ilen :: Disabled , true => Ilen :: Enabled , } } # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ilen :: Disabled } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ilen :: Enabled } } # [doc = "Field `ILEN` writer - ILEN"] pub type IlenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ilen > ; impl < 'a , REG > IlenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Disabled) } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Enabled) } } # [doc = "IFEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifen { # [doc = "0: Interrupt falling edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt falling edge detection request enabled"] Enabled = 1 , } impl From < Ifen > for bool { # [inline (always)] fn from (variant : Ifen) -> Self { variant as u8 != 0 } } # [doc = "Field `IFEN` reader - IFEN"] pub type IfenR = crate :: BitReader < Ifen > ; impl IfenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifen { match self . bits { false => Ifen :: Disabled , true => Ifen :: Enabled , } } # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ifen :: Disabled } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ifen :: Enabled } } # [doc = "Field `IFEN` writer - IFEN"] pub type IfenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifen > ; impl < 'a , REG > IfenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Disabled) } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Enabled) } } # [doc = "FEMPT\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Fempt { # [doc = "0: FIFO not empty"] NotEmpty = 0 , # [doc = "1: FIFO empty"] Empty = 1 , } impl From < Fempt > for bool { # [inline (always)] fn from (variant : Fempt) -> Self { variant as u8 != 0 } } # [doc = "Field `FEMPT` reader - FEMPT"] pub type FemptR = crate :: BitReader < Fempt > ; impl FemptR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Fempt { match self . bits { false => Fempt :: NotEmpty , true => Fempt :: Empty , } } # [doc = "FIFO not empty"] # [inline (always)] pub fn is_not_empty (& self) -> bool { * self == Fempt :: NotEmpty } # [doc = "FIFO empty"] # [inline (always)] pub fn is_empty (& self) -> bool { * self == Fempt :: Empty } } impl R { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& self) -> IrsR { IrsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& self) -> IlsR { IlsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& self) -> IfsR { IfsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& self) -> IrenR { IrenR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& self) -> IlenR { IlenR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& self) -> IfenR { IfenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - FEMPT"] # [inline (always)] pub fn fempt (& self) -> FemptR { FemptR :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& mut self) -> IrsW < SrSpec > { IrsW :: new (self , 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& mut self) -> IlsW < SrSpec > { IlsW :: new (self , 1) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& mut self) -> IfsW < SrSpec > { IfsW :: new (self , 2) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& mut self) -> IrenW <'_, SrSpec > { IrenW :: new (self , 3) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& mut self) -> IlenW < SrSpec > { IlenW :: new (self , 4) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& mut self) -> IfenW < SrSpec > { IfenW :: new (self , 5) } } # [doc = "FIFO status and interrupt register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SrSpec ; impl crate :: RegisterSpec for SrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sr::R`](R) reader structure"] impl crate :: Readable for SrSpec { } # [doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] impl crate :: Writable for SrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SR%s to value 0x40"] impl crate :: Resettable for SrSpec { const RESET_VALUE : u32 = 0x40 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sr.rs:1:11067 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn ilen (& mut self) -> IlenW < SrSpec > { IlenW :: new (self , 4) } # [doc = "Bit 5 - IFEN"] # [inline (alw... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SR%s` reader"] pub type R = crate :: R < SrSpec > ; # [doc = "Register `SR%s` writer"] pub type W = crate :: W < SrSpec > ; # [doc = "IRS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Irs { # [doc = "0: Interrupt rising edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt rising edge occurred"] Occurred = 1 , } impl From < Irs > for bool { # [inline (always)] fn from (variant : Irs) -> Self { variant as u8 != 0 } } # [doc = "Field `IRS` reader - IRS"] pub type IrsR = crate :: BitReader < Irs > ; impl IrsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Irs { match self . bits { false => Irs :: DidNotOccur , true => Irs :: Occurred , } } # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Irs :: DidNotOccur } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Irs :: Occurred } } # [doc = "Field `IRS` writer - IRS"] pub type IrsW < 'a , REG > = crate :: BitWriter < 'a , REG , Irs > ; impl < 'a , REG > IrsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: DidNotOccur) } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: Occurred) } } # [doc = "ILS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ils { # [doc = "0: Interrupt high-level did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt high-level occurred"] Occurred = 1 , } impl From < Ils > for bool { # [inline (always)] fn from (variant : Ils) -> Self { variant as u8 != 0 } } # [doc = "Field `ILS` reader - ILS"] pub type IlsR = crate :: BitReader < Ils > ; impl IlsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ils { match self . bits { false => Ils :: DidNotOccur , true => Ils :: Occurred , } } # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ils :: DidNotOccur } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ils :: Occurred } } # [doc = "Field `ILS` writer - ILS"] pub type IlsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ils > ; impl < 'a , REG > IlsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: DidNotOccur) } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: Occurred) } } # [doc = "IFS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifs { # [doc = "0: Interrupt falling edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt falling edge occurred"] Occurred = 1 , } impl From < Ifs > for bool { # [inline (always)] fn from (variant : Ifs) -> Self { variant as u8 != 0 } } # [doc = "Field `IFS` reader - IFS"] pub type IfsR = crate :: BitReader < Ifs > ; impl IfsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifs { match self . bits { false => Ifs :: DidNotOccur , true => Ifs :: Occurred , } } # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ifs :: DidNotOccur } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ifs :: Occurred } } # [doc = "Field `IFS` writer - IFS"] pub type IfsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifs > ; impl < 'a , REG > IfsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: DidNotOccur) } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: Occurred) } } # [doc = "IREN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Iren { # [doc = "0: Interrupt rising edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt rising edge detection request enabled"] Enabled = 1 , } impl From < Iren > for bool { # [inline (always)] fn from (variant : Iren) -> Self { variant as u8 != 0 } } # [doc = "Field `IREN` reader - IREN"] pub type IrenR = crate :: BitReader < Iren > ; impl IrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Iren { match self . bits { false => Iren :: Disabled , true => Iren :: Enabled , } } # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Iren :: Disabled } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Iren :: Enabled } } # [doc = "Field `IREN` writer - IREN"] pub type IrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Iren > ; impl < 'a , REG > IrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Disabled) } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Enabled) } } # [doc = "ILEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ilen { # [doc = "0: Interrupt high-level detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt high-level detection request enabled"] Enabled = 1 , } impl From < Ilen > for bool { # [inline (always)] fn from (variant : Ilen) -> Self { variant as u8 != 0 } } # [doc = "Field `ILEN` reader - ILEN"] pub type IlenR = crate :: BitReader < Ilen > ; impl IlenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ilen { match self . bits { false => Ilen :: Disabled , true => Ilen :: Enabled , } } # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ilen :: Disabled } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ilen :: Enabled } } # [doc = "Field `ILEN` writer - ILEN"] pub type IlenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ilen > ; impl < 'a , REG > IlenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Disabled) } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Enabled) } } # [doc = "IFEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifen { # [doc = "0: Interrupt falling edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt falling edge detection request enabled"] Enabled = 1 , } impl From < Ifen > for bool { # [inline (always)] fn from (variant : Ifen) -> Self { variant as u8 != 0 } } # [doc = "Field `IFEN` reader - IFEN"] pub type IfenR = crate :: BitReader < Ifen > ; impl IfenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifen { match self . bits { false => Ifen :: Disabled , true => Ifen :: Enabled , } } # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ifen :: Disabled } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ifen :: Enabled } } # [doc = "Field `IFEN` writer - IFEN"] pub type IfenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifen > ; impl < 'a , REG > IfenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Disabled) } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Enabled) } } # [doc = "FEMPT\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Fempt { # [doc = "0: FIFO not empty"] NotEmpty = 0 , # [doc = "1: FIFO empty"] Empty = 1 , } impl From < Fempt > for bool { # [inline (always)] fn from (variant : Fempt) -> Self { variant as u8 != 0 } } # [doc = "Field `FEMPT` reader - FEMPT"] pub type FemptR = crate :: BitReader < Fempt > ; impl FemptR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Fempt { match self . bits { false => Fempt :: NotEmpty , true => Fempt :: Empty , } } # [doc = "FIFO not empty"] # [inline (always)] pub fn is_not_empty (& self) -> bool { * self == Fempt :: NotEmpty } # [doc = "FIFO empty"] # [inline (always)] pub fn is_empty (& self) -> bool { * self == Fempt :: Empty } } impl R { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& self) -> IrsR { IrsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& self) -> IlsR { IlsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& self) -> IfsR { IfsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& self) -> IrenR { IrenR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& self) -> IlenR { IlenR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& self) -> IfenR { IfenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - FEMPT"] # [inline (always)] pub fn fempt (& self) -> FemptR { FemptR :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& mut self) -> IrsW < SrSpec > { IrsW :: new (self , 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& mut self) -> IlsW < SrSpec > { IlsW :: new (self , 1) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& mut self) -> IfsW < SrSpec > { IfsW :: new (self , 2) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& mut self) -> IrenW < SrSpec > { IrenW :: new (self , 3) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& mut self) -> IlenW <'_, SrSpec > { IlenW :: new (self , 4) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& mut self) -> IfenW < SrSpec > { IfenW :: new (self , 5) } } # [doc = "FIFO status and interrupt register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SrSpec ; impl crate :: RegisterSpec for SrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sr::R`](R) reader structure"] impl crate :: Readable for SrSpec { } # [doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] impl crate :: Writable for SrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SR%s to value 0x40"] impl crate :: Resettable for SrSpec { const RESET_VALUE : u32 = 0x40 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sr.rs:1:11185 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn ifen (& mut self) -> IfenW < SrSpec > { IfenW :: new (self , 5) } } # [doc = "FIFO status and interrupt r... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SR%s` reader"] pub type R = crate :: R < SrSpec > ; # [doc = "Register `SR%s` writer"] pub type W = crate :: W < SrSpec > ; # [doc = "IRS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Irs { # [doc = "0: Interrupt rising edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt rising edge occurred"] Occurred = 1 , } impl From < Irs > for bool { # [inline (always)] fn from (variant : Irs) -> Self { variant as u8 != 0 } } # [doc = "Field `IRS` reader - IRS"] pub type IrsR = crate :: BitReader < Irs > ; impl IrsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Irs { match self . bits { false => Irs :: DidNotOccur , true => Irs :: Occurred , } } # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Irs :: DidNotOccur } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Irs :: Occurred } } # [doc = "Field `IRS` writer - IRS"] pub type IrsW < 'a , REG > = crate :: BitWriter < 'a , REG , Irs > ; impl < 'a , REG > IrsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: DidNotOccur) } # [doc = "Interrupt rising edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Irs :: Occurred) } } # [doc = "ILS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ils { # [doc = "0: Interrupt high-level did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt high-level occurred"] Occurred = 1 , } impl From < Ils > for bool { # [inline (always)] fn from (variant : Ils) -> Self { variant as u8 != 0 } } # [doc = "Field `ILS` reader - ILS"] pub type IlsR = crate :: BitReader < Ils > ; impl IlsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ils { match self . bits { false => Ils :: DidNotOccur , true => Ils :: Occurred , } } # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ils :: DidNotOccur } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ils :: Occurred } } # [doc = "Field `ILS` writer - ILS"] pub type IlsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ils > ; impl < 'a , REG > IlsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: DidNotOccur) } # [doc = "Interrupt high-level occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ils :: Occurred) } } # [doc = "IFS\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifs { # [doc = "0: Interrupt falling edge did not occur"] DidNotOccur = 0 , # [doc = "1: Interrupt falling edge occurred"] Occurred = 1 , } impl From < Ifs > for bool { # [inline (always)] fn from (variant : Ifs) -> Self { variant as u8 != 0 } } # [doc = "Field `IFS` reader - IFS"] pub type IfsR = crate :: BitReader < Ifs > ; impl IfsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifs { match self . bits { false => Ifs :: DidNotOccur , true => Ifs :: Occurred , } } # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn is_did_not_occur (& self) -> bool { * self == Ifs :: DidNotOccur } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn is_occurred (& self) -> bool { * self == Ifs :: Occurred } } # [doc = "Field `IFS` writer - IFS"] pub type IfsW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifs > ; impl < 'a , REG > IfsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge did not occur"] # [inline (always)] pub fn did_not_occur (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: DidNotOccur) } # [doc = "Interrupt falling edge occurred"] # [inline (always)] pub fn occurred (self) -> & 'a mut crate :: W < REG > { self . variant (Ifs :: Occurred) } } # [doc = "IREN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Iren { # [doc = "0: Interrupt rising edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt rising edge detection request enabled"] Enabled = 1 , } impl From < Iren > for bool { # [inline (always)] fn from (variant : Iren) -> Self { variant as u8 != 0 } } # [doc = "Field `IREN` reader - IREN"] pub type IrenR = crate :: BitReader < Iren > ; impl IrenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Iren { match self . bits { false => Iren :: Disabled , true => Iren :: Enabled , } } # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Iren :: Disabled } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Iren :: Enabled } } # [doc = "Field `IREN` writer - IREN"] pub type IrenW < 'a , REG > = crate :: BitWriter < 'a , REG , Iren > ; impl < 'a , REG > IrenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt rising edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Disabled) } # [doc = "Interrupt rising edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Iren :: Enabled) } } # [doc = "ILEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ilen { # [doc = "0: Interrupt high-level detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt high-level detection request enabled"] Enabled = 1 , } impl From < Ilen > for bool { # [inline (always)] fn from (variant : Ilen) -> Self { variant as u8 != 0 } } # [doc = "Field `ILEN` reader - ILEN"] pub type IlenR = crate :: BitReader < Ilen > ; impl IlenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ilen { match self . bits { false => Ilen :: Disabled , true => Ilen :: Enabled , } } # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ilen :: Disabled } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ilen :: Enabled } } # [doc = "Field `ILEN` writer - ILEN"] pub type IlenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ilen > ; impl < 'a , REG > IlenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt high-level detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Disabled) } # [doc = "Interrupt high-level detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ilen :: Enabled) } } # [doc = "IFEN\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ifen { # [doc = "0: Interrupt falling edge detection request disabled"] Disabled = 0 , # [doc = "1: Interrupt falling edge detection request enabled"] Enabled = 1 , } impl From < Ifen > for bool { # [inline (always)] fn from (variant : Ifen) -> Self { variant as u8 != 0 } } # [doc = "Field `IFEN` reader - IFEN"] pub type IfenR = crate :: BitReader < Ifen > ; impl IfenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ifen { match self . bits { false => Ifen :: Disabled , true => Ifen :: Enabled , } } # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ifen :: Disabled } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ifen :: Enabled } } # [doc = "Field `IFEN` writer - IFEN"] pub type IfenW < 'a , REG > = crate :: BitWriter < 'a , REG , Ifen > ; impl < 'a , REG > IfenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Interrupt falling edge detection request disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Disabled) } # [doc = "Interrupt falling edge detection request enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ifen :: Enabled) } } # [doc = "FEMPT\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Fempt { # [doc = "0: FIFO not empty"] NotEmpty = 0 , # [doc = "1: FIFO empty"] Empty = 1 , } impl From < Fempt > for bool { # [inline (always)] fn from (variant : Fempt) -> Self { variant as u8 != 0 } } # [doc = "Field `FEMPT` reader - FEMPT"] pub type FemptR = crate :: BitReader < Fempt > ; impl FemptR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Fempt { match self . bits { false => Fempt :: NotEmpty , true => Fempt :: Empty , } } # [doc = "FIFO not empty"] # [inline (always)] pub fn is_not_empty (& self) -> bool { * self == Fempt :: NotEmpty } # [doc = "FIFO empty"] # [inline (always)] pub fn is_empty (& self) -> bool { * self == Fempt :: Empty } } impl R { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& self) -> IrsR { IrsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& self) -> IlsR { IlsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& self) -> IfsR { IfsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& self) -> IrenR { IrenR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& self) -> IlenR { IlenR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& self) -> IfenR { IfenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - FEMPT"] # [inline (always)] pub fn fempt (& self) -> FemptR { FemptR :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bit 0 - IRS"] # [inline (always)] pub fn irs (& mut self) -> IrsW < SrSpec > { IrsW :: new (self , 0) } # [doc = "Bit 1 - ILS"] # [inline (always)] pub fn ils (& mut self) -> IlsW < SrSpec > { IlsW :: new (self , 1) } # [doc = "Bit 2 - IFS"] # [inline (always)] pub fn ifs (& mut self) -> IfsW < SrSpec > { IfsW :: new (self , 2) } # [doc = "Bit 3 - IREN"] # [inline (always)] pub fn iren (& mut self) -> IrenW < SrSpec > { IrenW :: new (self , 3) } # [doc = "Bit 4 - ILEN"] # [inline (always)] pub fn ilen (& mut self) -> IlenW < SrSpec > { IlenW :: new (self , 4) } # [doc = "Bit 5 - IFEN"] # [inline (always)] pub fn ifen (& mut self) -> IfenW <'_, SrSpec > { IfenW :: new (self , 5) } } # [doc = "FIFO status and interrupt register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SrSpec ; impl crate :: RegisterSpec for SrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sr::R`](R) reader structure"] impl crate :: Readable for SrSpec { } # [doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] impl crate :: Writable for SrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SR%s to value 0x40"] impl crate :: Resettable for SrSpec { const RESET_VALUE : u32 = 0x40 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem2.rs:1:1627 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem2Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM2` reader"] pub type R = crate :: R < Pmem2Spec > ; # [doc = "Register `PMEM2` writer"] pub type W = crate :: W < Pmem2Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW <'_, Pmem2Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem2Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem2Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem2Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem2Spec ; impl crate :: RegisterSpec for Pmem2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem2::R`](R) reader structure"] impl crate :: Readable for Pmem2Spec { } # [doc = "`write(|w| ..)` method takes [`pmem2::W`](W) writer structure"] impl crate :: Writable for Pmem2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM2 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem2Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem2.rs:1:1763 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem2Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM2` reader"] pub type R = crate :: R < Pmem2Spec > ; # [doc = "Register `PMEM2` writer"] pub type W = crate :: W < Pmem2Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem2Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW <'_, Pmem2Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem2Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem2Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem2Spec ; impl crate :: RegisterSpec for Pmem2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem2::R`](R) reader structure"] impl crate :: Readable for Pmem2Spec { } # [doc = "`write(|w| ..)` method takes [`pmem2::W`](W) writer structure"] impl crate :: Writable for Pmem2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM2 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem2Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem2.rs:1:1902 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem2Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM2` reader"] pub type R = crate :: R < Pmem2Spec > ; # [doc = "Register `PMEM2` writer"] pub type W = crate :: W < Pmem2Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem2Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem2Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW <'_, Pmem2Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem2Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem2Spec ; impl crate :: RegisterSpec for Pmem2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem2::R`](R) reader structure"] impl crate :: Readable for Pmem2Spec { } # [doc = "`write(|w| ..)` method takes [`pmem2::W`](W) writer structure"] impl crate :: Writable for Pmem2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM2 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem2Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem2.rs:1:2040 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem2Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space ti... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM2` reader"] pub type R = crate :: R < Pmem2Spec > ; # [doc = "Register `PMEM2` writer"] pub type W = crate :: W < Pmem2Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem2Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem2Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem2Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW <'_, Pmem2Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem2Spec ; impl crate :: RegisterSpec for Pmem2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem2::R`](R) reader structure"] impl crate :: Readable for Pmem2Spec { } # [doc = "`write(|w| ..)` method takes [`pmem2::W`](W) writer structure"] impl crate :: Writable for Pmem2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM2 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem2Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt2.rs:1:1627 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn attset (& mut self) -> AttsetW < Patt2Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT2` reader"] pub type R = crate :: R < Patt2Spec > ; # [doc = "Register `PATT2` writer"] pub type W = crate :: W < Patt2Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW <'_, Patt2Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt2Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW < Patt2Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt2Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`patt2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt2Spec ; impl crate :: RegisterSpec for Patt2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt2::R`](R) reader structure"] impl crate :: Readable for Patt2Spec { } # [doc = "`write(|w| ..)` method takes [`patt2::W`](W) writer structure"] impl crate :: Writable for Patt2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT2 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt2Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt2.rs:1:1763 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt2Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT2` reader"] pub type R = crate :: R < Patt2Spec > ; # [doc = "Register `PATT2` writer"] pub type W = crate :: W < Patt2Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW < Patt2Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW <'_, Patt2Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW < Patt2Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt2Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`patt2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt2Spec ; impl crate :: RegisterSpec for Patt2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt2::R`](R) reader structure"] impl crate :: Readable for Patt2Spec { } # [doc = "`write(|w| ..)` method takes [`patt2::W`](W) writer structure"] impl crate :: Writable for Patt2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT2 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt2Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt2.rs:1:1902 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn atthold (& mut self) -> AttholdW < Patt2Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT2` reader"] pub type R = crate :: R < Patt2Spec > ; # [doc = "Register `PATT2` writer"] pub type W = crate :: W < Patt2Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW < Patt2Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt2Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW <'_, Patt2Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt2Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`patt2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt2Spec ; impl crate :: RegisterSpec for Patt2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt2::R`](R) reader structure"] impl crate :: Readable for Patt2Spec { } # [doc = "`write(|w| ..)` method takes [`patt2::W`](W) writer structure"] impl crate :: Writable for Patt2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT2 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt2Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt2.rs:1:2040 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt2Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT2` reader"] pub type R = crate :: R < Patt2Spec > ; # [doc = "Register `PATT2` writer"] pub type W = crate :: W < Patt2Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW < Patt2Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt2Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW < Patt2Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW <'_, Patt2Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`patt2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt2Spec ; impl crate :: RegisterSpec for Patt2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt2::R`](R) reader structure"] impl crate :: Readable for Patt2Spec { } # [doc = "`write(|w| ..)` method takes [`patt2::W`](W) writer structure"] impl crate :: Writable for Patt2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT2 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt2Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem3.rs:1:1627 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem3Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM3` reader"] pub type R = crate :: R < Pmem3Spec > ; # [doc = "Register `PMEM3` writer"] pub type W = crate :: W < Pmem3Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW <'_, Pmem3Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem3Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem3Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem3Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem3Spec ; impl crate :: RegisterSpec for Pmem3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem3::R`](R) reader structure"] impl crate :: Readable for Pmem3Spec { } # [doc = "`write(|w| ..)` method takes [`pmem3::W`](W) writer structure"] impl crate :: Writable for Pmem3Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM3 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem3Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem3.rs:1:1763 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem3Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM3` reader"] pub type R = crate :: R < Pmem3Spec > ; # [doc = "Register `PMEM3` writer"] pub type W = crate :: W < Pmem3Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem3Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW <'_, Pmem3Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem3Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem3Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem3Spec ; impl crate :: RegisterSpec for Pmem3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem3::R`](R) reader structure"] impl crate :: Readable for Pmem3Spec { } # [doc = "`write(|w| ..)` method takes [`pmem3::W`](W) writer structure"] impl crate :: Writable for Pmem3Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM3 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem3Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem3.rs:1:1902 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem3Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM3` reader"] pub type R = crate :: R < Pmem3Spec > ; # [doc = "Register `PMEM3` writer"] pub type W = crate :: W < Pmem3Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem3Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem3Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW <'_, Pmem3Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem3Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem3Spec ; impl crate :: RegisterSpec for Pmem3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem3::R`](R) reader structure"] impl crate :: Readable for Pmem3Spec { } # [doc = "`write(|w| ..)` method takes [`pmem3::W`](W) writer structure"] impl crate :: Writable for Pmem3Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM3 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem3Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem3.rs:1:2040 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem3Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space ti... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM3` reader"] pub type R = crate :: R < Pmem3Spec > ; # [doc = "Register `PMEM3` writer"] pub type W = crate :: W < Pmem3Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem3Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem3Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem3Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW <'_, Pmem3Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem3Spec ; impl crate :: RegisterSpec for Pmem3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem3::R`](R) reader structure"] impl crate :: Readable for Pmem3Spec { } # [doc = "`write(|w| ..)` method takes [`pmem3::W`](W) writer structure"] impl crate :: Writable for Pmem3Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM3 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem3Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt3.rs:1:1627 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn attset (& mut self) -> AttsetW < Patt3Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT3` reader"] pub type R = crate :: R < Patt3Spec > ; # [doc = "Register `PATT3` writer"] pub type W = crate :: W < Patt3Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW <'_, Patt3Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt3Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW < Patt3Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt3Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`patt3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt3Spec ; impl crate :: RegisterSpec for Patt3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt3::R`](R) reader structure"] impl crate :: Readable for Patt3Spec { } # [doc = "`write(|w| ..)` method takes [`patt3::W`](W) writer structure"] impl crate :: Writable for Patt3Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT3 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt3Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt3.rs:1:1763 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt3Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT3` reader"] pub type R = crate :: R < Patt3Spec > ; # [doc = "Register `PATT3` writer"] pub type W = crate :: W < Patt3Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW < Patt3Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW <'_, Patt3Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW < Patt3Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt3Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`patt3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt3Spec ; impl crate :: RegisterSpec for Patt3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt3::R`](R) reader structure"] impl crate :: Readable for Patt3Spec { } # [doc = "`write(|w| ..)` method takes [`patt3::W`](W) writer structure"] impl crate :: Writable for Patt3Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT3 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt3Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt3.rs:1:1902 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn atthold (& mut self) -> AttholdW < Patt3Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT3` reader"] pub type R = crate :: R < Patt3Spec > ; # [doc = "Register `PATT3` writer"] pub type W = crate :: W < Patt3Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW < Patt3Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt3Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW <'_, Patt3Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt3Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`patt3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt3Spec ; impl crate :: RegisterSpec for Patt3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt3::R`](R) reader structure"] impl crate :: Readable for Patt3Spec { } # [doc = "`write(|w| ..)` method takes [`patt3::W`](W) writer structure"] impl crate :: Writable for Patt3Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT3 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt3Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt3.rs:1:2040 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt3Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT3` reader"] pub type R = crate :: R < Patt3Spec > ; # [doc = "Register `PATT3` writer"] pub type W = crate :: W < Patt3Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW < Patt3Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt3Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW < Patt3Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW <'_, Patt3Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`patt3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt3Spec ; impl crate :: RegisterSpec for Patt3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt3::R`](R) reader structure"] impl crate :: Readable for Patt3Spec { } # [doc = "`write(|w| ..)` method takes [`patt3::W`](W) writer structure"] impl crate :: Writable for Patt3Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT3 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt3Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem4.rs:1:1627 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem4Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM4` reader"] pub type R = crate :: R < Pmem4Spec > ; # [doc = "Register `PMEM4` writer"] pub type W = crate :: W < Pmem4Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW <'_, Pmem4Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem4Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem4Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem4Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem4Spec ; impl crate :: RegisterSpec for Pmem4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem4::R`](R) reader structure"] impl crate :: Readable for Pmem4Spec { } # [doc = "`write(|w| ..)` method takes [`pmem4::W`](W) writer structure"] impl crate :: Writable for Pmem4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem4.rs:1:1763 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem4Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM4` reader"] pub type R = crate :: R < Pmem4Spec > ; # [doc = "Register `PMEM4` writer"] pub type W = crate :: W < Pmem4Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem4Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW <'_, Pmem4Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem4Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem4Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem4Spec ; impl crate :: RegisterSpec for Pmem4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem4::R`](R) reader structure"] impl crate :: Readable for Pmem4Spec { } # [doc = "`write(|w| ..)` method takes [`pmem4::W`](W) writer structure"] impl crate :: Writable for Pmem4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem4.rs:1:1902 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem4Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM4` reader"] pub type R = crate :: R < Pmem4Spec > ; # [doc = "Register `PMEM4` writer"] pub type W = crate :: W < Pmem4Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem4Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem4Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW <'_, Pmem4Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem4Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem4Spec ; impl crate :: RegisterSpec for Pmem4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem4::R`](R) reader structure"] impl crate :: Readable for Pmem4Spec { } # [doc = "`write(|w| ..)` method takes [`pmem4::W`](W) writer structure"] impl crate :: Writable for Pmem4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pmem4.rs:1:2040 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn memhiz (& mut self) -> MemhizW < Pmem4Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space ti... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PMEM4` reader"] pub type R = crate :: R < Pmem4Spec > ; # [doc = "Register `PMEM4` writer"] pub type W = crate :: W < Pmem4Spec > ; # [doc = "Field `MEMSET` reader - MEMSETx"] pub type MemsetR = crate :: FieldReader ; # [doc = "Field `MEMSET` writer - MEMSETx"] pub type MemsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMWAIT` reader - MEMWAITx"] pub type MemwaitR = crate :: FieldReader ; # [doc = "Field `MEMWAIT` writer - MEMWAITx"] pub type MemwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHOLD` reader - MEMHOLDx"] pub type MemholdR = crate :: FieldReader ; # [doc = "Field `MEMHOLD` writer - MEMHOLDx"] pub type MemholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MEMHIZ` reader - MEMHIZx"] pub type MemhizR = crate :: FieldReader ; # [doc = "Field `MEMHIZ` writer - MEMHIZx"] pub type MemhizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& self) -> MemsetR { MemsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& self) -> MemwaitR { MemwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& self) -> MemholdR { MemholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& self) -> MemhizR { MemhizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - MEMSETx"] # [inline (always)] pub fn memset (& mut self) -> MemsetW < Pmem4Spec > { MemsetW :: new (self , 0) } # [doc = "Bits 8:15 - MEMWAITx"] # [inline (always)] pub fn memwait (& mut self) -> MemwaitW < Pmem4Spec > { MemwaitW :: new (self , 8) } # [doc = "Bits 16:23 - MEMHOLDx"] # [inline (always)] pub fn memhold (& mut self) -> MemholdW < Pmem4Spec > { MemholdW :: new (self , 16) } # [doc = "Bits 24:31 - MEMHIZx"] # [inline (always)] pub fn memhiz (& mut self) -> MemhizW <'_, Pmem4Spec > { MemhizW :: new (self , 24) } } # [doc = "Common memory space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pmem4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pmem4Spec ; impl crate :: RegisterSpec for Pmem4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmem4::R`](R) reader structure"] impl crate :: Readable for Pmem4Spec { } # [doc = "`write(|w| ..)` method takes [`pmem4::W`](W) writer structure"] impl crate :: Writable for Pmem4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PMEM4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pmem4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt4.rs:1:1627 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn attset (& mut self) -> AttsetW < Patt4Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT4` reader"] pub type R = crate :: R < Patt4Spec > ; # [doc = "Register `PATT4` writer"] pub type W = crate :: W < Patt4Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW <'_, Patt4Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt4Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW < Patt4Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt4Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`patt4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt4Spec ; impl crate :: RegisterSpec for Patt4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt4::R`](R) reader structure"] impl crate :: Readable for Patt4Spec { } # [doc = "`write(|w| ..)` method takes [`patt4::W`](W) writer structure"] impl crate :: Writable for Patt4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt4.rs:1:1763 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt4Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT4` reader"] pub type R = crate :: R < Patt4Spec > ; # [doc = "Register `PATT4` writer"] pub type W = crate :: W < Patt4Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW < Patt4Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW <'_, Patt4Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW < Patt4Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt4Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`patt4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt4Spec ; impl crate :: RegisterSpec for Patt4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt4::R`](R) reader structure"] impl crate :: Readable for Patt4Spec { } # [doc = "`write(|w| ..)` method takes [`patt4::W`](W) writer structure"] impl crate :: Writable for Patt4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt4.rs:1:1902 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn atthold (& mut self) -> AttholdW < Patt4Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT4` reader"] pub type R = crate :: R < Patt4Spec > ; # [doc = "Register `PATT4` writer"] pub type W = crate :: W < Patt4Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW < Patt4Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt4Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW <'_, Patt4Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt4Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`patt4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt4Spec ; impl crate :: RegisterSpec for Patt4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt4::R`](R) reader structure"] impl crate :: Readable for Patt4Spec { } # [doc = "`write(|w| ..)` method takes [`patt4::W`](W) writer structure"] impl crate :: Writable for Patt4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/patt4.rs:1:2040 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn atthiz (& mut self) -> AtthizW < Patt4Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PATT4` reader"] pub type R = crate :: R < Patt4Spec > ; # [doc = "Register `PATT4` writer"] pub type W = crate :: W < Patt4Spec > ; # [doc = "Field `ATTSET` reader - ATTSETx"] pub type AttsetR = crate :: FieldReader ; # [doc = "Field `ATTSET` writer - ATTSETx"] pub type AttsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTWAIT` reader - ATTWAITx"] pub type AttwaitR = crate :: FieldReader ; # [doc = "Field `ATTWAIT` writer - ATTWAITx"] pub type AttwaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHOLD` reader - ATTHOLDx"] pub type AttholdR = crate :: FieldReader ; # [doc = "Field `ATTHOLD` writer - ATTHOLDx"] pub type AttholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ATTHIZ` reader - ATTHIZx"] pub type AtthizR = crate :: FieldReader ; # [doc = "Field `ATTHIZ` writer - ATTHIZx"] pub type AtthizW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& self) -> AttsetR { AttsetR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& self) -> AttwaitR { AttwaitR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& self) -> AttholdR { AttholdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& self) -> AtthizR { AtthizR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - ATTSETx"] # [inline (always)] pub fn attset (& mut self) -> AttsetW < Patt4Spec > { AttsetW :: new (self , 0) } # [doc = "Bits 8:15 - ATTWAITx"] # [inline (always)] pub fn attwait (& mut self) -> AttwaitW < Patt4Spec > { AttwaitW :: new (self , 8) } # [doc = "Bits 16:23 - ATTHOLDx"] # [inline (always)] pub fn atthold (& mut self) -> AttholdW < Patt4Spec > { AttholdW :: new (self , 16) } # [doc = "Bits 24:31 - ATTHIZx"] # [inline (always)] pub fn atthiz (& mut self) -> AtthizW <'_, Patt4Spec > { AtthizW :: new (self , 24) } } # [doc = "Attribute memory space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`patt4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Patt4Spec ; impl crate :: RegisterSpec for Patt4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`patt4::R`](R) reader structure"] impl crate :: Readable for Patt4Spec { } # [doc = "`write(|w| ..)` method takes [`patt4::W`](W) writer structure"] impl crate :: Writable for Patt4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PATT4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Patt4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pio4.rs:1:1610 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn iosetx (& mut self) -> IosetxW < Pio4Spec > { IosetxW :: new (self , 0) } # [doc = "Bits 8:15 - IOWAITx"] # [... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PIO4` reader"] pub type R = crate :: R < Pio4Spec > ; # [doc = "Register `PIO4` writer"] pub type W = crate :: W < Pio4Spec > ; # [doc = "Field `IOSETx` reader - IOSETx"] pub type IosetxR = crate :: FieldReader ; # [doc = "Field `IOSETx` writer - IOSETx"] pub type IosetxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOWAITx` reader - IOWAITx"] pub type IowaitxR = crate :: FieldReader ; # [doc = "Field `IOWAITx` writer - IOWAITx"] pub type IowaitxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOHOLDx` reader - IOHOLDx"] pub type IoholdxR = crate :: FieldReader ; # [doc = "Field `IOHOLDx` writer - IOHOLDx"] pub type IoholdxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOHIZx` reader - IOHIZx"] pub type IohizxR = crate :: FieldReader ; # [doc = "Field `IOHIZx` writer - IOHIZx"] pub type IohizxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - IOSETx"] # [inline (always)] pub fn iosetx (& self) -> IosetxR { IosetxR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - IOWAITx"] # [inline (always)] pub fn iowaitx (& self) -> IowaitxR { IowaitxR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - IOHOLDx"] # [inline (always)] pub fn ioholdx (& self) -> IoholdxR { IoholdxR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - IOHIZx"] # [inline (always)] pub fn iohizx (& self) -> IohizxR { IohizxR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - IOSETx"] # [inline (always)] pub fn iosetx (& mut self) -> IosetxW <'_, Pio4Spec > { IosetxW :: new (self , 0) } # [doc = "Bits 8:15 - IOWAITx"] # [inline (always)] pub fn iowaitx (& mut self) -> IowaitxW < Pio4Spec > { IowaitxW :: new (self , 8) } # [doc = "Bits 16:23 - IOHOLDx"] # [inline (always)] pub fn ioholdx (& mut self) -> IoholdxW < Pio4Spec > { IoholdxW :: new (self , 16) } # [doc = "Bits 24:31 - IOHIZx"] # [inline (always)] pub fn iohizx (& mut self) -> IohizxW < Pio4Spec > { IohizxW :: new (self , 24) } } # [doc = "I/O space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pio4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pio4Spec ; impl crate :: RegisterSpec for Pio4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pio4::R`](R) reader structure"] impl crate :: Readable for Pio4Spec { } # [doc = "`write(|w| ..)` method takes [`pio4::W`](W) writer structure"] impl crate :: Writable for Pio4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PIO4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pio4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pio4.rs:1:1744 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn iowaitx (& mut self) -> IowaitxW < Pio4Spec > { IowaitxW :: new (self , 8) } # [doc = "Bits 16:23 - IOHOLDx"] #... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PIO4` reader"] pub type R = crate :: R < Pio4Spec > ; # [doc = "Register `PIO4` writer"] pub type W = crate :: W < Pio4Spec > ; # [doc = "Field `IOSETx` reader - IOSETx"] pub type IosetxR = crate :: FieldReader ; # [doc = "Field `IOSETx` writer - IOSETx"] pub type IosetxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOWAITx` reader - IOWAITx"] pub type IowaitxR = crate :: FieldReader ; # [doc = "Field `IOWAITx` writer - IOWAITx"] pub type IowaitxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOHOLDx` reader - IOHOLDx"] pub type IoholdxR = crate :: FieldReader ; # [doc = "Field `IOHOLDx` writer - IOHOLDx"] pub type IoholdxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOHIZx` reader - IOHIZx"] pub type IohizxR = crate :: FieldReader ; # [doc = "Field `IOHIZx` writer - IOHIZx"] pub type IohizxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - IOSETx"] # [inline (always)] pub fn iosetx (& self) -> IosetxR { IosetxR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - IOWAITx"] # [inline (always)] pub fn iowaitx (& self) -> IowaitxR { IowaitxR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - IOHOLDx"] # [inline (always)] pub fn ioholdx (& self) -> IoholdxR { IoholdxR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - IOHIZx"] # [inline (always)] pub fn iohizx (& self) -> IohizxR { IohizxR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - IOSETx"] # [inline (always)] pub fn iosetx (& mut self) -> IosetxW < Pio4Spec > { IosetxW :: new (self , 0) } # [doc = "Bits 8:15 - IOWAITx"] # [inline (always)] pub fn iowaitx (& mut self) -> IowaitxW <'_, Pio4Spec > { IowaitxW :: new (self , 8) } # [doc = "Bits 16:23 - IOHOLDx"] # [inline (always)] pub fn ioholdx (& mut self) -> IoholdxW < Pio4Spec > { IoholdxW :: new (self , 16) } # [doc = "Bits 24:31 - IOHIZx"] # [inline (always)] pub fn iohizx (& mut self) -> IohizxW < Pio4Spec > { IohizxW :: new (self , 24) } } # [doc = "I/O space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pio4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pio4Spec ; impl crate :: RegisterSpec for Pio4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pio4::R`](R) reader structure"] impl crate :: Readable for Pio4Spec { } # [doc = "`write(|w| ..)` method takes [`pio4::W`](W) writer structure"] impl crate :: Writable for Pio4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PIO4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pio4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pio4.rs:1:1881 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn ioholdx (& mut self) -> IoholdxW < Pio4Spec > { IoholdxW :: new (self , 16) } # [doc = "Bits 24:31 - IOHIZx"] #... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PIO4` reader"] pub type R = crate :: R < Pio4Spec > ; # [doc = "Register `PIO4` writer"] pub type W = crate :: W < Pio4Spec > ; # [doc = "Field `IOSETx` reader - IOSETx"] pub type IosetxR = crate :: FieldReader ; # [doc = "Field `IOSETx` writer - IOSETx"] pub type IosetxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOWAITx` reader - IOWAITx"] pub type IowaitxR = crate :: FieldReader ; # [doc = "Field `IOWAITx` writer - IOWAITx"] pub type IowaitxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOHOLDx` reader - IOHOLDx"] pub type IoholdxR = crate :: FieldReader ; # [doc = "Field `IOHOLDx` writer - IOHOLDx"] pub type IoholdxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOHIZx` reader - IOHIZx"] pub type IohizxR = crate :: FieldReader ; # [doc = "Field `IOHIZx` writer - IOHIZx"] pub type IohizxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - IOSETx"] # [inline (always)] pub fn iosetx (& self) -> IosetxR { IosetxR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - IOWAITx"] # [inline (always)] pub fn iowaitx (& self) -> IowaitxR { IowaitxR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - IOHOLDx"] # [inline (always)] pub fn ioholdx (& self) -> IoholdxR { IoholdxR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - IOHIZx"] # [inline (always)] pub fn iohizx (& self) -> IohizxR { IohizxR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - IOSETx"] # [inline (always)] pub fn iosetx (& mut self) -> IosetxW < Pio4Spec > { IosetxW :: new (self , 0) } # [doc = "Bits 8:15 - IOWAITx"] # [inline (always)] pub fn iowaitx (& mut self) -> IowaitxW < Pio4Spec > { IowaitxW :: new (self , 8) } # [doc = "Bits 16:23 - IOHOLDx"] # [inline (always)] pub fn ioholdx (& mut self) -> IoholdxW <'_, Pio4Spec > { IoholdxW :: new (self , 16) } # [doc = "Bits 24:31 - IOHIZx"] # [inline (always)] pub fn iohizx (& mut self) -> IohizxW < Pio4Spec > { IohizxW :: new (self , 24) } } # [doc = "I/O space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pio4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pio4Spec ; impl crate :: RegisterSpec for Pio4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pio4::R`](R) reader structure"] impl crate :: Readable for Pio4Spec { } # [doc = "`write(|w| ..)` method takes [`pio4::W`](W) writer structure"] impl crate :: Writable for Pio4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PIO4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pio4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/pio4.rs:1:2017 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn iohizx (& mut self) -> IohizxW < Pio4Spec > { IohizxW :: new (self , 24) } } # [doc = "I/O space timing regis... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PIO4` reader"] pub type R = crate :: R < Pio4Spec > ; # [doc = "Register `PIO4` writer"] pub type W = crate :: W < Pio4Spec > ; # [doc = "Field `IOSETx` reader - IOSETx"] pub type IosetxR = crate :: FieldReader ; # [doc = "Field `IOSETx` writer - IOSETx"] pub type IosetxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOWAITx` reader - IOWAITx"] pub type IowaitxR = crate :: FieldReader ; # [doc = "Field `IOWAITx` writer - IOWAITx"] pub type IowaitxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOHOLDx` reader - IOHOLDx"] pub type IoholdxR = crate :: FieldReader ; # [doc = "Field `IOHOLDx` writer - IOHOLDx"] pub type IoholdxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IOHIZx` reader - IOHIZx"] pub type IohizxR = crate :: FieldReader ; # [doc = "Field `IOHIZx` writer - IOHIZx"] pub type IohizxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - IOSETx"] # [inline (always)] pub fn iosetx (& self) -> IosetxR { IosetxR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - IOWAITx"] # [inline (always)] pub fn iowaitx (& self) -> IowaitxR { IowaitxR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - IOHOLDx"] # [inline (always)] pub fn ioholdx (& self) -> IoholdxR { IoholdxR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - IOHIZx"] # [inline (always)] pub fn iohizx (& self) -> IohizxR { IohizxR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - IOSETx"] # [inline (always)] pub fn iosetx (& mut self) -> IosetxW < Pio4Spec > { IosetxW :: new (self , 0) } # [doc = "Bits 8:15 - IOWAITx"] # [inline (always)] pub fn iowaitx (& mut self) -> IowaitxW < Pio4Spec > { IowaitxW :: new (self , 8) } # [doc = "Bits 16:23 - IOHOLDx"] # [inline (always)] pub fn ioholdx (& mut self) -> IoholdxW < Pio4Spec > { IoholdxW :: new (self , 16) } # [doc = "Bits 24:31 - IOHIZx"] # [inline (always)] pub fn iohizx (& mut self) -> IohizxW <'_, Pio4Spec > { IohizxW :: new (self , 24) } } # [doc = "I/O space timing register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pio4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Pio4Spec ; impl crate :: RegisterSpec for Pio4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pio4::R`](R) reader structure"] impl crate :: Readable for Pio4Spec { } # [doc = "`write(|w| ..)` method takes [`pio4::W`](W) writer structure"] impl crate :: Writable for Pio4Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PIO4 to value 0xfcfc_fcfc"] impl crate :: Resettable for Pio4Spec { const RESET_VALUE : u32 = 0xfcfc_fcfc ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bwtr.rs:1:3761 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn addset (& mut self) -> AddsetW < BwtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [in... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BWTR%s` reader"] pub type R = crate :: R < BwtrSpec > ; # [doc = "Register `BWTR%s` writer"] pub type W = crate :: W < BwtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW <'_, BwtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW < BwtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW < BwtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW < BwtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW < BwtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash write timing registers %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bwtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bwtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BwtrSpec ; impl crate :: RegisterSpec for BwtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bwtr::R`](R) reader structure"] impl crate :: Readable for BwtrSpec { } # [doc = "`write(|w| ..)` method takes [`bwtr::W`](W) writer structure"] impl crate :: Writable for BwtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BWTR%s to value 0x0fff_ffff"] impl crate :: Resettable for BwtrSpec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bwtr.rs:1:3892 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn addhld (& mut self) -> AddhldW < BwtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [i... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BWTR%s` reader"] pub type R = crate :: R < BwtrSpec > ; # [doc = "Register `BWTR%s` writer"] pub type W = crate :: W < BwtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW < BwtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW <'_, BwtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW < BwtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW < BwtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW < BwtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash write timing registers %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bwtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bwtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BwtrSpec ; impl crate :: RegisterSpec for BwtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bwtr::R`](R) reader structure"] impl crate :: Readable for BwtrSpec { } # [doc = "`write(|w| ..)` method takes [`bwtr::W`](W) writer structure"] impl crate :: Writable for BwtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BWTR%s to value 0x0fff_ffff"] impl crate :: Resettable for BwtrSpec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bwtr.rs:1:4024 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn datast (& mut self) -> DatastW < BwtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # ... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BWTR%s` reader"] pub type R = crate :: R < BwtrSpec > ; # [doc = "Register `BWTR%s` writer"] pub type W = crate :: W < BwtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW < BwtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW < BwtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW <'_, BwtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW < BwtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW < BwtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash write timing registers %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bwtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bwtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BwtrSpec ; impl crate :: RegisterSpec for BwtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bwtr::R`](R) reader structure"] impl crate :: Readable for BwtrSpec { } # [doc = "`write(|w| ..)` method takes [`bwtr::W`](W) writer structure"] impl crate :: Writable for BwtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BWTR%s to value 0x0fff_ffff"] impl crate :: Resettable for BwtrSpec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bwtr.rs:1:4159 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn busturn (& mut self) -> BusturnW < BwtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 28:29 - ACCMOD"] #... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BWTR%s` reader"] pub type R = crate :: R < BwtrSpec > ; # [doc = "Register `BWTR%s` writer"] pub type W = crate :: W < BwtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW < BwtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW < BwtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW < BwtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW <'_, BwtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW < BwtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash write timing registers %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bwtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bwtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BwtrSpec ; impl crate :: RegisterSpec for BwtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bwtr::R`](R) reader structure"] impl crate :: Readable for BwtrSpec { } # [doc = "`write(|w| ..)` method takes [`bwtr::W`](W) writer structure"] impl crate :: Writable for BwtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BWTR%s to value 0x0fff_ffff"] impl crate :: Resettable for BwtrSpec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/bwtr.rs:1:4295 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn accmod (& mut self) -> AccmodW < BwtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash write t... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `BWTR%s` reader"] pub type R = crate :: R < BwtrSpec > ; # [doc = "Register `BWTR%s` writer"] pub type W = crate :: W < BwtrSpec > ; # [doc = "Field `ADDSET` reader - ADDSET"] pub type AddsetR = crate :: FieldReader ; # [doc = "Field `ADDSET` writer - ADDSET"] pub type AddsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "Field `ADDHLD` reader - ADDHLD"] pub type AddhldR = crate :: FieldReader ; # [doc = "Field `ADDHLD` writer - ADDHLD"] pub type AddhldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DATAST` reader - DATAST"] pub type DatastR = crate :: FieldReader ; # [doc = "Field `DATAST` writer - DATAST"] pub type DatastW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `BUSTURN` reader - BUSTURN"] pub type BusturnR = crate :: FieldReader ; # [doc = "Field `BUSTURN` writer - BUSTURN"] pub type BusturnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , u8 , crate :: Safe > ; # [doc = "ACCMOD\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Accmod { # [doc = "0: Access mode A"] A = 0 , # [doc = "1: Access mode B"] B = 1 , # [doc = "2: Access mode C"] C = 2 , # [doc = "3: Access mode D"] D = 3 , } impl From < Accmod > for u8 { # [inline (always)] fn from (variant : Accmod) -> Self { variant as _ } } impl crate :: FieldSpec for Accmod { type Ux = u8 ; } impl crate :: IsEnum for Accmod { } # [doc = "Field `ACCMOD` reader - ACCMOD"] pub type AccmodR = crate :: FieldReader < Accmod > ; impl AccmodR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Accmod { match self . bits { 0 => Accmod :: A , 1 => Accmod :: B , 2 => Accmod :: C , 3 => Accmod :: D , _ => unreachable ! () , } } # [doc = "Access mode A"] # [inline (always)] pub fn is_a (& self) -> bool { * self == Accmod :: A } # [doc = "Access mode B"] # [inline (always)] pub fn is_b (& self) -> bool { * self == Accmod :: B } # [doc = "Access mode C"] # [inline (always)] pub fn is_c (& self) -> bool { * self == Accmod :: C } # [doc = "Access mode D"] # [inline (always)] pub fn is_d (& self) -> bool { * self == Accmod :: D } } # [doc = "Field `ACCMOD` writer - ACCMOD"] pub type AccmodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Accmod , crate :: Safe > ; impl < 'a , REG > AccmodW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Access mode A"] # [inline (always)] pub fn a (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: A) } # [doc = "Access mode B"] # [inline (always)] pub fn b (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: B) } # [doc = "Access mode C"] # [inline (always)] pub fn c (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: C) } # [doc = "Access mode D"] # [inline (always)] pub fn d (self) -> & 'a mut crate :: W < REG > { self . variant (Accmod :: D) } } impl R { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& self) -> AddsetR { AddsetR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& self) -> AddhldR { AddhldR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& self) -> DatastR { DatastR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& self) -> BusturnR { BusturnR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& self) -> AccmodR { AccmodR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:3 - ADDSET"] # [inline (always)] pub fn addset (& mut self) -> AddsetW < BwtrSpec > { AddsetW :: new (self , 0) } # [doc = "Bits 4:7 - ADDHLD"] # [inline (always)] pub fn addhld (& mut self) -> AddhldW < BwtrSpec > { AddhldW :: new (self , 4) } # [doc = "Bits 8:15 - DATAST"] # [inline (always)] pub fn datast (& mut self) -> DatastW < BwtrSpec > { DatastW :: new (self , 8) } # [doc = "Bits 16:19 - BUSTURN"] # [inline (always)] pub fn busturn (& mut self) -> BusturnW < BwtrSpec > { BusturnW :: new (self , 16) } # [doc = "Bits 28:29 - ACCMOD"] # [inline (always)] pub fn accmod (& mut self) -> AccmodW <'_, BwtrSpec > { AccmodW :: new (self , 28) } } # [doc = "SRAM/NOR-Flash write timing registers %s\n\nYou can [`read`](crate::Reg::read) this register and get [`bwtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bwtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BwtrSpec ; impl crate :: RegisterSpec for BwtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bwtr::R`](R) reader structure"] impl crate :: Readable for BwtrSpec { } # [doc = "`write(|w| ..)` method takes [`bwtr::W`](W) writer structure"] impl crate :: Writable for BwtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets BWTR%s to value 0x0fff_ffff"] impl crate :: Resettable for BwtrSpec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr1.rs:1:3436 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr1Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row addres... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR1` reader"] pub type R = crate :: R < Sdcr1Spec > ; # [doc = "Register `SDCR1` writer"] pub type W = crate :: W < Sdcr1Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RBURST` reader - Burst read"] pub type RburstR = crate :: BitReader ; # [doc = "Field `RBURST` writer - Burst read"] pub type RburstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RPIPE` reader - Read pipe"] pub type RpipeR = crate :: FieldReader ; # [doc = "Field `RPIPE` writer - Read pipe"] pub type RpipeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& self) -> RburstR { RburstR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& self) -> RpipeR { RpipeR :: new (((self . bits >> 13) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW <'_, Sdcr1Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr1Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr1Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr1Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr1Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr1Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr1Spec > { SdclkW :: new (self , 10) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& mut self) -> RburstW < Sdcr1Spec > { RburstW :: new (self , 12) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& mut self) -> RpipeW < Sdcr1Spec > { RpipeW :: new (self , 13) } } # [doc = "SDRAM Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr1Spec ; impl crate :: RegisterSpec for Sdcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr1::R`](R) reader structure"] impl crate :: Readable for Sdcr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr1::W`](W) writer structure"] impl crate :: Writable for Sdcr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR1 to value 0x02d0"] impl crate :: Resettable for Sdcr1Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr1.rs:1:3576 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr1Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus widt... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR1` reader"] pub type R = crate :: R < Sdcr1Spec > ; # [doc = "Register `SDCR1` writer"] pub type W = crate :: W < Sdcr1Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RBURST` reader - Burst read"] pub type RburstR = crate :: BitReader ; # [doc = "Field `RBURST` writer - Burst read"] pub type RburstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RPIPE` reader - Read pipe"] pub type RpipeR = crate :: FieldReader ; # [doc = "Field `RPIPE` writer - Read pipe"] pub type RpipeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& self) -> RburstR { RburstR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& self) -> RpipeR { RpipeR :: new (((self . bits >> 13) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr1Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW <'_, Sdcr1Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr1Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr1Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr1Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr1Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr1Spec > { SdclkW :: new (self , 10) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& mut self) -> RburstW < Sdcr1Spec > { RburstW :: new (self , 12) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& mut self) -> RpipeW < Sdcr1Spec > { RpipeW :: new (self , 13) } } # [doc = "SDRAM Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr1Spec ; impl crate :: RegisterSpec for Sdcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr1::R`](R) reader structure"] impl crate :: Readable for Sdcr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr1::W`](W) writer structure"] impl crate :: Writable for Sdcr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR1 to value 0x02d0"] impl crate :: Resettable for Sdcr1Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr1.rs:1:3713 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr1Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal b... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR1` reader"] pub type R = crate :: R < Sdcr1Spec > ; # [doc = "Register `SDCR1` writer"] pub type W = crate :: W < Sdcr1Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RBURST` reader - Burst read"] pub type RburstR = crate :: BitReader ; # [doc = "Field `RBURST` writer - Burst read"] pub type RburstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RPIPE` reader - Read pipe"] pub type RpipeR = crate :: FieldReader ; # [doc = "Field `RPIPE` writer - Read pipe"] pub type RpipeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& self) -> RburstR { RburstR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& self) -> RpipeR { RpipeR :: new (((self . bits >> 13) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr1Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr1Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW <'_, Sdcr1Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr1Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr1Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr1Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr1Spec > { SdclkW :: new (self , 10) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& mut self) -> RburstW < Sdcr1Spec > { RburstW :: new (self , 12) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& mut self) -> RpipeW < Sdcr1Spec > { RpipeW :: new (self , 13) } } # [doc = "SDRAM Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr1Spec ; impl crate :: RegisterSpec for Sdcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr1::R`](R) reader structure"] impl crate :: Readable for Sdcr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr1::W`](W) writer structure"] impl crate :: Writable for Sdcr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR1 to value 0x02d0"] impl crate :: Resettable for Sdcr1Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr1.rs:1:3852 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr1Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inl... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR1` reader"] pub type R = crate :: R < Sdcr1Spec > ; # [doc = "Register `SDCR1` writer"] pub type W = crate :: W < Sdcr1Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RBURST` reader - Burst read"] pub type RburstR = crate :: BitReader ; # [doc = "Field `RBURST` writer - Burst read"] pub type RburstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RPIPE` reader - Read pipe"] pub type RpipeR = crate :: FieldReader ; # [doc = "Field `RPIPE` writer - Read pipe"] pub type RpipeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& self) -> RburstR { RburstR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& self) -> RpipeR { RpipeR :: new (((self . bits >> 13) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr1Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr1Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr1Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW <'_, Sdcr1Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr1Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr1Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr1Spec > { SdclkW :: new (self , 10) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& mut self) -> RburstW < Sdcr1Spec > { RburstW :: new (self , 12) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& mut self) -> RpipeW < Sdcr1Spec > { RpipeW :: new (self , 13) } } # [doc = "SDRAM Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr1Spec ; impl crate :: RegisterSpec for Sdcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr1::R`](R) reader structure"] impl crate :: Readable for Sdcr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr1::W`](W) writer structure"] impl crate :: Writable for Sdcr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR1 to value 0x02d0"] impl crate :: Resettable for Sdcr1Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr1.rs:1:3978 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr1Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # ... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR1` reader"] pub type R = crate :: R < Sdcr1Spec > ; # [doc = "Register `SDCR1` writer"] pub type W = crate :: W < Sdcr1Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RBURST` reader - Burst read"] pub type RburstR = crate :: BitReader ; # [doc = "Field `RBURST` writer - Burst read"] pub type RburstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RPIPE` reader - Read pipe"] pub type RpipeR = crate :: FieldReader ; # [doc = "Field `RPIPE` writer - Read pipe"] pub type RpipeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& self) -> RburstR { RburstR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& self) -> RpipeR { RpipeR :: new (((self . bits >> 13) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr1Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr1Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr1Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr1Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW <'_, Sdcr1Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr1Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr1Spec > { SdclkW :: new (self , 10) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& mut self) -> RburstW < Sdcr1Spec > { RburstW :: new (self , 12) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& mut self) -> RpipeW < Sdcr1Spec > { RpipeW :: new (self , 13) } } # [doc = "SDRAM Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr1Spec ; impl crate :: RegisterSpec for Sdcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr1::R`](R) reader structure"] impl crate :: Readable for Sdcr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr1::W`](W) writer structure"] impl crate :: Writable for Sdcr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR1 to value 0x02d0"] impl crate :: Resettable for Sdcr1Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr1.rs:1:4107 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr1Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock config... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR1` reader"] pub type R = crate :: R < Sdcr1Spec > ; # [doc = "Register `SDCR1` writer"] pub type W = crate :: W < Sdcr1Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RBURST` reader - Burst read"] pub type RburstR = crate :: BitReader ; # [doc = "Field `RBURST` writer - Burst read"] pub type RburstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RPIPE` reader - Read pipe"] pub type RpipeR = crate :: FieldReader ; # [doc = "Field `RPIPE` writer - Read pipe"] pub type RpipeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& self) -> RburstR { RburstR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& self) -> RpipeR { RpipeR :: new (((self . bits >> 13) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr1Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr1Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr1Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr1Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr1Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW <'_, Sdcr1Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr1Spec > { SdclkW :: new (self , 10) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& mut self) -> RburstW < Sdcr1Spec > { RburstW :: new (self , 12) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& mut self) -> RpipeW < Sdcr1Spec > { RpipeW :: new (self , 13) } } # [doc = "SDRAM Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr1Spec ; impl crate :: RegisterSpec for Sdcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr1::R`](R) reader structure"] impl crate :: Readable for Sdcr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr1::W`](W) writer structure"] impl crate :: Writable for Sdcr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR1 to value 0x02d0"] impl crate :: Resettable for Sdcr1Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr1.rs:1:4251 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr1Spec > { SdclkW :: new (self , 10) } # [doc = "Bit 12 - Burst read"] # [... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR1` reader"] pub type R = crate :: R < Sdcr1Spec > ; # [doc = "Register `SDCR1` writer"] pub type W = crate :: W < Sdcr1Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RBURST` reader - Burst read"] pub type RburstR = crate :: BitReader ; # [doc = "Field `RBURST` writer - Burst read"] pub type RburstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RPIPE` reader - Read pipe"] pub type RpipeR = crate :: FieldReader ; # [doc = "Field `RPIPE` writer - Read pipe"] pub type RpipeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& self) -> RburstR { RburstR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& self) -> RpipeR { RpipeR :: new (((self . bits >> 13) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr1Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr1Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr1Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr1Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr1Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr1Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW <'_, Sdcr1Spec > { SdclkW :: new (self , 10) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& mut self) -> RburstW < Sdcr1Spec > { RburstW :: new (self , 12) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& mut self) -> RpipeW < Sdcr1Spec > { RpipeW :: new (self , 13) } } # [doc = "SDRAM Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr1Spec ; impl crate :: RegisterSpec for Sdcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr1::R`](R) reader structure"] impl crate :: Readable for Sdcr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr1::W`](W) writer structure"] impl crate :: Writable for Sdcr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR1 to value 0x02d0"] impl crate :: Resettable for Sdcr1Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr1.rs:1:4384 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn rburst (& mut self) -> RburstW < Sdcr1Spec > { RburstW :: new (self , 12) } # [doc = "Bits 13:14 - Read pipe"]... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR1` reader"] pub type R = crate :: R < Sdcr1Spec > ; # [doc = "Register `SDCR1` writer"] pub type W = crate :: W < Sdcr1Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RBURST` reader - Burst read"] pub type RburstR = crate :: BitReader ; # [doc = "Field `RBURST` writer - Burst read"] pub type RburstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RPIPE` reader - Read pipe"] pub type RpipeR = crate :: FieldReader ; # [doc = "Field `RPIPE` writer - Read pipe"] pub type RpipeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& self) -> RburstR { RburstR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& self) -> RpipeR { RpipeR :: new (((self . bits >> 13) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr1Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr1Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr1Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr1Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr1Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr1Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr1Spec > { SdclkW :: new (self , 10) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& mut self) -> RburstW <'_, Sdcr1Spec > { RburstW :: new (self , 12) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& mut self) -> RpipeW < Sdcr1Spec > { RpipeW :: new (self , 13) } } # [doc = "SDRAM Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr1Spec ; impl crate :: RegisterSpec for Sdcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr1::R`](R) reader structure"] impl crate :: Readable for Sdcr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr1::W`](W) writer structure"] impl crate :: Writable for Sdcr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR1 to value 0x02d0"] impl crate :: Resettable for Sdcr1Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr1.rs:1:4521 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn rpipe (& mut self) -> RpipeW < Sdcr1Spec > { RpipeW :: new (self , 13) } } # [doc = "SDRAM Control Register ... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR1` reader"] pub type R = crate :: R < Sdcr1Spec > ; # [doc = "Register `SDCR1` writer"] pub type W = crate :: W < Sdcr1Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RBURST` reader - Burst read"] pub type RburstR = crate :: BitReader ; # [doc = "Field `RBURST` writer - Burst read"] pub type RburstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RPIPE` reader - Read pipe"] pub type RpipeR = crate :: FieldReader ; # [doc = "Field `RPIPE` writer - Read pipe"] pub type RpipeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& self) -> RburstR { RburstR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& self) -> RpipeR { RpipeR :: new (((self . bits >> 13) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr1Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr1Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr1Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr1Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr1Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr1Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr1Spec > { SdclkW :: new (self , 10) } # [doc = "Bit 12 - Burst read"] # [inline (always)] pub fn rburst (& mut self) -> RburstW < Sdcr1Spec > { RburstW :: new (self , 12) } # [doc = "Bits 13:14 - Read pipe"] # [inline (always)] pub fn rpipe (& mut self) -> RpipeW <'_, Sdcr1Spec > { RpipeW :: new (self , 13) } } # [doc = "SDRAM Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr1Spec ; impl crate :: RegisterSpec for Sdcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr1::R`](R) reader structure"] impl crate :: Readable for Sdcr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr1::W`](W) writer structure"] impl crate :: Writable for Sdcr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR1 to value 0x02d0"] impl crate :: Resettable for Sdcr1Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr2.rs:1:2757 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr2Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row addres... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR2` reader"] pub type R = crate :: R < Sdcr2Spec > ; # [doc = "Register `SDCR2` writer"] pub type W = crate :: W < Sdcr2Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW <'_, Sdcr2Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr2Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr2Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr2Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr2Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr2Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr2Spec > { SdclkW :: new (self , 10) } } # [doc = "SDRAM Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr2Spec ; impl crate :: RegisterSpec for Sdcr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr2::R`](R) reader structure"] impl crate :: Readable for Sdcr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr2::W`](W) writer structure"] impl crate :: Writable for Sdcr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR2 to value 0x02d0"] impl crate :: Resettable for Sdcr2Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr2.rs:1:2897 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr2Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus widt... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR2` reader"] pub type R = crate :: R < Sdcr2Spec > ; # [doc = "Register `SDCR2` writer"] pub type W = crate :: W < Sdcr2Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr2Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW <'_, Sdcr2Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr2Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr2Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr2Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr2Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr2Spec > { SdclkW :: new (self , 10) } } # [doc = "SDRAM Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr2Spec ; impl crate :: RegisterSpec for Sdcr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr2::R`](R) reader structure"] impl crate :: Readable for Sdcr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr2::W`](W) writer structure"] impl crate :: Writable for Sdcr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR2 to value 0x02d0"] impl crate :: Resettable for Sdcr2Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr2.rs:1:3034 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr2Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal b... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR2` reader"] pub type R = crate :: R < Sdcr2Spec > ; # [doc = "Register `SDCR2` writer"] pub type W = crate :: W < Sdcr2Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr2Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr2Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW <'_, Sdcr2Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr2Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr2Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr2Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr2Spec > { SdclkW :: new (self , 10) } } # [doc = "SDRAM Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr2Spec ; impl crate :: RegisterSpec for Sdcr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr2::R`](R) reader structure"] impl crate :: Readable for Sdcr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr2::W`](W) writer structure"] impl crate :: Writable for Sdcr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR2 to value 0x02d0"] impl crate :: Resettable for Sdcr2Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr2.rs:1:3173 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr2Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inl... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR2` reader"] pub type R = crate :: R < Sdcr2Spec > ; # [doc = "Register `SDCR2` writer"] pub type W = crate :: W < Sdcr2Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr2Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr2Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr2Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW <'_, Sdcr2Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr2Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr2Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr2Spec > { SdclkW :: new (self , 10) } } # [doc = "SDRAM Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr2Spec ; impl crate :: RegisterSpec for Sdcr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr2::R`](R) reader structure"] impl crate :: Readable for Sdcr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr2::W`](W) writer structure"] impl crate :: Writable for Sdcr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR2 to value 0x02d0"] impl crate :: Resettable for Sdcr2Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr2.rs:1:3299 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr2Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # ... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR2` reader"] pub type R = crate :: R < Sdcr2Spec > ; # [doc = "Register `SDCR2` writer"] pub type W = crate :: W < Sdcr2Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr2Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr2Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr2Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr2Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW <'_, Sdcr2Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr2Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr2Spec > { SdclkW :: new (self , 10) } } # [doc = "SDRAM Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr2Spec ; impl crate :: RegisterSpec for Sdcr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr2::R`](R) reader structure"] impl crate :: Readable for Sdcr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr2::W`](W) writer structure"] impl crate :: Writable for Sdcr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR2 to value 0x02d0"] impl crate :: Resettable for Sdcr2Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr2.rs:1:3428 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr2Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock config... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR2` reader"] pub type R = crate :: R < Sdcr2Spec > ; # [doc = "Register `SDCR2` writer"] pub type W = crate :: W < Sdcr2Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr2Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr2Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr2Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr2Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr2Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW <'_, Sdcr2Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr2Spec > { SdclkW :: new (self , 10) } } # [doc = "SDRAM Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr2Spec ; impl crate :: RegisterSpec for Sdcr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr2::R`](R) reader structure"] impl crate :: Readable for Sdcr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr2::W`](W) writer structure"] impl crate :: Writable for Sdcr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR2 to value 0x02d0"] impl crate :: Resettable for Sdcr2Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcr2.rs:1:3572 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn sdclk (& mut self) -> SdclkW < Sdcr2Spec > { SdclkW :: new (self , 10) } } # [doc = "SDRAM Control Register ... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCR2` reader"] pub type R = crate :: R < Sdcr2Spec > ; # [doc = "Register `SDCR2` writer"] pub type W = crate :: W < Sdcr2Spec > ; # [doc = "Field `NC` reader - Number of column address bits"] pub type NcR = crate :: FieldReader ; # [doc = "Field `NC` writer - Number of column address bits"] pub type NcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NR` reader - Number of row address bits"] pub type NrR = crate :: FieldReader ; # [doc = "Field `NR` writer - Number of row address bits"] pub type NrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MWID` reader - Memory data bus width"] pub type MwidR = crate :: FieldReader ; # [doc = "Field `MWID` writer - Memory data bus width"] pub type MwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NB` reader - Number of internal banks"] pub type NbR = crate :: BitReader ; # [doc = "Field `NB` writer - Number of internal banks"] pub type NbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAS` reader - CAS latency"] pub type CasR = crate :: FieldReader ; # [doc = "Field `CAS` writer - CAS latency"] pub type CasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WP` reader - Write protection"] pub type WpR = crate :: BitReader ; # [doc = "Field `WP` writer - Write protection"] pub type WpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDCLK` reader - SDRAM clock configuration"] pub type SdclkR = crate :: FieldReader ; # [doc = "Field `SDCLK` writer - SDRAM clock configuration"] pub type SdclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& self) -> NcR { NcR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& self) -> NrR { NrR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& self) -> MwidR { MwidR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& self) -> NbR { NbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& self) -> CasR { CasR :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& self) -> WpR { WpR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& self) -> SdclkR { SdclkR :: new (((self . bits >> 10) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Number of column address bits"] # [inline (always)] pub fn nc (& mut self) -> NcW < Sdcr2Spec > { NcW :: new (self , 0) } # [doc = "Bits 2:3 - Number of row address bits"] # [inline (always)] pub fn nr (& mut self) -> NrW < Sdcr2Spec > { NrW :: new (self , 2) } # [doc = "Bits 4:5 - Memory data bus width"] # [inline (always)] pub fn mwid (& mut self) -> MwidW < Sdcr2Spec > { MwidW :: new (self , 4) } # [doc = "Bit 6 - Number of internal banks"] # [inline (always)] pub fn nb (& mut self) -> NbW < Sdcr2Spec > { NbW :: new (self , 6) } # [doc = "Bits 7:8 - CAS latency"] # [inline (always)] pub fn cas (& mut self) -> CasW < Sdcr2Spec > { CasW :: new (self , 7) } # [doc = "Bit 9 - Write protection"] # [inline (always)] pub fn wp (& mut self) -> WpW < Sdcr2Spec > { WpW :: new (self , 9) } # [doc = "Bits 10:11 - SDRAM clock configuration"] # [inline (always)] pub fn sdclk (& mut self) -> SdclkW <'_, Sdcr2Spec > { SdclkW :: new (self , 10) } } # [doc = "SDRAM Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdcr2Spec ; impl crate :: RegisterSpec for Sdcr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcr2::R`](R) reader structure"] impl crate :: Readable for Sdcr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdcr2::W`](W) writer structure"] impl crate :: Writable for Sdcr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCR2 to value 0x02d0"] impl crate :: Resettable for Sdcr2Spec { const RESET_VALUE : u32 = 0x02d0 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr1.rs:1:2797 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr1Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR1` reader"] pub type R = crate :: R < Sdtr1Spec > ; # [doc = "Register `SDTR1` writer"] pub type W = crate :: W < Sdtr1Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW <'_, Sdtr1Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr1Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr1Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr1Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr1Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr1Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr1Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr1Spec ; impl crate :: RegisterSpec for Sdtr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr1::R`](R) reader structure"] impl crate :: Readable for Sdtr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr1::W`](W) writer structure"] impl crate :: Writable for Sdtr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR1 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr1Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr1.rs:1:2940 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr1Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh tim... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR1` reader"] pub type R = crate :: R < Sdtr1Spec > ; # [doc = "Register `SDTR1` writer"] pub type W = crate :: W < Sdtr1Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr1Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW <'_, Sdtr1Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr1Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr1Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr1Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr1Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr1Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr1Spec ; impl crate :: RegisterSpec for Sdtr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr1::R`](R) reader structure"] impl crate :: Readable for Sdtr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr1::W`](W) writer structure"] impl crate :: Writable for Sdtr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR1 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr1Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr1.rs:1:3078 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr1Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR1` reader"] pub type R = crate :: R < Sdtr1Spec > ; # [doc = "Register `SDTR1` writer"] pub type W = crate :: W < Sdtr1Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr1Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr1Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW <'_, Sdtr1Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr1Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr1Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr1Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr1Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr1Spec ; impl crate :: RegisterSpec for Sdtr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr1::R`](R) reader structure"] impl crate :: Readable for Sdtr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr1::W`](W) writer structure"] impl crate :: Writable for Sdtr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR1 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr1Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr1.rs:1:3214 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr1Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR1` reader"] pub type R = crate :: R < Sdtr1Spec > ; # [doc = "Register `SDTR1` writer"] pub type W = crate :: W < Sdtr1Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr1Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr1Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr1Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW <'_, Sdtr1Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr1Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr1Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr1Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr1Spec ; impl crate :: RegisterSpec for Sdtr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr1::R`](R) reader structure"] impl crate :: Readable for Sdtr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr1::W`](W) writer structure"] impl crate :: Writable for Sdtr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR1 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr1Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr1.rs:1:3348 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr1Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge d... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR1` reader"] pub type R = crate :: R < Sdtr1Spec > ; # [doc = "Register `SDTR1` writer"] pub type W = crate :: W < Sdtr1Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr1Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr1Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr1Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr1Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW <'_, Sdtr1Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr1Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr1Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr1Spec ; impl crate :: RegisterSpec for Sdtr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr1::R`](R) reader structure"] impl crate :: Readable for Sdtr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr1::W`](W) writer structure"] impl crate :: Writable for Sdtr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR1 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr1Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr1.rs:1:3487 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr1Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column d... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR1` reader"] pub type R = crate :: R < Sdtr1Spec > ; # [doc = "Register `SDTR1` writer"] pub type W = crate :: W < Sdtr1Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr1Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr1Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr1Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr1Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr1Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW <'_, Sdtr1Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr1Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr1Spec ; impl crate :: RegisterSpec for Sdtr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr1::R`](R) reader structure"] impl crate :: Readable for Sdtr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr1::W`](W) writer structure"] impl crate :: Writable for Sdtr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR1 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr1Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr1.rs:1:3627 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr1Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 1\n... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR1` reader"] pub type R = crate :: R < Sdtr1Spec > ; # [doc = "Register `SDTR1` writer"] pub type W = crate :: W < Sdtr1Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr1Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr1Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr1Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr1Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr1Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr1Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW <'_, Sdtr1Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr1Spec ; impl crate :: RegisterSpec for Sdtr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr1::R`](R) reader structure"] impl crate :: Readable for Sdtr1Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr1::W`](W) writer structure"] impl crate :: Writable for Sdtr1Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR1 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr1Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr2.rs:1:2797 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr2Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR2` reader"] pub type R = crate :: R < Sdtr2Spec > ; # [doc = "Register `SDTR2` writer"] pub type W = crate :: W < Sdtr2Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW <'_, Sdtr2Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr2Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr2Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr2Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr2Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr2Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr2Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr2Spec ; impl crate :: RegisterSpec for Sdtr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr2::R`](R) reader structure"] impl crate :: Readable for Sdtr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr2::W`](W) writer structure"] impl crate :: Writable for Sdtr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR2 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr2Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr2.rs:1:2940 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr2Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh tim... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR2` reader"] pub type R = crate :: R < Sdtr2Spec > ; # [doc = "Register `SDTR2` writer"] pub type W = crate :: W < Sdtr2Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr2Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW <'_, Sdtr2Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr2Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr2Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr2Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr2Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr2Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr2Spec ; impl crate :: RegisterSpec for Sdtr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr2::R`](R) reader structure"] impl crate :: Readable for Sdtr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr2::W`](W) writer structure"] impl crate :: Writable for Sdtr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR2 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr2Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr2.rs:1:3078 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr2Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR2` reader"] pub type R = crate :: R < Sdtr2Spec > ; # [doc = "Register `SDTR2` writer"] pub type W = crate :: W < Sdtr2Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr2Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr2Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW <'_, Sdtr2Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr2Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr2Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr2Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr2Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr2Spec ; impl crate :: RegisterSpec for Sdtr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr2::R`](R) reader structure"] impl crate :: Readable for Sdtr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr2::W`](W) writer structure"] impl crate :: Writable for Sdtr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR2 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr2Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr2.rs:1:3214 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr2Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR2` reader"] pub type R = crate :: R < Sdtr2Spec > ; # [doc = "Register `SDTR2` writer"] pub type W = crate :: W < Sdtr2Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr2Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr2Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr2Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW <'_, Sdtr2Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr2Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr2Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr2Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr2Spec ; impl crate :: RegisterSpec for Sdtr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr2::R`](R) reader structure"] impl crate :: Readable for Sdtr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr2::W`](W) writer structure"] impl crate :: Writable for Sdtr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR2 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr2Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr2.rs:1:3348 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr2Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge d... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR2` reader"] pub type R = crate :: R < Sdtr2Spec > ; # [doc = "Register `SDTR2` writer"] pub type W = crate :: W < Sdtr2Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr2Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr2Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr2Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr2Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW <'_, Sdtr2Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr2Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr2Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr2Spec ; impl crate :: RegisterSpec for Sdtr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr2::R`](R) reader structure"] impl crate :: Readable for Sdtr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr2::W`](W) writer structure"] impl crate :: Writable for Sdtr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR2 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr2Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr2.rs:1:3487 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr2Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column d... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR2` reader"] pub type R = crate :: R < Sdtr2Spec > ; # [doc = "Register `SDTR2` writer"] pub type W = crate :: W < Sdtr2Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr2Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr2Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr2Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr2Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr2Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW <'_, Sdtr2Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr2Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr2Spec ; impl crate :: RegisterSpec for Sdtr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr2::R`](R) reader structure"] impl crate :: Readable for Sdtr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr2::W`](W) writer structure"] impl crate :: Writable for Sdtr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR2 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr2Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdtr2.rs:1:3627 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn trcd (& mut self) -> TrcdW < Sdtr2Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 2\n... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDTR2` reader"] pub type R = crate :: R < Sdtr2Spec > ; # [doc = "Register `SDTR2` writer"] pub type W = crate :: W < Sdtr2Spec > ; # [doc = "Field `TMRD` reader - Load Mode Register to Active"] pub type TmrdR = crate :: FieldReader ; # [doc = "Field `TMRD` writer - Load Mode Register to Active"] pub type TmrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSR` reader - Exit self-refresh delay"] pub type TxsrR = crate :: FieldReader ; # [doc = "Field `TXSR` writer - Exit self-refresh delay"] pub type TxsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRAS` reader - Self refresh time"] pub type TrasR = crate :: FieldReader ; # [doc = "Field `TRAS` writer - Self refresh time"] pub type TrasW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRC` reader - Row cycle delay"] pub type TrcR = crate :: FieldReader ; # [doc = "Field `TRC` writer - Row cycle delay"] pub type TrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TWR` reader - Recovery delay"] pub type TwrR = crate :: FieldReader ; # [doc = "Field `TWR` writer - Recovery delay"] pub type TwrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRP` reader - Row precharge delay"] pub type TrpR = crate :: FieldReader ; # [doc = "Field `TRP` writer - Row precharge delay"] pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRCD` reader - Row to column delay"] pub type TrcdR = crate :: FieldReader ; # [doc = "Field `TRCD` writer - Row to column delay"] pub type TrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& self) -> TmrdR { TmrdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& self) -> TxsrR { TxsrR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& self) -> TrasR { TrasR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& self) -> TrcR { TrcR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& self) -> TwrR { TwrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& self) -> TrpR { TrpR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& self) -> TrcdR { TrcdR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Load Mode Register to Active"] # [inline (always)] pub fn tmrd (& mut self) -> TmrdW < Sdtr2Spec > { TmrdW :: new (self , 0) } # [doc = "Bits 4:7 - Exit self-refresh delay"] # [inline (always)] pub fn txsr (& mut self) -> TxsrW < Sdtr2Spec > { TxsrW :: new (self , 4) } # [doc = "Bits 8:11 - Self refresh time"] # [inline (always)] pub fn tras (& mut self) -> TrasW < Sdtr2Spec > { TrasW :: new (self , 8) } # [doc = "Bits 12:15 - Row cycle delay"] # [inline (always)] pub fn trc (& mut self) -> TrcW < Sdtr2Spec > { TrcW :: new (self , 12) } # [doc = "Bits 16:19 - Recovery delay"] # [inline (always)] pub fn twr (& mut self) -> TwrW < Sdtr2Spec > { TwrW :: new (self , 16) } # [doc = "Bits 20:23 - Row precharge delay"] # [inline (always)] pub fn trp (& mut self) -> TrpW < Sdtr2Spec > { TrpW :: new (self , 20) } # [doc = "Bits 24:27 - Row to column delay"] # [inline (always)] pub fn trcd (& mut self) -> TrcdW <'_, Sdtr2Spec > { TrcdW :: new (self , 24) } } # [doc = "SDRAM Timing register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sdtr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdtr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Sdtr2Spec ; impl crate :: RegisterSpec for Sdtr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdtr2::R`](R) reader structure"] impl crate :: Readable for Sdtr2Spec { } # [doc = "`write(|w| ..)` method takes [`sdtr2::W`](W) writer structure"] impl crate :: Writable for Sdtr2Spec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDTR2 to value 0x0fff_ffff"] impl crate :: Resettable for Sdtr2Spec { const RESET_VALUE : u32 = 0x0fff_ffff ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcmr.rs:1:1363 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn mode (& mut self) -> ModeW < SdcmrSpec > { ModeW :: new (self , 0) } # [doc = "Bit 3 - Command target bank ... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCMR` reader"] pub type R = crate :: R < SdcmrSpec > ; # [doc = "Register `SDCMR` writer"] pub type W = crate :: W < SdcmrSpec > ; # [doc = "Field `MODE` writer - Command mode"] pub type ModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CTB2` writer - Command target bank 2"] pub type Ctb2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTB1` writer - Command target bank 1"] pub type Ctb1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NRFS` reader - Number of Auto-refresh"] pub type NrfsR = crate :: FieldReader ; # [doc = "Field `NRFS` writer - Number of Auto-refresh"] pub type NrfsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `MRD` reader - Mode Register definition"] pub type MrdR = crate :: FieldReader < u16 > ; # [doc = "Field `MRD` writer - Mode Register definition"] pub type MrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bits 5:8 - Number of Auto-refresh"] # [inline (always)] pub fn nrfs (& self) -> NrfsR { NrfsR :: new (((self . bits >> 5) & 0x0f) as u8) } # [doc = "Bits 9:21 - Mode Register definition"] # [inline (always)] pub fn mrd (& self) -> MrdR { MrdR :: new (((self . bits >> 9) & 0x1fff) as u16) } } impl W { # [doc = "Bits 0:2 - Command mode"] # [inline (always)] pub fn mode (& mut self) -> ModeW <'_, SdcmrSpec > { ModeW :: new (self , 0) } # [doc = "Bit 3 - Command target bank 2"] # [inline (always)] pub fn ctb2 (& mut self) -> Ctb2W < SdcmrSpec > { Ctb2W :: new (self , 3) } # [doc = "Bit 4 - Command target bank 1"] # [inline (always)] pub fn ctb1 (& mut self) -> Ctb1W < SdcmrSpec > { Ctb1W :: new (self , 4) } # [doc = "Bits 5:8 - Number of Auto-refresh"] # [inline (always)] pub fn nrfs (& mut self) -> NrfsW < SdcmrSpec > { NrfsW :: new (self , 5) } # [doc = "Bits 9:21 - Mode Register definition"] # [inline (always)] pub fn mrd (& mut self) -> MrdW < SdcmrSpec > { MrdW :: new (self , 9) } } # [doc = "SDRAM Command Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SdcmrSpec ; impl crate :: RegisterSpec for SdcmrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcmr::R`](R) reader structure"] impl crate :: Readable for SdcmrSpec { } # [doc = "`write(|w| ..)` method takes [`sdcmr::W`](W) writer structure"] impl crate :: Writable for SdcmrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCMR to value 0"] impl crate :: Resettable for SdcmrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcmr.rs:1:1501 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn ctb2 (& mut self) -> Ctb2W < SdcmrSpec > { Ctb2W :: new (self , 3) } # [doc = "Bit 4 - Command target bank ... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCMR` reader"] pub type R = crate :: R < SdcmrSpec > ; # [doc = "Register `SDCMR` writer"] pub type W = crate :: W < SdcmrSpec > ; # [doc = "Field `MODE` writer - Command mode"] pub type ModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CTB2` writer - Command target bank 2"] pub type Ctb2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTB1` writer - Command target bank 1"] pub type Ctb1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NRFS` reader - Number of Auto-refresh"] pub type NrfsR = crate :: FieldReader ; # [doc = "Field `NRFS` writer - Number of Auto-refresh"] pub type NrfsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `MRD` reader - Mode Register definition"] pub type MrdR = crate :: FieldReader < u16 > ; # [doc = "Field `MRD` writer - Mode Register definition"] pub type MrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bits 5:8 - Number of Auto-refresh"] # [inline (always)] pub fn nrfs (& self) -> NrfsR { NrfsR :: new (((self . bits >> 5) & 0x0f) as u8) } # [doc = "Bits 9:21 - Mode Register definition"] # [inline (always)] pub fn mrd (& self) -> MrdR { MrdR :: new (((self . bits >> 9) & 0x1fff) as u16) } } impl W { # [doc = "Bits 0:2 - Command mode"] # [inline (always)] pub fn mode (& mut self) -> ModeW < SdcmrSpec > { ModeW :: new (self , 0) } # [doc = "Bit 3 - Command target bank 2"] # [inline (always)] pub fn ctb2 (& mut self) -> Ctb2W <'_, SdcmrSpec > { Ctb2W :: new (self , 3) } # [doc = "Bit 4 - Command target bank 1"] # [inline (always)] pub fn ctb1 (& mut self) -> Ctb1W < SdcmrSpec > { Ctb1W :: new (self , 4) } # [doc = "Bits 5:8 - Number of Auto-refresh"] # [inline (always)] pub fn nrfs (& mut self) -> NrfsW < SdcmrSpec > { NrfsW :: new (self , 5) } # [doc = "Bits 9:21 - Mode Register definition"] # [inline (always)] pub fn mrd (& mut self) -> MrdW < SdcmrSpec > { MrdW :: new (self , 9) } } # [doc = "SDRAM Command Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SdcmrSpec ; impl crate :: RegisterSpec for SdcmrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcmr::R`](R) reader structure"] impl crate :: Readable for SdcmrSpec { } # [doc = "`write(|w| ..)` method takes [`sdcmr::W`](W) writer structure"] impl crate :: Writable for SdcmrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCMR to value 0"] impl crate :: Resettable for SdcmrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcmr.rs:1:1639 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn ctb1 (& mut self) -> Ctb1W < SdcmrSpec > { Ctb1W :: new (self , 4) } # [doc = "Bits 5:8 - Number of Auto-re... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCMR` reader"] pub type R = crate :: R < SdcmrSpec > ; # [doc = "Register `SDCMR` writer"] pub type W = crate :: W < SdcmrSpec > ; # [doc = "Field `MODE` writer - Command mode"] pub type ModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CTB2` writer - Command target bank 2"] pub type Ctb2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTB1` writer - Command target bank 1"] pub type Ctb1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NRFS` reader - Number of Auto-refresh"] pub type NrfsR = crate :: FieldReader ; # [doc = "Field `NRFS` writer - Number of Auto-refresh"] pub type NrfsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `MRD` reader - Mode Register definition"] pub type MrdR = crate :: FieldReader < u16 > ; # [doc = "Field `MRD` writer - Mode Register definition"] pub type MrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bits 5:8 - Number of Auto-refresh"] # [inline (always)] pub fn nrfs (& self) -> NrfsR { NrfsR :: new (((self . bits >> 5) & 0x0f) as u8) } # [doc = "Bits 9:21 - Mode Register definition"] # [inline (always)] pub fn mrd (& self) -> MrdR { MrdR :: new (((self . bits >> 9) & 0x1fff) as u16) } } impl W { # [doc = "Bits 0:2 - Command mode"] # [inline (always)] pub fn mode (& mut self) -> ModeW < SdcmrSpec > { ModeW :: new (self , 0) } # [doc = "Bit 3 - Command target bank 2"] # [inline (always)] pub fn ctb2 (& mut self) -> Ctb2W < SdcmrSpec > { Ctb2W :: new (self , 3) } # [doc = "Bit 4 - Command target bank 1"] # [inline (always)] pub fn ctb1 (& mut self) -> Ctb1W <'_, SdcmrSpec > { Ctb1W :: new (self , 4) } # [doc = "Bits 5:8 - Number of Auto-refresh"] # [inline (always)] pub fn nrfs (& mut self) -> NrfsW < SdcmrSpec > { NrfsW :: new (self , 5) } # [doc = "Bits 9:21 - Mode Register definition"] # [inline (always)] pub fn mrd (& mut self) -> MrdW < SdcmrSpec > { MrdW :: new (self , 9) } } # [doc = "SDRAM Command Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SdcmrSpec ; impl crate :: RegisterSpec for SdcmrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcmr::R`](R) reader structure"] impl crate :: Readable for SdcmrSpec { } # [doc = "`write(|w| ..)` method takes [`sdcmr::W`](W) writer structure"] impl crate :: Writable for SdcmrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCMR to value 0"] impl crate :: Resettable for SdcmrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcmr.rs:1:1781 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn nrfs (& mut self) -> NrfsW < SdcmrSpec > { NrfsW :: new (self , 5) } # [doc = "Bits 9:21 - Mode Register de... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCMR` reader"] pub type R = crate :: R < SdcmrSpec > ; # [doc = "Register `SDCMR` writer"] pub type W = crate :: W < SdcmrSpec > ; # [doc = "Field `MODE` writer - Command mode"] pub type ModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CTB2` writer - Command target bank 2"] pub type Ctb2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTB1` writer - Command target bank 1"] pub type Ctb1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NRFS` reader - Number of Auto-refresh"] pub type NrfsR = crate :: FieldReader ; # [doc = "Field `NRFS` writer - Number of Auto-refresh"] pub type NrfsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `MRD` reader - Mode Register definition"] pub type MrdR = crate :: FieldReader < u16 > ; # [doc = "Field `MRD` writer - Mode Register definition"] pub type MrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bits 5:8 - Number of Auto-refresh"] # [inline (always)] pub fn nrfs (& self) -> NrfsR { NrfsR :: new (((self . bits >> 5) & 0x0f) as u8) } # [doc = "Bits 9:21 - Mode Register definition"] # [inline (always)] pub fn mrd (& self) -> MrdR { MrdR :: new (((self . bits >> 9) & 0x1fff) as u16) } } impl W { # [doc = "Bits 0:2 - Command mode"] # [inline (always)] pub fn mode (& mut self) -> ModeW < SdcmrSpec > { ModeW :: new (self , 0) } # [doc = "Bit 3 - Command target bank 2"] # [inline (always)] pub fn ctb2 (& mut self) -> Ctb2W < SdcmrSpec > { Ctb2W :: new (self , 3) } # [doc = "Bit 4 - Command target bank 1"] # [inline (always)] pub fn ctb1 (& mut self) -> Ctb1W < SdcmrSpec > { Ctb1W :: new (self , 4) } # [doc = "Bits 5:8 - Number of Auto-refresh"] # [inline (always)] pub fn nrfs (& mut self) -> NrfsW <'_, SdcmrSpec > { NrfsW :: new (self , 5) } # [doc = "Bits 9:21 - Mode Register definition"] # [inline (always)] pub fn mrd (& mut self) -> MrdW < SdcmrSpec > { MrdW :: new (self , 9) } } # [doc = "SDRAM Command Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SdcmrSpec ; impl crate :: RegisterSpec for SdcmrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcmr::R`](R) reader structure"] impl crate :: Readable for SdcmrSpec { } # [doc = "`write(|w| ..)` method takes [`sdcmr::W`](W) writer structure"] impl crate :: Writable for SdcmrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCMR to value 0"] impl crate :: Resettable for SdcmrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdcmr.rs:1:1925 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn mrd (& mut self) -> MrdW < SdcmrSpec > { MrdW :: new (self , 9) } } # [doc = "SDRAM Command Mode register... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDCMR` reader"] pub type R = crate :: R < SdcmrSpec > ; # [doc = "Register `SDCMR` writer"] pub type W = crate :: W < SdcmrSpec > ; # [doc = "Field `MODE` writer - Command mode"] pub type ModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CTB2` writer - Command target bank 2"] pub type Ctb2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTB1` writer - Command target bank 1"] pub type Ctb1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NRFS` reader - Number of Auto-refresh"] pub type NrfsR = crate :: FieldReader ; # [doc = "Field `NRFS` writer - Number of Auto-refresh"] pub type NrfsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `MRD` reader - Mode Register definition"] pub type MrdR = crate :: FieldReader < u16 > ; # [doc = "Field `MRD` writer - Mode Register definition"] pub type MrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bits 5:8 - Number of Auto-refresh"] # [inline (always)] pub fn nrfs (& self) -> NrfsR { NrfsR :: new (((self . bits >> 5) & 0x0f) as u8) } # [doc = "Bits 9:21 - Mode Register definition"] # [inline (always)] pub fn mrd (& self) -> MrdR { MrdR :: new (((self . bits >> 9) & 0x1fff) as u16) } } impl W { # [doc = "Bits 0:2 - Command mode"] # [inline (always)] pub fn mode (& mut self) -> ModeW < SdcmrSpec > { ModeW :: new (self , 0) } # [doc = "Bit 3 - Command target bank 2"] # [inline (always)] pub fn ctb2 (& mut self) -> Ctb2W < SdcmrSpec > { Ctb2W :: new (self , 3) } # [doc = "Bit 4 - Command target bank 1"] # [inline (always)] pub fn ctb1 (& mut self) -> Ctb1W < SdcmrSpec > { Ctb1W :: new (self , 4) } # [doc = "Bits 5:8 - Number of Auto-refresh"] # [inline (always)] pub fn nrfs (& mut self) -> NrfsW < SdcmrSpec > { NrfsW :: new (self , 5) } # [doc = "Bits 9:21 - Mode Register definition"] # [inline (always)] pub fn mrd (& mut self) -> MrdW <'_, SdcmrSpec > { MrdW :: new (self , 9) } } # [doc = "SDRAM Command Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdcmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SdcmrSpec ; impl crate :: RegisterSpec for SdcmrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdcmr::R`](R) reader structure"] impl crate :: Readable for SdcmrSpec { } # [doc = "`write(|w| ..)` method takes [`sdcmr::W`](W) writer structure"] impl crate :: Writable for SdcmrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDCMR to value 0"] impl crate :: Resettable for SdcmrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdrtr.rs:1:1115 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn cre (& mut self) -> CreW < SdrtrSpec > { CreW :: new (self , 0) } # [doc = "Bits 1:13 - Refresh Timer Cou... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDRTR` reader"] pub type R = crate :: R < SdrtrSpec > ; # [doc = "Register `SDRTR` writer"] pub type W = crate :: W < SdrtrSpec > ; # [doc = "Field `CRE` writer - Clear Refresh error flag"] pub type CreW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `COUNT` reader - Refresh Timer Count"] pub type CountR = crate :: FieldReader < u16 > ; # [doc = "Field `COUNT` writer - Refresh Timer Count"] pub type CountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; # [doc = "Field `REIE` reader - RES Interrupt Enable"] pub type ReieR = crate :: BitReader ; # [doc = "Field `REIE` writer - RES Interrupt Enable"] pub type ReieW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 1:13 - Refresh Timer Count"] # [inline (always)] pub fn count (& self) -> CountR { CountR :: new (((self . bits >> 1) & 0x1fff) as u16) } # [doc = "Bit 14 - RES Interrupt Enable"] # [inline (always)] pub fn reie (& self) -> ReieR { ReieR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Clear Refresh error flag"] # [inline (always)] pub fn cre (& mut self) -> CreW <'_, SdrtrSpec > { CreW :: new (self , 0) } # [doc = "Bits 1:13 - Refresh Timer Count"] # [inline (always)] pub fn count (& mut self) -> CountW < SdrtrSpec > { CountW :: new (self , 1) } # [doc = "Bit 14 - RES Interrupt Enable"] # [inline (always)] pub fn reie (& mut self) -> ReieW < SdrtrSpec > { ReieW :: new (self , 14) } } # [doc = "SDRAM Refresh Timer register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdrtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdrtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SdrtrSpec ; impl crate :: RegisterSpec for SdrtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdrtr::R`](R) reader structure"] impl crate :: Readable for SdrtrSpec { } # [doc = "`write(|w| ..)` method takes [`sdrtr::W`](W) writer structure"] impl crate :: Writable for SdrtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDRTR to value 0"] impl crate :: Resettable for SdrtrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdrtr.rs:1:1254 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn count (& mut self) -> CountW < SdrtrSpec > { CountW :: new (self , 1) } # [doc = "Bit 14 - RES Interrupt Ena... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDRTR` reader"] pub type R = crate :: R < SdrtrSpec > ; # [doc = "Register `SDRTR` writer"] pub type W = crate :: W < SdrtrSpec > ; # [doc = "Field `CRE` writer - Clear Refresh error flag"] pub type CreW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `COUNT` reader - Refresh Timer Count"] pub type CountR = crate :: FieldReader < u16 > ; # [doc = "Field `COUNT` writer - Refresh Timer Count"] pub type CountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; # [doc = "Field `REIE` reader - RES Interrupt Enable"] pub type ReieR = crate :: BitReader ; # [doc = "Field `REIE` writer - RES Interrupt Enable"] pub type ReieW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 1:13 - Refresh Timer Count"] # [inline (always)] pub fn count (& self) -> CountR { CountR :: new (((self . bits >> 1) & 0x1fff) as u16) } # [doc = "Bit 14 - RES Interrupt Enable"] # [inline (always)] pub fn reie (& self) -> ReieR { ReieR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Clear Refresh error flag"] # [inline (always)] pub fn cre (& mut self) -> CreW < SdrtrSpec > { CreW :: new (self , 0) } # [doc = "Bits 1:13 - Refresh Timer Count"] # [inline (always)] pub fn count (& mut self) -> CountW <'_, SdrtrSpec > { CountW :: new (self , 1) } # [doc = "Bit 14 - RES Interrupt Enable"] # [inline (always)] pub fn reie (& mut self) -> ReieW < SdrtrSpec > { ReieW :: new (self , 14) } } # [doc = "SDRAM Refresh Timer register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdrtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdrtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SdrtrSpec ; impl crate :: RegisterSpec for SdrtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdrtr::R`](R) reader structure"] impl crate :: Readable for SdrtrSpec { } # [doc = "`write(|w| ..)` method takes [`sdrtr::W`](W) writer structure"] impl crate :: Writable for SdrtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDRTR to value 0"] impl crate :: Resettable for SdrtrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/fsmc/sdrtr.rs:1:1394 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn reie (& mut self) -> ReieW < SdrtrSpec > { ReieW :: new (self , 14) } } # [doc = "SDRAM Refresh Timer regis... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SDRTR` reader"] pub type R = crate :: R < SdrtrSpec > ; # [doc = "Register `SDRTR` writer"] pub type W = crate :: W < SdrtrSpec > ; # [doc = "Field `CRE` writer - Clear Refresh error flag"] pub type CreW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `COUNT` reader - Refresh Timer Count"] pub type CountR = crate :: FieldReader < u16 > ; # [doc = "Field `COUNT` writer - Refresh Timer Count"] pub type CountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; # [doc = "Field `REIE` reader - RES Interrupt Enable"] pub type ReieR = crate :: BitReader ; # [doc = "Field `REIE` writer - RES Interrupt Enable"] pub type ReieW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 1:13 - Refresh Timer Count"] # [inline (always)] pub fn count (& self) -> CountR { CountR :: new (((self . bits >> 1) & 0x1fff) as u16) } # [doc = "Bit 14 - RES Interrupt Enable"] # [inline (always)] pub fn reie (& self) -> ReieR { ReieR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Clear Refresh error flag"] # [inline (always)] pub fn cre (& mut self) -> CreW < SdrtrSpec > { CreW :: new (self , 0) } # [doc = "Bits 1:13 - Refresh Timer Count"] # [inline (always)] pub fn count (& mut self) -> CountW < SdrtrSpec > { CountW :: new (self , 1) } # [doc = "Bit 14 - RES Interrupt Enable"] # [inline (always)] pub fn reie (& mut self) -> ReieW <'_, SdrtrSpec > { ReieW :: new (self , 14) } } # [doc = "SDRAM Refresh Timer register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdrtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdrtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SdrtrSpec ; impl crate :: RegisterSpec for SdrtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sdrtr::R`](R) reader structure"] impl crate :: Readable for SdrtrSpec { } # [doc = "`write(|w| ..)` method takes [`sdrtr::W`](W) writer structure"] impl crate :: Writable for SdrtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SDRTR to value 0"] impl crate :: Resettable for SdrtrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/cr.rs:1:4040 [INFO] [stdout] | [INFO] [stdout] 1 | ...line (always)] pub fn dbg_sleep (& mut self) -> DbgSleepW < CrSpec > { DbgSleepW :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"] # [i... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"] pub type DbgSleepR = crate :: BitReader ; # [doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"] pub type DbgSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STOP` reader - DBG_STOP"] pub type DbgStopR = crate :: BitReader ; # [doc = "Field `DBG_STOP` writer - DBG_STOP"] pub type DbgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"] pub type DbgStandbyR = crate :: BitReader ; # [doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"] pub type DbgStandbyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_IOEN` reader - TRACE_IOEN"] pub type TraceIoenR = crate :: BitReader ; # [doc = "Field `TRACE_IOEN` writer - TRACE_IOEN"] pub type TraceIoenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_MODE` reader - TRACE_MODE"] pub type TraceModeR = crate :: FieldReader ; # [doc = "Field `TRACE_MODE` writer - TRACE_MODE"] pub type TraceModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - DBG_TIM8_STOP"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - DBG_TIM8_STOP"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& self) -> DbgSleepR { DbgSleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& self) -> DbgStopR { DbgStopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& self) -> DbgStandbyR { DbgStandbyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& self) -> TraceIoenR { TraceIoenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& self) -> TraceModeR { TraceModeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& self) -> DbgI2c2SmbusTimeoutR { DbgI2c2SmbusTimeoutR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& mut self) -> DbgSleepW <'_, CrSpec > { DbgSleepW :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& mut self) -> DbgStopW < CrSpec > { DbgStopW :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& mut self) -> DbgStandbyW < CrSpec > { DbgStandbyW :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& mut self) -> TraceIoenW < CrSpec > { TraceIoenW :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& mut self) -> TraceModeW < CrSpec > { TraceModeW :: new (self , 6) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& mut self) -> DbgI2c2SmbusTimeoutW < CrSpec > { DbgI2c2SmbusTimeoutW :: new (self , 16) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < CrSpec > { DbgTim8StopW :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < CrSpec > { DbgTim5StopW :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < CrSpec > { DbgTim6StopW :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < CrSpec > { DbgTim7StopW :: new (self , 20) } } # [doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/cr.rs:1:4174 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn dbg_stop (& mut self) -> DbgStopW < CrSpec > { DbgStopW :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"] # [... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"] pub type DbgSleepR = crate :: BitReader ; # [doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"] pub type DbgSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STOP` reader - DBG_STOP"] pub type DbgStopR = crate :: BitReader ; # [doc = "Field `DBG_STOP` writer - DBG_STOP"] pub type DbgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"] pub type DbgStandbyR = crate :: BitReader ; # [doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"] pub type DbgStandbyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_IOEN` reader - TRACE_IOEN"] pub type TraceIoenR = crate :: BitReader ; # [doc = "Field `TRACE_IOEN` writer - TRACE_IOEN"] pub type TraceIoenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_MODE` reader - TRACE_MODE"] pub type TraceModeR = crate :: FieldReader ; # [doc = "Field `TRACE_MODE` writer - TRACE_MODE"] pub type TraceModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - DBG_TIM8_STOP"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - DBG_TIM8_STOP"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& self) -> DbgSleepR { DbgSleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& self) -> DbgStopR { DbgStopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& self) -> DbgStandbyR { DbgStandbyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& self) -> TraceIoenR { TraceIoenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& self) -> TraceModeR { TraceModeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& self) -> DbgI2c2SmbusTimeoutR { DbgI2c2SmbusTimeoutR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& mut self) -> DbgSleepW < CrSpec > { DbgSleepW :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& mut self) -> DbgStopW <'_, CrSpec > { DbgStopW :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& mut self) -> DbgStandbyW < CrSpec > { DbgStandbyW :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& mut self) -> TraceIoenW < CrSpec > { TraceIoenW :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& mut self) -> TraceModeW < CrSpec > { TraceModeW :: new (self , 6) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& mut self) -> DbgI2c2SmbusTimeoutW < CrSpec > { DbgI2c2SmbusTimeoutW :: new (self , 16) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < CrSpec > { DbgTim8StopW :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < CrSpec > { DbgTim5StopW :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < CrSpec > { DbgTim6StopW :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < CrSpec > { DbgTim7StopW :: new (self , 20) } } # [doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/cr.rs:1:4312 [INFO] [stdout] | [INFO] [stdout] 1 | ...e (always)] pub fn dbg_standby (& mut self) -> DbgStandbyW < CrSpec > { DbgStandbyW :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"]... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"] pub type DbgSleepR = crate :: BitReader ; # [doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"] pub type DbgSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STOP` reader - DBG_STOP"] pub type DbgStopR = crate :: BitReader ; # [doc = "Field `DBG_STOP` writer - DBG_STOP"] pub type DbgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"] pub type DbgStandbyR = crate :: BitReader ; # [doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"] pub type DbgStandbyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_IOEN` reader - TRACE_IOEN"] pub type TraceIoenR = crate :: BitReader ; # [doc = "Field `TRACE_IOEN` writer - TRACE_IOEN"] pub type TraceIoenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_MODE` reader - TRACE_MODE"] pub type TraceModeR = crate :: FieldReader ; # [doc = "Field `TRACE_MODE` writer - TRACE_MODE"] pub type TraceModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - DBG_TIM8_STOP"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - DBG_TIM8_STOP"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& self) -> DbgSleepR { DbgSleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& self) -> DbgStopR { DbgStopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& self) -> DbgStandbyR { DbgStandbyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& self) -> TraceIoenR { TraceIoenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& self) -> TraceModeR { TraceModeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& self) -> DbgI2c2SmbusTimeoutR { DbgI2c2SmbusTimeoutR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& mut self) -> DbgSleepW < CrSpec > { DbgSleepW :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& mut self) -> DbgStopW < CrSpec > { DbgStopW :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& mut self) -> DbgStandbyW <'_, CrSpec > { DbgStandbyW :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& mut self) -> TraceIoenW < CrSpec > { TraceIoenW :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& mut self) -> TraceModeW < CrSpec > { TraceModeW :: new (self , 6) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& mut self) -> DbgI2c2SmbusTimeoutW < CrSpec > { DbgI2c2SmbusTimeoutW :: new (self , 16) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < CrSpec > { DbgTim8StopW :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < CrSpec > { DbgTim5StopW :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < CrSpec > { DbgTim6StopW :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < CrSpec > { DbgTim7StopW :: new (self , 20) } } # [doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/cr.rs:1:4454 [INFO] [stdout] | [INFO] [stdout] 1 | ...ne (always)] pub fn trace_ioen (& mut self) -> TraceIoenW < CrSpec > { TraceIoenW :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"] pub type DbgSleepR = crate :: BitReader ; # [doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"] pub type DbgSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STOP` reader - DBG_STOP"] pub type DbgStopR = crate :: BitReader ; # [doc = "Field `DBG_STOP` writer - DBG_STOP"] pub type DbgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"] pub type DbgStandbyR = crate :: BitReader ; # [doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"] pub type DbgStandbyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_IOEN` reader - TRACE_IOEN"] pub type TraceIoenR = crate :: BitReader ; # [doc = "Field `TRACE_IOEN` writer - TRACE_IOEN"] pub type TraceIoenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_MODE` reader - TRACE_MODE"] pub type TraceModeR = crate :: FieldReader ; # [doc = "Field `TRACE_MODE` writer - TRACE_MODE"] pub type TraceModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - DBG_TIM8_STOP"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - DBG_TIM8_STOP"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& self) -> DbgSleepR { DbgSleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& self) -> DbgStopR { DbgStopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& self) -> DbgStandbyR { DbgStandbyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& self) -> TraceIoenR { TraceIoenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& self) -> TraceModeR { TraceModeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& self) -> DbgI2c2SmbusTimeoutR { DbgI2c2SmbusTimeoutR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& mut self) -> DbgSleepW < CrSpec > { DbgSleepW :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& mut self) -> DbgStopW < CrSpec > { DbgStopW :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& mut self) -> DbgStandbyW < CrSpec > { DbgStandbyW :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& mut self) -> TraceIoenW <'_, CrSpec > { TraceIoenW :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& mut self) -> TraceModeW < CrSpec > { TraceModeW :: new (self , 6) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& mut self) -> DbgI2c2SmbusTimeoutW < CrSpec > { DbgI2c2SmbusTimeoutW :: new (self , 16) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < CrSpec > { DbgTim8StopW :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < CrSpec > { DbgTim5StopW :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < CrSpec > { DbgTim6StopW :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < CrSpec > { DbgTim7StopW :: new (self , 20) } } # [doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/cr.rs:1:4597 [INFO] [stdout] | [INFO] [stdout] 1 | ...ne (always)] pub fn trace_mode (& mut self) -> TraceModeW < CrSpec > { TraceModeW :: new (self , 6) } # [doc = "Bit 16 - DBG_I2C2_SMBU... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"] pub type DbgSleepR = crate :: BitReader ; # [doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"] pub type DbgSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STOP` reader - DBG_STOP"] pub type DbgStopR = crate :: BitReader ; # [doc = "Field `DBG_STOP` writer - DBG_STOP"] pub type DbgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"] pub type DbgStandbyR = crate :: BitReader ; # [doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"] pub type DbgStandbyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_IOEN` reader - TRACE_IOEN"] pub type TraceIoenR = crate :: BitReader ; # [doc = "Field `TRACE_IOEN` writer - TRACE_IOEN"] pub type TraceIoenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_MODE` reader - TRACE_MODE"] pub type TraceModeR = crate :: FieldReader ; # [doc = "Field `TRACE_MODE` writer - TRACE_MODE"] pub type TraceModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - DBG_TIM8_STOP"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - DBG_TIM8_STOP"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& self) -> DbgSleepR { DbgSleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& self) -> DbgStopR { DbgStopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& self) -> DbgStandbyR { DbgStandbyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& self) -> TraceIoenR { TraceIoenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& self) -> TraceModeR { TraceModeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& self) -> DbgI2c2SmbusTimeoutR { DbgI2c2SmbusTimeoutR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& mut self) -> DbgSleepW < CrSpec > { DbgSleepW :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& mut self) -> DbgStopW < CrSpec > { DbgStopW :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& mut self) -> DbgStandbyW < CrSpec > { DbgStandbyW :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& mut self) -> TraceIoenW < CrSpec > { TraceIoenW :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& mut self) -> TraceModeW <'_, CrSpec > { TraceModeW :: new (self , 6) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& mut self) -> DbgI2c2SmbusTimeoutW < CrSpec > { DbgI2c2SmbusTimeoutW :: new (self , 16) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < CrSpec > { DbgTim8StopW :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < CrSpec > { DbgTim5StopW :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < CrSpec > { DbgTim6StopW :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < CrSpec > { DbgTim7StopW :: new (self , 20) } } # [doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/cr.rs:1:4762 [INFO] [stdout] | [INFO] [stdout] 1 | ...fn dbg_i2c2_smbus_timeout (& mut self) -> DbgI2c2SmbusTimeoutW < CrSpec > { DbgI2c2SmbusTimeoutW :: new (self , 16) } # [doc = "Bit 17... [INFO] [stdout] | ^^^^^^^^^^ ------------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"] pub type DbgSleepR = crate :: BitReader ; # [doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"] pub type DbgSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STOP` reader - DBG_STOP"] pub type DbgStopR = crate :: BitReader ; # [doc = "Field `DBG_STOP` writer - DBG_STOP"] pub type DbgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"] pub type DbgStandbyR = crate :: BitReader ; # [doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"] pub type DbgStandbyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_IOEN` reader - TRACE_IOEN"] pub type TraceIoenR = crate :: BitReader ; # [doc = "Field `TRACE_IOEN` writer - TRACE_IOEN"] pub type TraceIoenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_MODE` reader - TRACE_MODE"] pub type TraceModeR = crate :: FieldReader ; # [doc = "Field `TRACE_MODE` writer - TRACE_MODE"] pub type TraceModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - DBG_TIM8_STOP"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - DBG_TIM8_STOP"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& self) -> DbgSleepR { DbgSleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& self) -> DbgStopR { DbgStopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& self) -> DbgStandbyR { DbgStandbyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& self) -> TraceIoenR { TraceIoenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& self) -> TraceModeR { TraceModeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& self) -> DbgI2c2SmbusTimeoutR { DbgI2c2SmbusTimeoutR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& mut self) -> DbgSleepW < CrSpec > { DbgSleepW :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& mut self) -> DbgStopW < CrSpec > { DbgStopW :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& mut self) -> DbgStandbyW < CrSpec > { DbgStandbyW :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& mut self) -> TraceIoenW < CrSpec > { TraceIoenW :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& mut self) -> TraceModeW < CrSpec > { TraceModeW :: new (self , 6) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& mut self) -> DbgI2c2SmbusTimeoutW <'_, CrSpec > { DbgI2c2SmbusTimeoutW :: new (self , 16) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < CrSpec > { DbgTim8StopW :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < CrSpec > { DbgTim5StopW :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < CrSpec > { DbgTim6StopW :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < CrSpec > { DbgTim7StopW :: new (self , 20) } } # [doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/cr.rs:1:4930 [INFO] [stdout] | [INFO] [stdout] 1 | ...always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < CrSpec > { DbgTim8StopW :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_... [INFO] [stdout] | ^^^^^^^^^^ ----------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"] pub type DbgSleepR = crate :: BitReader ; # [doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"] pub type DbgSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STOP` reader - DBG_STOP"] pub type DbgStopR = crate :: BitReader ; # [doc = "Field `DBG_STOP` writer - DBG_STOP"] pub type DbgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"] pub type DbgStandbyR = crate :: BitReader ; # [doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"] pub type DbgStandbyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_IOEN` reader - TRACE_IOEN"] pub type TraceIoenR = crate :: BitReader ; # [doc = "Field `TRACE_IOEN` writer - TRACE_IOEN"] pub type TraceIoenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_MODE` reader - TRACE_MODE"] pub type TraceModeR = crate :: FieldReader ; # [doc = "Field `TRACE_MODE` writer - TRACE_MODE"] pub type TraceModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - DBG_TIM8_STOP"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - DBG_TIM8_STOP"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& self) -> DbgSleepR { DbgSleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& self) -> DbgStopR { DbgStopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& self) -> DbgStandbyR { DbgStandbyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& self) -> TraceIoenR { TraceIoenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& self) -> TraceModeR { TraceModeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& self) -> DbgI2c2SmbusTimeoutR { DbgI2c2SmbusTimeoutR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& mut self) -> DbgSleepW < CrSpec > { DbgSleepW :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& mut self) -> DbgStopW < CrSpec > { DbgStopW :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& mut self) -> DbgStandbyW < CrSpec > { DbgStandbyW :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& mut self) -> TraceIoenW < CrSpec > { TraceIoenW :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& mut self) -> TraceModeW < CrSpec > { TraceModeW :: new (self , 6) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& mut self) -> DbgI2c2SmbusTimeoutW < CrSpec > { DbgI2c2SmbusTimeoutW :: new (self , 16) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW <'_, CrSpec > { DbgTim8StopW :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < CrSpec > { DbgTim5StopW :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < CrSpec > { DbgTim6StopW :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < CrSpec > { DbgTim7StopW :: new (self , 20) } } # [doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/cr.rs:1:5082 [INFO] [stdout] | [INFO] [stdout] 1 | ...always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < CrSpec > { DbgTim5StopW :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_... [INFO] [stdout] | ^^^^^^^^^^ ----------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"] pub type DbgSleepR = crate :: BitReader ; # [doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"] pub type DbgSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STOP` reader - DBG_STOP"] pub type DbgStopR = crate :: BitReader ; # [doc = "Field `DBG_STOP` writer - DBG_STOP"] pub type DbgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"] pub type DbgStandbyR = crate :: BitReader ; # [doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"] pub type DbgStandbyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_IOEN` reader - TRACE_IOEN"] pub type TraceIoenR = crate :: BitReader ; # [doc = "Field `TRACE_IOEN` writer - TRACE_IOEN"] pub type TraceIoenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_MODE` reader - TRACE_MODE"] pub type TraceModeR = crate :: FieldReader ; # [doc = "Field `TRACE_MODE` writer - TRACE_MODE"] pub type TraceModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - DBG_TIM8_STOP"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - DBG_TIM8_STOP"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& self) -> DbgSleepR { DbgSleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& self) -> DbgStopR { DbgStopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& self) -> DbgStandbyR { DbgStandbyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& self) -> TraceIoenR { TraceIoenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& self) -> TraceModeR { TraceModeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& self) -> DbgI2c2SmbusTimeoutR { DbgI2c2SmbusTimeoutR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& mut self) -> DbgSleepW < CrSpec > { DbgSleepW :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& mut self) -> DbgStopW < CrSpec > { DbgStopW :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& mut self) -> DbgStandbyW < CrSpec > { DbgStandbyW :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& mut self) -> TraceIoenW < CrSpec > { TraceIoenW :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& mut self) -> TraceModeW < CrSpec > { TraceModeW :: new (self , 6) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& mut self) -> DbgI2c2SmbusTimeoutW < CrSpec > { DbgI2c2SmbusTimeoutW :: new (self , 16) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < CrSpec > { DbgTim8StopW :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW <'_, CrSpec > { DbgTim5StopW :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < CrSpec > { DbgTim6StopW :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < CrSpec > { DbgTim7StopW :: new (self , 20) } } # [doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/cr.rs:1:5234 [INFO] [stdout] | [INFO] [stdout] 1 | ...always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < CrSpec > { DbgTim6StopW :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_... [INFO] [stdout] | ^^^^^^^^^^ ----------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"] pub type DbgSleepR = crate :: BitReader ; # [doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"] pub type DbgSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STOP` reader - DBG_STOP"] pub type DbgStopR = crate :: BitReader ; # [doc = "Field `DBG_STOP` writer - DBG_STOP"] pub type DbgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"] pub type DbgStandbyR = crate :: BitReader ; # [doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"] pub type DbgStandbyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_IOEN` reader - TRACE_IOEN"] pub type TraceIoenR = crate :: BitReader ; # [doc = "Field `TRACE_IOEN` writer - TRACE_IOEN"] pub type TraceIoenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_MODE` reader - TRACE_MODE"] pub type TraceModeR = crate :: FieldReader ; # [doc = "Field `TRACE_MODE` writer - TRACE_MODE"] pub type TraceModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - DBG_TIM8_STOP"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - DBG_TIM8_STOP"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& self) -> DbgSleepR { DbgSleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& self) -> DbgStopR { DbgStopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& self) -> DbgStandbyR { DbgStandbyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& self) -> TraceIoenR { TraceIoenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& self) -> TraceModeR { TraceModeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& self) -> DbgI2c2SmbusTimeoutR { DbgI2c2SmbusTimeoutR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& mut self) -> DbgSleepW < CrSpec > { DbgSleepW :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& mut self) -> DbgStopW < CrSpec > { DbgStopW :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& mut self) -> DbgStandbyW < CrSpec > { DbgStandbyW :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& mut self) -> TraceIoenW < CrSpec > { TraceIoenW :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& mut self) -> TraceModeW < CrSpec > { TraceModeW :: new (self , 6) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& mut self) -> DbgI2c2SmbusTimeoutW < CrSpec > { DbgI2c2SmbusTimeoutW :: new (self , 16) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < CrSpec > { DbgTim8StopW :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < CrSpec > { DbgTim5StopW :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW <'_, CrSpec > { DbgTim6StopW :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < CrSpec > { DbgTim7StopW :: new (self , 20) } } # [doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/cr.rs:1:5386 [INFO] [stdout] | [INFO] [stdout] 1 | ...always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < CrSpec > { DbgTim7StopW :: new (self , 20) } } # [doc = "Control Register... [INFO] [stdout] | ^^^^^^^^^^ ----------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"] pub type DbgSleepR = crate :: BitReader ; # [doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"] pub type DbgSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STOP` reader - DBG_STOP"] pub type DbgStopR = crate :: BitReader ; # [doc = "Field `DBG_STOP` writer - DBG_STOP"] pub type DbgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"] pub type DbgStandbyR = crate :: BitReader ; # [doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"] pub type DbgStandbyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_IOEN` reader - TRACE_IOEN"] pub type TraceIoenR = crate :: BitReader ; # [doc = "Field `TRACE_IOEN` writer - TRACE_IOEN"] pub type TraceIoenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_MODE` reader - TRACE_MODE"] pub type TraceModeR = crate :: FieldReader ; # [doc = "Field `TRACE_MODE` writer - TRACE_MODE"] pub type TraceModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT"] pub type DbgI2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - DBG_TIM8_STOP"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - DBG_TIM8_STOP"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& self) -> DbgSleepR { DbgSleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& self) -> DbgStopR { DbgStopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& self) -> DbgStandbyR { DbgStandbyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& self) -> TraceIoenR { TraceIoenR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& self) -> TraceModeR { TraceModeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& self) -> DbgI2c2SmbusTimeoutR { DbgI2c2SmbusTimeoutR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_SLEEP"] # [inline (always)] pub fn dbg_sleep (& mut self) -> DbgSleepW < CrSpec > { DbgSleepW :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"] # [inline (always)] pub fn dbg_stop (& mut self) -> DbgStopW < CrSpec > { DbgStopW :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"] # [inline (always)] pub fn dbg_standby (& mut self) -> DbgStandbyW < CrSpec > { DbgStandbyW :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"] # [inline (always)] pub fn trace_ioen (& mut self) -> TraceIoenW < CrSpec > { TraceIoenW :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"] # [inline (always)] pub fn trace_mode (& mut self) -> TraceModeW < CrSpec > { TraceModeW :: new (self , 6) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_i2c2_smbus_timeout (& mut self) -> DbgI2c2SmbusTimeoutW < CrSpec > { DbgI2c2SmbusTimeoutW :: new (self , 16) } # [doc = "Bit 17 - DBG_TIM8_STOP"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < CrSpec > { DbgTim8StopW :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < CrSpec > { DbgTim5StopW :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < CrSpec > { DbgTim6StopW :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW <'_, CrSpec > { DbgTim7StopW :: new (self , 20) } } # [doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:6726 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 ... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW <'_, Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:6881 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW <'_, Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:7035 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW <'_, Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:7189 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW <'_, Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:7343 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW <'_, Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:7497 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW <'_, Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:7653 [INFO] [stdout] | [INFO] [stdout] 1 | ...ays)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM... [INFO] [stdout] | ^^^^^^^^^^ ---------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW <'_, Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:7811 [INFO] [stdout] | [INFO] [stdout] 1 | ...ays)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM... [INFO] [stdout] | ^^^^^^^^^^ ---------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW <'_, Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:7969 [INFO] [stdout] | [INFO] [stdout] 1 | ...ays)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WW... [INFO] [stdout] | ^^^^^^^^^^ ---------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW <'_, Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:8126 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWD... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW <'_, Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:8283 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW <'_, Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:8457 [INFO] [stdout] | [INFO] [stdout] 1 | ... dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit ... [INFO] [stdout] | ^^^^^^^^^^ ----------------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW <'_, Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:8647 [INFO] [stdout] | [INFO] [stdout] 1 | ... dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit ... [INFO] [stdout] | ^^^^^^^^^^ ----------------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW <'_, Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:8835 [INFO] [stdout] | [INFO] [stdout] 1 | ...n dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit ... [INFO] [stdout] | ^^^^^^^^^^ ----------------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW <'_, Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:9007 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW <'_, Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb1_fz.rs:1:9163 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW < Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB1_FZ` reader"] pub type R = crate :: R < Apb1FzSpec > ; # [doc = "Register `APB1_FZ` writer"] pub type W = crate :: W < Apb1FzSpec > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"] pub type DbgTim2StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"] pub type DbgTim2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP"] pub type DbgTim3StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP"] pub type DbgTim3StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"] pub type DbgTim4StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"] pub type DbgTim4StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"] pub type DbgTim5StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"] pub type DbgTim5StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"] pub type DbgTim6StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"] pub type DbgTim6StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"] pub type DbgTim7StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"] pub type DbgTim7StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP"] pub type DbgTim12StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP"] pub type DbgTim12StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP"] pub type DbgTim13StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP"] pub type DbgTim13StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP"] pub type DbgTim14StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP"] pub type DbgTim14StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"] pub type DbgWwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"] pub type DbgWwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP"] pub type DbgIwdgStopR = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP"] pub type DbgIwdgStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT"] pub type DbgJ2c1SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT"] pub type DbgJ2c2SmbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutR = crate :: BitReader ; # [doc = "Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT"] pub type DbgJ2c3smbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"] pub type DbgCan1StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"] pub type DbgCan1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"] pub type DbgCan2StopR = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"] pub type DbgCan2StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& self) -> DbgTim2StopR { DbgTim2StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& self) -> DbgTim3StopR { DbgTim3StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& self) -> DbgTim4StopR { DbgTim4StopR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& self) -> DbgTim5StopR { DbgTim5StopR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& self) -> DbgTim6StopR { DbgTim6StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& self) -> DbgTim7StopR { DbgTim7StopR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& self) -> DbgTim12StopR { DbgTim12StopR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& self) -> DbgTim13StopR { DbgTim13StopR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& self) -> DbgTim14StopR { DbgTim14StopR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& self) -> DbgWwdgStopR { DbgWwdgStopR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& self) -> DbgIwdgStopR { DbgIwdgStopR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& self) -> DbgJ2c1SmbusTimeoutR { DbgJ2c1SmbusTimeoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& self) -> DbgJ2c2SmbusTimeoutR { DbgJ2c2SmbusTimeoutR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& self) -> DbgJ2c3smbusTimeoutR { DbgJ2c3smbusTimeoutR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& self) -> DbgCan1StopR { DbgCan1StopR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& self) -> DbgCan2StopR { DbgCan2StopR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_TIM2_STOP"] # [inline (always)] pub fn dbg_tim2_stop (& mut self) -> DbgTim2StopW < Apb1FzSpec > { DbgTim2StopW :: new (self , 0) } # [doc = "Bit 1 - DBG_TIM3 _STOP"] # [inline (always)] pub fn dbg_tim3_stop (& mut self) -> DbgTim3StopW < Apb1FzSpec > { DbgTim3StopW :: new (self , 1) } # [doc = "Bit 2 - DBG_TIM4_STOP"] # [inline (always)] pub fn dbg_tim4_stop (& mut self) -> DbgTim4StopW < Apb1FzSpec > { DbgTim4StopW :: new (self , 2) } # [doc = "Bit 3 - DBG_TIM5_STOP"] # [inline (always)] pub fn dbg_tim5_stop (& mut self) -> DbgTim5StopW < Apb1FzSpec > { DbgTim5StopW :: new (self , 3) } # [doc = "Bit 4 - DBG_TIM6_STOP"] # [inline (always)] pub fn dbg_tim6_stop (& mut self) -> DbgTim6StopW < Apb1FzSpec > { DbgTim6StopW :: new (self , 4) } # [doc = "Bit 5 - DBG_TIM7_STOP"] # [inline (always)] pub fn dbg_tim7_stop (& mut self) -> DbgTim7StopW < Apb1FzSpec > { DbgTim7StopW :: new (self , 5) } # [doc = "Bit 6 - DBG_TIM12_STOP"] # [inline (always)] pub fn dbg_tim12_stop (& mut self) -> DbgTim12StopW < Apb1FzSpec > { DbgTim12StopW :: new (self , 6) } # [doc = "Bit 7 - DBG_TIM13_STOP"] # [inline (always)] pub fn dbg_tim13_stop (& mut self) -> DbgTim13StopW < Apb1FzSpec > { DbgTim13StopW :: new (self , 7) } # [doc = "Bit 8 - DBG_TIM14_STOP"] # [inline (always)] pub fn dbg_tim14_stop (& mut self) -> DbgTim14StopW < Apb1FzSpec > { DbgTim14StopW :: new (self , 8) } # [doc = "Bit 11 - DBG_WWDG_STOP"] # [inline (always)] pub fn dbg_wwdg_stop (& mut self) -> DbgWwdgStopW < Apb1FzSpec > { DbgWwdgStopW :: new (self , 11) } # [doc = "Bit 12 - DBG_IWDEG_STOP"] # [inline (always)] pub fn dbg_iwdg_stop (& mut self) -> DbgIwdgStopW < Apb1FzSpec > { DbgIwdgStopW :: new (self , 12) } # [doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c1_smbus_timeout (& mut self) -> DbgJ2c1SmbusTimeoutW < Apb1FzSpec > { DbgJ2c1SmbusTimeoutW :: new (self , 21) } # [doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c2_smbus_timeout (& mut self) -> DbgJ2c2SmbusTimeoutW < Apb1FzSpec > { DbgJ2c2SmbusTimeoutW :: new (self , 22) } # [doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] # [inline (always)] pub fn dbg_j2c3smbus_timeout (& mut self) -> DbgJ2c3smbusTimeoutW < Apb1FzSpec > { DbgJ2c3smbusTimeoutW :: new (self , 23) } # [doc = "Bit 25 - DBG_CAN1_STOP"] # [inline (always)] pub fn dbg_can1_stop (& mut self) -> DbgCan1StopW < Apb1FzSpec > { DbgCan1StopW :: new (self , 25) } # [doc = "Bit 26 - DBG_CAN2_STOP"] # [inline (always)] pub fn dbg_can2_stop (& mut self) -> DbgCan2StopW <'_, Apb1FzSpec > { DbgCan2StopW :: new (self , 26) } } # [doc = "Debug MCU APB1 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb1FzSpec ; impl crate :: RegisterSpec for Apb1FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1_fz::R`](R) reader structure"] impl crate :: Readable for Apb1FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure"] impl crate :: Writable for Apb1FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB1_FZ to value 0"] impl crate :: Resettable for Apb1FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb2_fz.rs:1:2636 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_tim1_stop (& mut self) -> DbgTim1StopW < Apb2FzSpec > { DbgTim1StopW :: new (self , 0) } # [doc = "Bit 1 - TIM8 coun... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB2_FZ` reader"] pub type R = crate :: R < Apb2FzSpec > ; # [doc = "Register `APB2_FZ` writer"] pub type W = crate :: W < Apb2FzSpec > ; # [doc = "Field `DBG_TIM1_STOP` reader - TIM1 counter stopped when core is halted"] pub type DbgTim1StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM1_STOP` writer - TIM1 counter stopped when core is halted"] pub type DbgTim1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - TIM8 counter stopped when core is halted"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - TIM8 counter stopped when core is halted"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM9_STOP` reader - TIM9 counter stopped when core is halted"] pub type DbgTim9StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM9_STOP` writer - TIM9 counter stopped when core is halted"] pub type DbgTim9StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM10_STOP` reader - TIM10 counter stopped when core is halted"] pub type DbgTim10StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM10_STOP` writer - TIM10 counter stopped when core is halted"] pub type DbgTim10StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM11_STOP` reader - TIM11 counter stopped when core is halted"] pub type DbgTim11StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM11_STOP` writer - TIM11 counter stopped when core is halted"] pub type DbgTim11StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - TIM1 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim1_stop (& self) -> DbgTim1StopR { DbgTim1StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - TIM8 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 16 - TIM9 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim9_stop (& self) -> DbgTim9StopR { DbgTim9StopR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - TIM10 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim10_stop (& self) -> DbgTim10StopR { DbgTim10StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - TIM11 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim11_stop (& self) -> DbgTim11StopR { DbgTim11StopR :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bit 0 - TIM1 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim1_stop (& mut self) -> DbgTim1StopW <'_, Apb2FzSpec > { DbgTim1StopW :: new (self , 0) } # [doc = "Bit 1 - TIM8 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < Apb2FzSpec > { DbgTim8StopW :: new (self , 1) } # [doc = "Bit 16 - TIM9 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim9_stop (& mut self) -> DbgTim9StopW < Apb2FzSpec > { DbgTim9StopW :: new (self , 16) } # [doc = "Bit 17 - TIM10 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim10_stop (& mut self) -> DbgTim10StopW < Apb2FzSpec > { DbgTim10StopW :: new (self , 17) } # [doc = "Bit 18 - TIM11 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim11_stop (& mut self) -> DbgTim11StopW < Apb2FzSpec > { DbgTim11StopW :: new (self , 18) } } # [doc = "Debug MCU APB2 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb2_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb2FzSpec ; impl crate :: RegisterSpec for Apb2FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb2_fz::R`](R) reader structure"] impl crate :: Readable for Apb2FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb2_fz::W`](W) writer structure"] impl crate :: Writable for Apb2FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB2_FZ to value 0"] impl crate :: Resettable for Apb2FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb2_fz.rs:1:2817 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < Apb2FzSpec > { DbgTim8StopW :: new (self , 1) } # [doc = "Bit 16 - TIM9 cou... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB2_FZ` reader"] pub type R = crate :: R < Apb2FzSpec > ; # [doc = "Register `APB2_FZ` writer"] pub type W = crate :: W < Apb2FzSpec > ; # [doc = "Field `DBG_TIM1_STOP` reader - TIM1 counter stopped when core is halted"] pub type DbgTim1StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM1_STOP` writer - TIM1 counter stopped when core is halted"] pub type DbgTim1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - TIM8 counter stopped when core is halted"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - TIM8 counter stopped when core is halted"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM9_STOP` reader - TIM9 counter stopped when core is halted"] pub type DbgTim9StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM9_STOP` writer - TIM9 counter stopped when core is halted"] pub type DbgTim9StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM10_STOP` reader - TIM10 counter stopped when core is halted"] pub type DbgTim10StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM10_STOP` writer - TIM10 counter stopped when core is halted"] pub type DbgTim10StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM11_STOP` reader - TIM11 counter stopped when core is halted"] pub type DbgTim11StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM11_STOP` writer - TIM11 counter stopped when core is halted"] pub type DbgTim11StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - TIM1 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim1_stop (& self) -> DbgTim1StopR { DbgTim1StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - TIM8 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 16 - TIM9 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim9_stop (& self) -> DbgTim9StopR { DbgTim9StopR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - TIM10 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim10_stop (& self) -> DbgTim10StopR { DbgTim10StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - TIM11 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim11_stop (& self) -> DbgTim11StopR { DbgTim11StopR :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bit 0 - TIM1 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim1_stop (& mut self) -> DbgTim1StopW < Apb2FzSpec > { DbgTim1StopW :: new (self , 0) } # [doc = "Bit 1 - TIM8 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW <'_, Apb2FzSpec > { DbgTim8StopW :: new (self , 1) } # [doc = "Bit 16 - TIM9 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim9_stop (& mut self) -> DbgTim9StopW < Apb2FzSpec > { DbgTim9StopW :: new (self , 16) } # [doc = "Bit 17 - TIM10 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim10_stop (& mut self) -> DbgTim10StopW < Apb2FzSpec > { DbgTim10StopW :: new (self , 17) } # [doc = "Bit 18 - TIM11 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim11_stop (& mut self) -> DbgTim11StopW < Apb2FzSpec > { DbgTim11StopW :: new (self , 18) } } # [doc = "Debug MCU APB2 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb2_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb2FzSpec ; impl crate :: RegisterSpec for Apb2FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb2_fz::R`](R) reader structure"] impl crate :: Readable for Apb2FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb2_fz::W`](W) writer structure"] impl crate :: Writable for Apb2FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB2_FZ to value 0"] impl crate :: Resettable for Apb2FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb2_fz.rs:1:2999 [INFO] [stdout] | [INFO] [stdout] 1 | ...ways)] pub fn dbg_tim9_stop (& mut self) -> DbgTim9StopW < Apb2FzSpec > { DbgTim9StopW :: new (self , 16) } # [doc = "Bit 17 - TIM10 c... [INFO] [stdout] | ^^^^^^^^^^ --------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB2_FZ` reader"] pub type R = crate :: R < Apb2FzSpec > ; # [doc = "Register `APB2_FZ` writer"] pub type W = crate :: W < Apb2FzSpec > ; # [doc = "Field `DBG_TIM1_STOP` reader - TIM1 counter stopped when core is halted"] pub type DbgTim1StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM1_STOP` writer - TIM1 counter stopped when core is halted"] pub type DbgTim1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - TIM8 counter stopped when core is halted"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - TIM8 counter stopped when core is halted"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM9_STOP` reader - TIM9 counter stopped when core is halted"] pub type DbgTim9StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM9_STOP` writer - TIM9 counter stopped when core is halted"] pub type DbgTim9StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM10_STOP` reader - TIM10 counter stopped when core is halted"] pub type DbgTim10StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM10_STOP` writer - TIM10 counter stopped when core is halted"] pub type DbgTim10StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM11_STOP` reader - TIM11 counter stopped when core is halted"] pub type DbgTim11StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM11_STOP` writer - TIM11 counter stopped when core is halted"] pub type DbgTim11StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - TIM1 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim1_stop (& self) -> DbgTim1StopR { DbgTim1StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - TIM8 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 16 - TIM9 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim9_stop (& self) -> DbgTim9StopR { DbgTim9StopR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - TIM10 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim10_stop (& self) -> DbgTim10StopR { DbgTim10StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - TIM11 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim11_stop (& self) -> DbgTim11StopR { DbgTim11StopR :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bit 0 - TIM1 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim1_stop (& mut self) -> DbgTim1StopW < Apb2FzSpec > { DbgTim1StopW :: new (self , 0) } # [doc = "Bit 1 - TIM8 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < Apb2FzSpec > { DbgTim8StopW :: new (self , 1) } # [doc = "Bit 16 - TIM9 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim9_stop (& mut self) -> DbgTim9StopW <'_, Apb2FzSpec > { DbgTim9StopW :: new (self , 16) } # [doc = "Bit 17 - TIM10 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim10_stop (& mut self) -> DbgTim10StopW < Apb2FzSpec > { DbgTim10StopW :: new (self , 17) } # [doc = "Bit 18 - TIM11 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim11_stop (& mut self) -> DbgTim11StopW < Apb2FzSpec > { DbgTim11StopW :: new (self , 18) } } # [doc = "Debug MCU APB2 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb2_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb2FzSpec ; impl crate :: RegisterSpec for Apb2FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb2_fz::R`](R) reader structure"] impl crate :: Readable for Apb2FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb2_fz::W`](W) writer structure"] impl crate :: Writable for Apb2FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB2_FZ to value 0"] impl crate :: Resettable for Apb2FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb2_fz.rs:1:3184 [INFO] [stdout] | [INFO] [stdout] 1 | ...ays)] pub fn dbg_tim10_stop (& mut self) -> DbgTim10StopW < Apb2FzSpec > { DbgTim10StopW :: new (self , 17) } # [doc = "Bit 18 - TIM11... [INFO] [stdout] | ^^^^^^^^^^ ---------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB2_FZ` reader"] pub type R = crate :: R < Apb2FzSpec > ; # [doc = "Register `APB2_FZ` writer"] pub type W = crate :: W < Apb2FzSpec > ; # [doc = "Field `DBG_TIM1_STOP` reader - TIM1 counter stopped when core is halted"] pub type DbgTim1StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM1_STOP` writer - TIM1 counter stopped when core is halted"] pub type DbgTim1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - TIM8 counter stopped when core is halted"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - TIM8 counter stopped when core is halted"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM9_STOP` reader - TIM9 counter stopped when core is halted"] pub type DbgTim9StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM9_STOP` writer - TIM9 counter stopped when core is halted"] pub type DbgTim9StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM10_STOP` reader - TIM10 counter stopped when core is halted"] pub type DbgTim10StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM10_STOP` writer - TIM10 counter stopped when core is halted"] pub type DbgTim10StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM11_STOP` reader - TIM11 counter stopped when core is halted"] pub type DbgTim11StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM11_STOP` writer - TIM11 counter stopped when core is halted"] pub type DbgTim11StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - TIM1 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim1_stop (& self) -> DbgTim1StopR { DbgTim1StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - TIM8 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 16 - TIM9 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim9_stop (& self) -> DbgTim9StopR { DbgTim9StopR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - TIM10 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim10_stop (& self) -> DbgTim10StopR { DbgTim10StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - TIM11 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim11_stop (& self) -> DbgTim11StopR { DbgTim11StopR :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bit 0 - TIM1 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim1_stop (& mut self) -> DbgTim1StopW < Apb2FzSpec > { DbgTim1StopW :: new (self , 0) } # [doc = "Bit 1 - TIM8 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < Apb2FzSpec > { DbgTim8StopW :: new (self , 1) } # [doc = "Bit 16 - TIM9 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim9_stop (& mut self) -> DbgTim9StopW < Apb2FzSpec > { DbgTim9StopW :: new (self , 16) } # [doc = "Bit 17 - TIM10 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim10_stop (& mut self) -> DbgTim10StopW <'_, Apb2FzSpec > { DbgTim10StopW :: new (self , 17) } # [doc = "Bit 18 - TIM11 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim11_stop (& mut self) -> DbgTim11StopW < Apb2FzSpec > { DbgTim11StopW :: new (self , 18) } } # [doc = "Debug MCU APB2 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb2_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb2FzSpec ; impl crate :: RegisterSpec for Apb2FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb2_fz::R`](R) reader structure"] impl crate :: Readable for Apb2FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb2_fz::W`](W) writer structure"] impl crate :: Writable for Apb2FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB2_FZ to value 0"] impl crate :: Resettable for Apb2FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dbgmcu/apb2_fz.rs:1:3371 [INFO] [stdout] | [INFO] [stdout] 1 | ...ays)] pub fn dbg_tim11_stop (& mut self) -> DbgTim11StopW < Apb2FzSpec > { DbgTim11StopW :: new (self , 18) } } # [doc = "Debug MCU AP... [INFO] [stdout] | ^^^^^^^^^^ ---------------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `APB2_FZ` reader"] pub type R = crate :: R < Apb2FzSpec > ; # [doc = "Register `APB2_FZ` writer"] pub type W = crate :: W < Apb2FzSpec > ; # [doc = "Field `DBG_TIM1_STOP` reader - TIM1 counter stopped when core is halted"] pub type DbgTim1StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM1_STOP` writer - TIM1 counter stopped when core is halted"] pub type DbgTim1StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - TIM8 counter stopped when core is halted"] pub type DbgTim8StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - TIM8 counter stopped when core is halted"] pub type DbgTim8StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM9_STOP` reader - TIM9 counter stopped when core is halted"] pub type DbgTim9StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM9_STOP` writer - TIM9 counter stopped when core is halted"] pub type DbgTim9StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM10_STOP` reader - TIM10 counter stopped when core is halted"] pub type DbgTim10StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM10_STOP` writer - TIM10 counter stopped when core is halted"] pub type DbgTim10StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM11_STOP` reader - TIM11 counter stopped when core is halted"] pub type DbgTim11StopR = crate :: BitReader ; # [doc = "Field `DBG_TIM11_STOP` writer - TIM11 counter stopped when core is halted"] pub type DbgTim11StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - TIM1 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim1_stop (& self) -> DbgTim1StopR { DbgTim1StopR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - TIM8 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim8_stop (& self) -> DbgTim8StopR { DbgTim8StopR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 16 - TIM9 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim9_stop (& self) -> DbgTim9StopR { DbgTim9StopR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - TIM10 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim10_stop (& self) -> DbgTim10StopR { DbgTim10StopR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - TIM11 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim11_stop (& self) -> DbgTim11StopR { DbgTim11StopR :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bit 0 - TIM1 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim1_stop (& mut self) -> DbgTim1StopW < Apb2FzSpec > { DbgTim1StopW :: new (self , 0) } # [doc = "Bit 1 - TIM8 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim8_stop (& mut self) -> DbgTim8StopW < Apb2FzSpec > { DbgTim8StopW :: new (self , 1) } # [doc = "Bit 16 - TIM9 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim9_stop (& mut self) -> DbgTim9StopW < Apb2FzSpec > { DbgTim9StopW :: new (self , 16) } # [doc = "Bit 17 - TIM10 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim10_stop (& mut self) -> DbgTim10StopW < Apb2FzSpec > { DbgTim10StopW :: new (self , 17) } # [doc = "Bit 18 - TIM11 counter stopped when core is halted"] # [inline (always)] pub fn dbg_tim11_stop (& mut self) -> DbgTim11StopW <'_, Apb2FzSpec > { DbgTim11StopW :: new (self , 18) } } # [doc = "Debug MCU APB2 Freeze registe\n\nYou can [`read`](crate::Reg::read) this register and get [`apb2_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Apb2FzSpec ; impl crate :: RegisterSpec for Apb2FzSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`apb2_fz::R`](R) reader structure"] impl crate :: Readable for Apb2FzSpec { } # [doc = "`write(|w| ..)` method takes [`apb2_fz::W`](W) writer structure"] impl crate :: Writable for Apb2FzSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets APB2_FZ to value 0"] impl crate :: Resettable for Apb2FzSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:5809 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear di... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W <'_, LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:5991 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W <'_, LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:6171 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear ha... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W <'_, LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:6348 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear tr... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W <'_, LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:6529 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FI... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W <'_, LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:6703 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear di... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W <'_, LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:6885 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W <'_, LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:7065 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear h... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W <'_, LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:7243 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W <'_, LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:7426 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W <'_, LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:7602 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W <'_, LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:7786 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clea... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W <'_, LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:7968 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W <'_, LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:8147 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W <'_, LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:8330 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W <'_, LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:8506 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W <'_, LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:8690 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clea... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W <'_, LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:8872 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W <'_, LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:9051 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W <'_, LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/lifcr.rs:1:9234 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W < LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag cle... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `LIFCR` writer"] pub type W = crate :: W < LifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif0 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif0 > for bool { # [inline (always)] fn from (variant : Cfeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF0` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub type Cfeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif0 > ; impl < 'a , REG > Cfeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif0 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif0 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif0 > for bool { # [inline (always)] fn from (variant : Cdmeif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF0` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub type Cdmeif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif0 > ; impl < 'a , REG > Cdmeif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif0 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif0 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif0 > for bool { # [inline (always)] fn from (variant : Cteif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF0` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub type Cteif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif0 > ; impl < 'a , REG > Cteif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif0 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif0 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif0 > for bool { # [inline (always)] fn from (variant : Chtif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF0` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub type Chtif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif0 > ; impl < 'a , REG > Chtif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif0 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 3..0)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif0 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif0 > for bool { # [inline (always)] fn from (variant : Ctcif0) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF0` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub type Ctcif0W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif0 > ; impl < 'a , REG > Ctcif0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif0 :: Clear) } } # [doc = "Field `CFEIF1` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif1W ; # [doc = "Field `CDMEIF1` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif1W ; # [doc = "Field `CTEIF1` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif1W ; # [doc = "Field `CHTIF1` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif1W ; # [doc = "Field `CTCIF1` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif1W ; # [doc = "Field `CFEIF2` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif2W ; # [doc = "Field `CDMEIF2` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif2W ; # [doc = "Field `CTEIF2` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif2W ; # [doc = "Field `CHTIF2` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif2W ; # [doc = "Field `CTCIF2` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif2W ; # [doc = "Field `CFEIF3` writer - Stream x clear FIFO error interrupt flag (x = 3..0)"] pub use Cfeif0W as Cfeif3W ; # [doc = "Field `CDMEIF3` writer - Stream x clear direct mode error interrupt flag (x = 3..0)"] pub use Cdmeif0W as Cdmeif3W ; # [doc = "Field `CTEIF3` writer - Stream x clear transfer error interrupt flag (x = 3..0)"] pub use Cteif0W as Cteif3W ; # [doc = "Field `CHTIF3` writer - Stream x clear half transfer interrupt flag (x = 3..0)"] pub use Chtif0W as Chtif3W ; # [doc = "Field `CTCIF3` writer - Stream x clear transfer complete interrupt flag (x = 3..0)"] pub use Ctcif0W as Ctcif3W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif0 (& mut self) -> Cfeif0W < LifcrSpec > { Cfeif0W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif0 (& mut self) -> Cdmeif0W < LifcrSpec > { Cdmeif0W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif0 (& mut self) -> Cteif0W < LifcrSpec > { Cteif0W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif0 (& mut self) -> Chtif0W < LifcrSpec > { Chtif0W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif0 (& mut self) -> Ctcif0W < LifcrSpec > { Ctcif0W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif1 (& mut self) -> Cfeif1W < LifcrSpec > { Cfeif1W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif1 (& mut self) -> Cdmeif1W < LifcrSpec > { Cdmeif1W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif1 (& mut self) -> Cteif1W < LifcrSpec > { Cteif1W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif1 (& mut self) -> Chtif1W < LifcrSpec > { Chtif1W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif1 (& mut self) -> Ctcif1W < LifcrSpec > { Ctcif1W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif2 (& mut self) -> Cfeif2W < LifcrSpec > { Cfeif2W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif2 (& mut self) -> Cdmeif2W < LifcrSpec > { Cdmeif2W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif2 (& mut self) -> Cteif2W < LifcrSpec > { Cteif2W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif2 (& mut self) -> Chtif2W < LifcrSpec > { Chtif2W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif2 (& mut self) -> Ctcif2W < LifcrSpec > { Ctcif2W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cfeif3 (& mut self) -> Cfeif3W < LifcrSpec > { Cfeif3W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cdmeif3 (& mut self) -> Cdmeif3W < LifcrSpec > { Cdmeif3W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"] # [inline (always)] pub fn cteif3 (& mut self) -> Cteif3W < LifcrSpec > { Cteif3W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"] # [inline (always)] pub fn chtif3 (& mut self) -> Chtif3W < LifcrSpec > { Chtif3W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"] # [inline (always)] pub fn ctcif3 (& mut self) -> Ctcif3W <'_, LifcrSpec > { Ctcif3W :: new (self , 27) } } # [doc = "low interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LifcrSpec ; impl crate :: RegisterSpec for LifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`lifcr::W`](W) writer structure"] impl crate :: Writable for LifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets LIFCR to value 0"] impl crate :: Resettable for LifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:5809 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear di... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W <'_, HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:5991 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W <'_, HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:6171 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear ha... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W <'_, HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:6348 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear tr... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W <'_, HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:6529 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FI... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W <'_, HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:6703 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear di... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W <'_, HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:6885 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W <'_, HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:7065 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear h... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W <'_, HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:7243 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W <'_, HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:7426 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W <'_, HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:7602 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W <'_, HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:7786 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clea... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W <'_, HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:7968 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W <'_, HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:8147 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W <'_, HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:8330 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W <'_, HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:8506 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W <'_, HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:8690 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clea... [INFO] [stdout] | ^^^^^^^^^^ ---------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W <'_, HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:8872 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W <'_, HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:9051 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W <'_, HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/hifcr.rs:1:9234 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W < HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag cl... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `HIFCR` writer"] pub type W = crate :: W < HifcrSpec > ; # [doc = "Stream x clear FIFO error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cfeif4 { # [doc = "1: Clear the corresponding CFEIFx flag"] Clear = 1 , } impl From < Cfeif4 > for bool { # [inline (always)] fn from (variant : Cfeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CFEIF4` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub type Cfeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cfeif4 > ; impl < 'a , REG > Cfeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding CFEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cfeif4 :: Clear) } } # [doc = "Stream x clear direct mode error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cdmeif4 { # [doc = "1: Clear the corresponding DMEIFx flag"] Clear = 1 , } impl From < Cdmeif4 > for bool { # [inline (always)] fn from (variant : Cdmeif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CDMEIF4` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub type Cdmeif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cdmeif4 > ; impl < 'a , REG > Cdmeif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding DMEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cdmeif4 :: Clear) } } # [doc = "Stream x clear transfer error interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cteif4 { # [doc = "1: Clear the corresponding TEIFx flag"] Clear = 1 , } impl From < Cteif4 > for bool { # [inline (always)] fn from (variant : Cteif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTEIF4` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub type Cteif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Cteif4 > ; impl < 'a , REG > Cteif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TEIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Cteif4 :: Clear) } } # [doc = "Stream x clear half transfer interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Chtif4 { # [doc = "1: Clear the corresponding HTIFx flag"] Clear = 1 , } impl From < Chtif4 > for bool { # [inline (always)] fn from (variant : Chtif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CHTIF4` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub type Chtif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Chtif4 > ; impl < 'a , REG > Chtif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding HTIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Chtif4 :: Clear) } } # [doc = "Stream x clear transfer complete interrupt flag (x = 7..4)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ctcif4 { # [doc = "1: Clear the corresponding TCIFx flag"] Clear = 1 , } impl From < Ctcif4 > for bool { # [inline (always)] fn from (variant : Ctcif4) -> Self { variant as u8 != 0 } } # [doc = "Field `CTCIF4` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub type Ctcif4W < 'a , REG > = crate :: BitWriter < 'a , REG , Ctcif4 > ; impl < 'a , REG > Ctcif4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clear the corresponding TCIFx flag"] # [inline (always)] pub fn clear (self) -> & 'a mut crate :: W < REG > { self . variant (Ctcif4 :: Clear) } } # [doc = "Field `CFEIF5` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif5W ; # [doc = "Field `CDMEIF5` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif5W ; # [doc = "Field `CTEIF5` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif5W ; # [doc = "Field `CHTIF5` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif5W ; # [doc = "Field `CTCIF5` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif5W ; # [doc = "Field `CFEIF6` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif6W ; # [doc = "Field `CDMEIF6` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif6W ; # [doc = "Field `CTEIF6` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif6W ; # [doc = "Field `CHTIF6` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif6W ; # [doc = "Field `CTCIF6` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif6W ; # [doc = "Field `CFEIF7` writer - Stream x clear FIFO error interrupt flag (x = 7..4)"] pub use Cfeif4W as Cfeif7W ; # [doc = "Field `CDMEIF7` writer - Stream x clear direct mode error interrupt flag (x = 7..4)"] pub use Cdmeif4W as Cdmeif7W ; # [doc = "Field `CTEIF7` writer - Stream x clear transfer error interrupt flag (x = 7..4)"] pub use Cteif4W as Cteif7W ; # [doc = "Field `CHTIF7` writer - Stream x clear half transfer interrupt flag (x = 7..4)"] pub use Chtif4W as Chtif7W ; # [doc = "Field `CTCIF7` writer - Stream x clear transfer complete interrupt flag (x = 7..4)"] pub use Ctcif4W as Ctcif7W ; impl W { # [doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif4 (& mut self) -> Cfeif4W < HifcrSpec > { Cfeif4W :: new (self , 0) } # [doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif4 (& mut self) -> Cdmeif4W < HifcrSpec > { Cdmeif4W :: new (self , 2) } # [doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif4 (& mut self) -> Cteif4W < HifcrSpec > { Cteif4W :: new (self , 3) } # [doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif4 (& mut self) -> Chtif4W < HifcrSpec > { Chtif4W :: new (self , 4) } # [doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif4 (& mut self) -> Ctcif4W < HifcrSpec > { Ctcif4W :: new (self , 5) } # [doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif5 (& mut self) -> Cfeif5W < HifcrSpec > { Cfeif5W :: new (self , 6) } # [doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif5 (& mut self) -> Cdmeif5W < HifcrSpec > { Cdmeif5W :: new (self , 8) } # [doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif5 (& mut self) -> Cteif5W < HifcrSpec > { Cteif5W :: new (self , 9) } # [doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif5 (& mut self) -> Chtif5W < HifcrSpec > { Chtif5W :: new (self , 10) } # [doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif5 (& mut self) -> Ctcif5W < HifcrSpec > { Ctcif5W :: new (self , 11) } # [doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif6 (& mut self) -> Cfeif6W < HifcrSpec > { Cfeif6W :: new (self , 16) } # [doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif6 (& mut self) -> Cdmeif6W < HifcrSpec > { Cdmeif6W :: new (self , 18) } # [doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif6 (& mut self) -> Cteif6W < HifcrSpec > { Cteif6W :: new (self , 19) } # [doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif6 (& mut self) -> Chtif6W < HifcrSpec > { Chtif6W :: new (self , 20) } # [doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif6 (& mut self) -> Ctcif6W < HifcrSpec > { Ctcif6W :: new (self , 21) } # [doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cfeif7 (& mut self) -> Cfeif7W < HifcrSpec > { Cfeif7W :: new (self , 22) } # [doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cdmeif7 (& mut self) -> Cdmeif7W < HifcrSpec > { Cdmeif7W :: new (self , 24) } # [doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"] # [inline (always)] pub fn cteif7 (& mut self) -> Cteif7W < HifcrSpec > { Cteif7W :: new (self , 25) } # [doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"] # [inline (always)] pub fn chtif7 (& mut self) -> Chtif7W < HifcrSpec > { Chtif7W :: new (self , 26) } # [doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"] # [inline (always)] pub fn ctcif7 (& mut self) -> Ctcif7W <'_, HifcrSpec > { Ctcif7W :: new (self , 27) } } # [doc = "high interrupt flag clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HifcrSpec ; impl crate :: RegisterSpec for HifcrSpec { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`hifcr::W`](W) writer structure"] impl crate :: Writable for HifcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets HIFCR to value 0"] impl crate :: Resettable for HifcrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:28255 [INFO] [stdout] | [INFO] [stdout] 1 | ...ow"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interr... [INFO] [stdout] | ^^^^^^^^^^ -------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW <'_, CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:28400 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error inter... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW <'_, CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:28547 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interru... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW <'_, CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:28691 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete int... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW <'_, CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:28839 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow contr... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW <'_, CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:28981 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer d... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW <'_, CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:29124 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inli... [INFO] [stdout] | ^^^^^^^^^^ --------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW <'_, CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:29249 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment ... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW <'_, CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:29388 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mod... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW <'_, CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:29524 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW <'_, CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:29665 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data si... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW <'_, CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:29804 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increme... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW <'_, CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:29956 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority lev... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW <'_, CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:30092 [INFO] [stdout] | [INFO] [stdout] 1 | ...el"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] #... [INFO] [stdout] | ^^^^^^^^^^ -------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW <'_, CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:30221 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only ... [INFO] [stdout] | ^^^^^^^^^^ --------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW <'_, CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:30376 [INFO] [stdout] | [INFO] [stdout] 1 | ...e)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst t... [INFO] [stdout] | ^^^^^^^^^^ -------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW <'_, CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:30533 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW <'_, CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:30694 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel sele... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW <'_, CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/cr.rs:1:30836 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn chsel (& mut self) -> ChselW < CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration re... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Stream enable / flag stream ready when read low\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum En { # [doc = "0: Stream disabled"] Disabled = 0 , # [doc = "1: Stream enabled"] Enabled = 1 , } impl From < En > for bool { # [inline (always)] fn from (variant : En) -> Self { variant as u8 != 0 } } # [doc = "Field `EN` reader - Stream enable / flag stream ready when read low"] pub type EnR = crate :: BitReader < En > ; impl EnR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> En { match self . bits { false => En :: Disabled , true => En :: Enabled , } } # [doc = "Stream disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == En :: Disabled } # [doc = "Stream enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == En :: Enabled } } # [doc = "Field `EN` writer - Stream enable / flag stream ready when read low"] pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG , En > ; impl < 'a , REG > EnW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Stream disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Disabled) } # [doc = "Stream enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (En :: Enabled) } } # [doc = "Direct mode error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmeie { # [doc = "0: DME interrupt disabled"] Disabled = 0 , # [doc = "1: DME interrupt enabled"] Enabled = 1 , } impl From < Dmeie > for bool { # [inline (always)] fn from (variant : Dmeie) -> Self { variant as u8 != 0 } } # [doc = "Field `DMEIE` reader - Direct mode error interrupt enable"] pub type DmeieR = crate :: BitReader < Dmeie > ; impl DmeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmeie { match self . bits { false => Dmeie :: Disabled , true => Dmeie :: Enabled , } } # [doc = "DME interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmeie :: Disabled } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmeie :: Enabled } } # [doc = "Field `DMEIE` writer - Direct mode error interrupt enable"] pub type DmeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmeie > ; impl < 'a , REG > DmeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DME interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Disabled) } # [doc = "DME interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmeie :: Enabled) } } # [doc = "Transfer error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Teie { # [doc = "0: TE interrupt disabled"] Disabled = 0 , # [doc = "1: TE interrupt enabled"] Enabled = 1 , } impl From < Teie > for bool { # [inline (always)] fn from (variant : Teie) -> Self { variant as u8 != 0 } } # [doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TeieR = crate :: BitReader < Teie > ; impl TeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Teie { match self . bits { false => Teie :: Disabled , true => Teie :: Enabled , } } # [doc = "TE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Teie :: Disabled } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Teie :: Enabled } } # [doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Teie > ; impl < 'a , REG > TeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Disabled) } # [doc = "TE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Teie :: Enabled) } } # [doc = "Half transfer interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Htie { # [doc = "0: HT interrupt disabled"] Disabled = 0 , # [doc = "1: HT interrupt enabled"] Enabled = 1 , } impl From < Htie > for bool { # [inline (always)] fn from (variant : Htie) -> Self { variant as u8 != 0 } } # [doc = "Field `HTIE` reader - Half transfer interrupt enable"] pub type HtieR = crate :: BitReader < Htie > ; impl HtieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Htie { match self . bits { false => Htie :: Disabled , true => Htie :: Enabled , } } # [doc = "HT interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Htie :: Disabled } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Htie :: Enabled } } # [doc = "Field `HTIE` writer - Half transfer interrupt enable"] pub type HtieW < 'a , REG > = crate :: BitWriter < 'a , REG , Htie > ; impl < 'a , REG > HtieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HT interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Disabled) } # [doc = "HT interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Htie :: Enabled) } } # [doc = "Transfer complete interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Tcie { # [doc = "0: TC interrupt disabled"] Disabled = 0 , # [doc = "1: TC interrupt enabled"] Enabled = 1 , } impl From < Tcie > for bool { # [inline (always)] fn from (variant : Tcie) -> Self { variant as u8 != 0 } } # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TcieR = crate :: BitReader < Tcie > ; impl TcieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Tcie { match self . bits { false => Tcie :: Disabled , true => Tcie :: Enabled , } } # [doc = "TC interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Tcie :: Disabled } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Tcie :: Enabled } } # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TcieW < 'a , REG > = crate :: BitWriter < 'a , REG , Tcie > ; impl < 'a , REG > TcieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TC interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Disabled) } # [doc = "TC interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Tcie :: Enabled) } } # [doc = "Peripheral flow controller\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pfctrl { # [doc = "0: The DMA is the flow controller"] Dma = 0 , # [doc = "1: The peripheral is the flow controller"] Peripheral = 1 , } impl From < Pfctrl > for bool { # [inline (always)] fn from (variant : Pfctrl) -> Self { variant as u8 != 0 } } # [doc = "Field `PFCTRL` reader - Peripheral flow controller"] pub type PfctrlR = crate :: BitReader < Pfctrl > ; impl PfctrlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pfctrl { match self . bits { false => Pfctrl :: Dma , true => Pfctrl :: Peripheral , } } # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn is_dma (& self) -> bool { * self == Pfctrl :: Dma } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn is_peripheral (& self) -> bool { * self == Pfctrl :: Peripheral } } # [doc = "Field `PFCTRL` writer - Peripheral flow controller"] pub type PfctrlW < 'a , REG > = crate :: BitWriter < 'a , REG , Pfctrl > ; impl < 'a , REG > PfctrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The DMA is the flow controller"] # [inline (always)] pub fn dma (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Dma) } # [doc = "The peripheral is the flow controller"] # [inline (always)] pub fn peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Pfctrl :: Peripheral) } } # [doc = "Data transfer direction\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Dir { # [doc = "0: Peripheral-to-memory"] PeripheralToMemory = 0 , # [doc = "1: Memory-to-peripheral"] MemoryToPeripheral = 1 , # [doc = "2: Memory-to-memory"] MemoryToMemory = 2 , } impl From < Dir > for u8 { # [inline (always)] fn from (variant : Dir) -> Self { variant as _ } } impl crate :: FieldSpec for Dir { type Ux = u8 ; } impl crate :: IsEnum for Dir { } # [doc = "Field `DIR` reader - Data transfer direction"] pub type DirR = crate :: FieldReader < Dir > ; impl DirR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Dir > { match self . bits { 0 => Some (Dir :: PeripheralToMemory) , 1 => Some (Dir :: MemoryToPeripheral) , 2 => Some (Dir :: MemoryToMemory) , _ => None , } } # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn is_peripheral_to_memory (& self) -> bool { * self == Dir :: PeripheralToMemory } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn is_memory_to_peripheral (& self) -> bool { * self == Dir :: MemoryToPeripheral } # [doc = "Memory-to-memory"] # [inline (always)] pub fn is_memory_to_memory (& self) -> bool { * self == Dir :: MemoryToMemory } } # [doc = "Field `DIR` writer - Data transfer direction"] pub type DirW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dir > ; impl < 'a , REG > DirW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Peripheral-to-memory"] # [inline (always)] pub fn peripheral_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: PeripheralToMemory) } # [doc = "Memory-to-peripheral"] # [inline (always)] pub fn memory_to_peripheral (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToPeripheral) } # [doc = "Memory-to-memory"] # [inline (always)] pub fn memory_to_memory (self) -> & 'a mut crate :: W < REG > { self . variant (Dir :: MemoryToMemory) } } # [doc = "Circular mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Circ { # [doc = "0: Circular mode disabled"] Disabled = 0 , # [doc = "1: Circular mode enabled"] Enabled = 1 , } impl From < Circ > for bool { # [inline (always)] fn from (variant : Circ) -> Self { variant as u8 != 0 } } # [doc = "Field `CIRC` reader - Circular mode"] pub type CircR = crate :: BitReader < Circ > ; impl CircR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Circ { match self . bits { false => Circ :: Disabled , true => Circ :: Enabled , } } # [doc = "Circular mode disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Circ :: Disabled } # [doc = "Circular mode enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Circ :: Enabled } } # [doc = "Field `CIRC` writer - Circular mode"] pub type CircW < 'a , REG > = crate :: BitWriter < 'a , REG , Circ > ; impl < 'a , REG > CircW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Circular mode disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Disabled) } # [doc = "Circular mode enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Circ :: Enabled) } } # [doc = "Peripheral increment mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pinc { # [doc = "0: Address pointer is fixed"] Fixed = 0 , # [doc = "1: Address pointer is incremented after each data transfer"] Incremented = 1 , } impl From < Pinc > for bool { # [inline (always)] fn from (variant : Pinc) -> Self { variant as u8 != 0 } } # [doc = "Field `PINC` reader - Peripheral increment mode"] pub type PincR = crate :: BitReader < Pinc > ; impl PincR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pinc { match self . bits { false => Pinc :: Fixed , true => Pinc :: Incremented , } } # [doc = "Address pointer is fixed"] # [inline (always)] pub fn is_fixed (& self) -> bool { * self == Pinc :: Fixed } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn is_incremented (& self) -> bool { * self == Pinc :: Incremented } } # [doc = "Field `PINC` writer - Peripheral increment mode"] pub type PincW < 'a , REG > = crate :: BitWriter < 'a , REG , Pinc > ; impl < 'a , REG > PincW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Address pointer is fixed"] # [inline (always)] pub fn fixed (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Fixed) } # [doc = "Address pointer is incremented after each data transfer"] # [inline (always)] pub fn incremented (self) -> & 'a mut crate :: W < REG > { self . variant (Pinc :: Incremented) } } # [doc = "Field `MINC` reader - Memory increment mode"] pub use PincR as MincR ; # [doc = "Field `MINC` writer - Memory increment mode"] pub use PincW as MincW ; # [doc = "Peripheral data size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Psize { # [doc = "0: Byte (8-bit)"] Bits8 = 0 , # [doc = "1: Half-word (16-bit)"] Bits16 = 1 , # [doc = "2: Word (32-bit)"] Bits32 = 2 , } impl From < Psize > for u8 { # [inline (always)] fn from (variant : Psize) -> Self { variant as _ } } impl crate :: FieldSpec for Psize { type Ux = u8 ; } impl crate :: IsEnum for Psize { } # [doc = "Field `PSIZE` reader - Peripheral data size"] pub type PsizeR = crate :: FieldReader < Psize > ; impl PsizeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Psize > { match self . bits { 0 => Some (Psize :: Bits8) , 1 => Some (Psize :: Bits16) , 2 => Some (Psize :: Bits32) , _ => None , } } # [doc = "Byte (8-bit)"] # [inline (always)] pub fn is_bits8 (& self) -> bool { * self == Psize :: Bits8 } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn is_bits16 (& self) -> bool { * self == Psize :: Bits16 } # [doc = "Word (32-bit)"] # [inline (always)] pub fn is_bits32 (& self) -> bool { * self == Psize :: Bits32 } } # [doc = "Field `PSIZE` writer - Peripheral data size"] pub type PsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Psize > ; impl < 'a , REG > PsizeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Byte (8-bit)"] # [inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits8) } # [doc = "Half-word (16-bit)"] # [inline (always)] pub fn bits16 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits16) } # [doc = "Word (32-bit)"] # [inline (always)] pub fn bits32 (self) -> & 'a mut crate :: W < REG > { self . variant (Psize :: Bits32) } } # [doc = "Field `MSIZE` reader - Memory data size"] pub use PsizeR as MsizeR ; # [doc = "Field `MSIZE` writer - Memory data size"] pub use PsizeW as MsizeW ; # [doc = "Peripheral increment offset size\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pincos { # [doc = "0: The offset size for the peripheral address calculation is linked to the PSIZE"] Psize = 0 , # [doc = "1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] Fixed4 = 1 , } impl From < Pincos > for bool { # [inline (always)] fn from (variant : Pincos) -> Self { variant as u8 != 0 } } # [doc = "Field `PINCOS` reader - Peripheral increment offset size"] pub type PincosR = crate :: BitReader < Pincos > ; impl PincosR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pincos { match self . bits { false => Pincos :: Psize , true => Pincos :: Fixed4 , } } # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn is_psize (& self) -> bool { * self == Pincos :: Psize } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn is_fixed4 (& self) -> bool { * self == Pincos :: Fixed4 } } # [doc = "Field `PINCOS` writer - Peripheral increment offset size"] pub type PincosW < 'a , REG > = crate :: BitWriter < 'a , REG , Pincos > ; impl < 'a , REG > PincosW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] # [inline (always)] pub fn psize (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Psize) } # [doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] # [inline (always)] pub fn fixed4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pincos :: Fixed4) } } # [doc = "Priority level\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pl { # [doc = "0: Low"] Low = 0 , # [doc = "1: Medium"] Medium = 1 , # [doc = "2: High"] High = 2 , # [doc = "3: Very high"] VeryHigh = 3 , } impl From < Pl > for u8 { # [inline (always)] fn from (variant : Pl) -> Self { variant as _ } } impl crate :: FieldSpec for Pl { type Ux = u8 ; } impl crate :: IsEnum for Pl { } # [doc = "Field `PL` reader - Priority level"] pub type PlR = crate :: FieldReader < Pl > ; impl PlR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pl { match self . bits { 0 => Pl :: Low , 1 => Pl :: Medium , 2 => Pl :: High , 3 => Pl :: VeryHigh , _ => unreachable ! () , } } # [doc = "Low"] # [inline (always)] pub fn is_low (& self) -> bool { * self == Pl :: Low } # [doc = "Medium"] # [inline (always)] pub fn is_medium (& self) -> bool { * self == Pl :: Medium } # [doc = "High"] # [inline (always)] pub fn is_high (& self) -> bool { * self == Pl :: High } # [doc = "Very high"] # [inline (always)] pub fn is_very_high (& self) -> bool { * self == Pl :: VeryHigh } } # [doc = "Field `PL` writer - Priority level"] pub type PlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pl , crate :: Safe > ; impl < 'a , REG > PlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Low"] # [inline (always)] pub fn low (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Low) } # [doc = "Medium"] # [inline (always)] pub fn medium (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: Medium) } # [doc = "High"] # [inline (always)] pub fn high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: High) } # [doc = "Very high"] # [inline (always)] pub fn very_high (self) -> & 'a mut crate :: W < REG > { self . variant (Pl :: VeryHigh) } } # [doc = "Double buffer mode\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dbm { # [doc = "0: No buffer switching at the end of transfer"] Disabled = 0 , # [doc = "1: Memory target switched at the end of the DMA transfer"] Enabled = 1 , } impl From < Dbm > for bool { # [inline (always)] fn from (variant : Dbm) -> Self { variant as u8 != 0 } } # [doc = "Field `DBM` reader - Double buffer mode"] pub type DbmR = crate :: BitReader < Dbm > ; impl DbmR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dbm { match self . bits { false => Dbm :: Disabled , true => Dbm :: Enabled , } } # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dbm :: Disabled } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dbm :: Enabled } } # [doc = "Field `DBM` writer - Double buffer mode"] pub type DbmW < 'a , REG > = crate :: BitWriter < 'a , REG , Dbm > ; impl < 'a , REG > DbmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No buffer switching at the end of transfer"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Disabled) } # [doc = "Memory target switched at the end of the DMA transfer"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dbm :: Enabled) } } # [doc = "Current target (only in double buffer mode)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ct { # [doc = "0: The current target memory is Memory 0"] Memory0 = 0 , # [doc = "1: The current target memory is Memory 1"] Memory1 = 1 , } impl From < Ct > for bool { # [inline (always)] fn from (variant : Ct) -> Self { variant as u8 != 0 } } # [doc = "Field `CT` reader - Current target (only in double buffer mode)"] pub type CtR = crate :: BitReader < Ct > ; impl CtR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ct { match self . bits { false => Ct :: Memory0 , true => Ct :: Memory1 , } } # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn is_memory0 (& self) -> bool { * self == Ct :: Memory0 } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn is_memory1 (& self) -> bool { * self == Ct :: Memory1 } } # [doc = "Field `CT` writer - Current target (only in double buffer mode)"] pub type CtW < 'a , REG > = crate :: BitWriter < 'a , REG , Ct > ; impl < 'a , REG > CtW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The current target memory is Memory 0"] # [inline (always)] pub fn memory0 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory0) } # [doc = "The current target memory is Memory 1"] # [inline (always)] pub fn memory1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ct :: Memory1) } } # [doc = "Peripheral burst transfer configuration\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pburst { # [doc = "0: Single transfer"] Single = 0 , # [doc = "1: Incremental burst of 4 beats"] Incr4 = 1 , # [doc = "2: Incremental burst of 8 beats"] Incr8 = 2 , # [doc = "3: Incremental burst of 16 beats"] Incr16 = 3 , } impl From < Pburst > for u8 { # [inline (always)] fn from (variant : Pburst) -> Self { variant as _ } } impl crate :: FieldSpec for Pburst { type Ux = u8 ; } impl crate :: IsEnum for Pburst { } # [doc = "Field `PBURST` reader - Peripheral burst transfer configuration"] pub type PburstR = crate :: FieldReader < Pburst > ; impl PburstR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pburst { match self . bits { 0 => Pburst :: Single , 1 => Pburst :: Incr4 , 2 => Pburst :: Incr8 , 3 => Pburst :: Incr16 , _ => unreachable ! () , } } # [doc = "Single transfer"] # [inline (always)] pub fn is_single (& self) -> bool { * self == Pburst :: Single } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn is_incr4 (& self) -> bool { * self == Pburst :: Incr4 } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn is_incr8 (& self) -> bool { * self == Pburst :: Incr8 } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn is_incr16 (& self) -> bool { * self == Pburst :: Incr16 } } # [doc = "Field `PBURST` writer - Peripheral burst transfer configuration"] pub type PburstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pburst , crate :: Safe > ; impl < 'a , REG > PburstW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Single transfer"] # [inline (always)] pub fn single (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Single) } # [doc = "Incremental burst of 4 beats"] # [inline (always)] pub fn incr4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr4) } # [doc = "Incremental burst of 8 beats"] # [inline (always)] pub fn incr8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr8) } # [doc = "Incremental burst of 16 beats"] # [inline (always)] pub fn incr16 (self) -> & 'a mut crate :: W < REG > { self . variant (Pburst :: Incr16) } } # [doc = "Field `MBURST` reader - Memory burst transfer configuration"] pub use PburstR as MburstR ; # [doc = "Field `MBURST` writer - Memory burst transfer configuration"] pub use PburstW as MburstW ; # [doc = "Field `CHSEL` reader - Channel selection"] pub type ChselR = crate :: FieldReader ; # [doc = "Field `CHSEL` writer - Channel selection"] pub type ChselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , u8 , crate :: Safe > ; impl R { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& self) -> DmeieR { DmeieR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& self) -> TeieR { TeieR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& self) -> HtieR { HtieR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& self) -> TcieR { TcieR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& self) -> PfctrlR { PfctrlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& self) -> DirR { DirR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& self) -> CircR { CircR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& self) -> PincR { PincR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& self) -> MincR { MincR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& self) -> PsizeR { PsizeR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& self) -> MsizeR { MsizeR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& self) -> PincosR { PincosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& self) -> PlR { PlR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& self) -> DbmR { DbmR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& self) -> CtR { CtR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& self) -> PburstR { PburstR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& self) -> MburstR { MburstR :: new (((self . bits >> 23) & 3) as u8) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& self) -> ChselR { ChselR :: new (((self . bits >> 25) & 7) as u8) } } impl W { # [doc = "Bit 0 - Stream enable / flag stream ready when read low"] # [inline (always)] pub fn en (& mut self) -> EnW < CrSpec > { EnW :: new (self , 0) } # [doc = "Bit 1 - Direct mode error interrupt enable"] # [inline (always)] pub fn dmeie (& mut self) -> DmeieW < CrSpec > { DmeieW :: new (self , 1) } # [doc = "Bit 2 - Transfer error interrupt enable"] # [inline (always)] pub fn teie (& mut self) -> TeieW < CrSpec > { TeieW :: new (self , 2) } # [doc = "Bit 3 - Half transfer interrupt enable"] # [inline (always)] pub fn htie (& mut self) -> HtieW < CrSpec > { HtieW :: new (self , 3) } # [doc = "Bit 4 - Transfer complete interrupt enable"] # [inline (always)] pub fn tcie (& mut self) -> TcieW < CrSpec > { TcieW :: new (self , 4) } # [doc = "Bit 5 - Peripheral flow controller"] # [inline (always)] pub fn pfctrl (& mut self) -> PfctrlW < CrSpec > { PfctrlW :: new (self , 5) } # [doc = "Bits 6:7 - Data transfer direction"] # [inline (always)] pub fn dir (& mut self) -> DirW < CrSpec > { DirW :: new (self , 6) } # [doc = "Bit 8 - Circular mode"] # [inline (always)] pub fn circ (& mut self) -> CircW < CrSpec > { CircW :: new (self , 8) } # [doc = "Bit 9 - Peripheral increment mode"] # [inline (always)] pub fn pinc (& mut self) -> PincW < CrSpec > { PincW :: new (self , 9) } # [doc = "Bit 10 - Memory increment mode"] # [inline (always)] pub fn minc (& mut self) -> MincW < CrSpec > { MincW :: new (self , 10) } # [doc = "Bits 11:12 - Peripheral data size"] # [inline (always)] pub fn psize (& mut self) -> PsizeW < CrSpec > { PsizeW :: new (self , 11) } # [doc = "Bits 13:14 - Memory data size"] # [inline (always)] pub fn msize (& mut self) -> MsizeW < CrSpec > { MsizeW :: new (self , 13) } # [doc = "Bit 15 - Peripheral increment offset size"] # [inline (always)] pub fn pincos (& mut self) -> PincosW < CrSpec > { PincosW :: new (self , 15) } # [doc = "Bits 16:17 - Priority level"] # [inline (always)] pub fn pl (& mut self) -> PlW < CrSpec > { PlW :: new (self , 16) } # [doc = "Bit 18 - Double buffer mode"] # [inline (always)] pub fn dbm (& mut self) -> DbmW < CrSpec > { DbmW :: new (self , 18) } # [doc = "Bit 19 - Current target (only in double buffer mode)"] # [inline (always)] pub fn ct (& mut self) -> CtW < CrSpec > { CtW :: new (self , 19) } # [doc = "Bits 21:22 - Peripheral burst transfer configuration"] # [inline (always)] pub fn pburst (& mut self) -> PburstW < CrSpec > { PburstW :: new (self , 21) } # [doc = "Bits 23:24 - Memory burst transfer configuration"] # [inline (always)] pub fn mburst (& mut self) -> MburstW < CrSpec > { MburstW :: new (self , 23) } # [doc = "Bits 25:27 - Channel selection"] # [inline (always)] pub fn chsel (& mut self) -> ChselW <'_, CrSpec > { ChselW :: new (self , 25) } } # [doc = "stream x configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/ndtr.rs:1:682 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn ndt (& mut self) -> NdtW < NdtrSpec > { NdtW :: new (self , 0) } } # [doc = "stream x number of data regi... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `NDTR` reader"] pub type R = crate :: R < NdtrSpec > ; # [doc = "Register `NDTR` writer"] pub type W = crate :: W < NdtrSpec > ; # [doc = "Field `NDT` reader - Number of data items to transfer"] pub type NdtR = crate :: FieldReader < u16 > ; # [doc = "Field `NDT` writer - Number of data items to transfer"] pub type NdtW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 , crate :: Safe > ; impl R { # [doc = "Bits 0:15 - Number of data items to transfer"] # [inline (always)] pub fn ndt (& self) -> NdtR { NdtR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Number of data items to transfer"] # [inline (always)] pub fn ndt (& mut self) -> NdtW <'_, NdtrSpec > { NdtW :: new (self , 0) } } # [doc = "stream x number of data register\n\nYou can [`read`](crate::Reg::read) this register and get [`ndtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ndtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NdtrSpec ; impl crate :: RegisterSpec for NdtrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ndtr::R`](R) reader structure"] impl crate :: Readable for NdtrSpec { } # [doc = "`write(|w| ..)` method takes [`ndtr::W`](W) writer structure"] impl crate :: Writable for NdtrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets NDTR to value 0"] impl crate :: Resettable for NdtrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/par.rs:1:580 [INFO] [stdout] | [INFO] [stdout] 1 | ...s"] # [inline (always)] pub fn pa (& mut self) -> PaW < ParSpec > { PaW :: new (self , 0) } } # [doc = "stream x peripheral address re... [INFO] [stdout] | ^^^^^^^^^^ --------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PAR` reader"] pub type R = crate :: R < ParSpec > ; # [doc = "Register `PAR` writer"] pub type W = crate :: W < ParSpec > ; # [doc = "Field `PA` reader - Peripheral address"] pub type PaR = crate :: FieldReader < u32 > ; # [doc = "Field `PA` writer - Peripheral address"] pub type PaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Peripheral address"] # [inline (always)] pub fn pa (& self) -> PaR { PaR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Peripheral address"] # [inline (always)] pub fn pa (& mut self) -> PaW <'_, ParSpec > { PaW :: new (self , 0) } } # [doc = "stream x peripheral address register\n\nYou can [`read`](crate::Reg::read) this register and get [`par::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`par::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ParSpec ; impl crate :: RegisterSpec for ParSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`par::R`](R) reader structure"] impl crate :: Readable for ParSpec { } # [doc = "`write(|w| ..)` method takes [`par::W`](W) writer structure"] impl crate :: Writable for ParSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PAR to value 0"] impl crate :: Resettable for ParSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/m0ar.rs:1:584 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn m0a (& mut self) -> M0aW < M0arSpec > { M0aW :: new (self , 0) } } # [doc = "stream x memory 0 address re... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `M0AR` reader"] pub type R = crate :: R < M0arSpec > ; # [doc = "Register `M0AR` writer"] pub type W = crate :: W < M0arSpec > ; # [doc = "Field `M0A` reader - Memory 0 address"] pub type M0aR = crate :: FieldReader < u32 > ; # [doc = "Field `M0A` writer - Memory 0 address"] pub type M0aW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Memory 0 address"] # [inline (always)] pub fn m0a (& self) -> M0aR { M0aR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Memory 0 address"] # [inline (always)] pub fn m0a (& mut self) -> M0aW <'_, M0arSpec > { M0aW :: new (self , 0) } } # [doc = "stream x memory 0 address register\n\nYou can [`read`](crate::Reg::read) this register and get [`m0ar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m0ar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct M0arSpec ; impl crate :: RegisterSpec for M0arSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`m0ar::R`](R) reader structure"] impl crate :: Readable for M0arSpec { } # [doc = "`write(|w| ..)` method takes [`m0ar::W`](W) writer structure"] impl crate :: Writable for M0arSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets M0AR to value 0"] impl crate :: Resettable for M0arSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/m1ar.rs:1:732 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn m1a (& mut self) -> M1aW < M1arSpec > { M1aW :: new (self , 0) } } # [doc = "stream x memory 1 address re... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `M1AR` reader"] pub type R = crate :: R < M1arSpec > ; # [doc = "Register `M1AR` writer"] pub type W = crate :: W < M1arSpec > ; # [doc = "Field `M1A` reader - Memory 1 address (used in case of Double buffer mode)"] pub type M1aR = crate :: FieldReader < u32 > ; # [doc = "Field `M1A` writer - Memory 1 address (used in case of Double buffer mode)"] pub type M1aW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"] # [inline (always)] pub fn m1a (& self) -> M1aR { M1aR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"] # [inline (always)] pub fn m1a (& mut self) -> M1aW <'_, M1arSpec > { M1aW :: new (self , 0) } } # [doc = "stream x memory 1 address register\n\nYou can [`read`](crate::Reg::read) this register and get [`m1ar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m1ar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct M1arSpec ; impl crate :: RegisterSpec for M1arSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`m1ar::R`](R) reader structure"] impl crate :: Readable for M1arSpec { } # [doc = "`write(|w| ..)` method takes [`m1ar::W`](W) writer structure"] impl crate :: Writable for M1arSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets M1AR to value 0"] impl crate :: Resettable for M1arSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/fcr.rs:1:7403 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn fth (& mut self) -> FthW < FcrSpec > { FthW :: new (self , 0) } # [doc = "Bit 2 - Direct mode disable"] ... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FCR` reader"] pub type R = crate :: R < FcrSpec > ; # [doc = "Register `FCR` writer"] pub type W = crate :: W < FcrSpec > ; # [doc = "FIFO threshold selection\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Fth { # [doc = "0: 1/4 full FIFO"] Quarter = 0 , # [doc = "1: 1/2 full FIFO"] Half = 1 , # [doc = "2: 3/4 full FIFO"] ThreeQuarters = 2 , # [doc = "3: Full FIFO"] Full = 3 , } impl From < Fth > for u8 { # [inline (always)] fn from (variant : Fth) -> Self { variant as _ } } impl crate :: FieldSpec for Fth { type Ux = u8 ; } impl crate :: IsEnum for Fth { } # [doc = "Field `FTH` reader - FIFO threshold selection"] pub type FthR = crate :: FieldReader < Fth > ; impl FthR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Fth { match self . bits { 0 => Fth :: Quarter , 1 => Fth :: Half , 2 => Fth :: ThreeQuarters , 3 => Fth :: Full , _ => unreachable ! () , } } # [doc = "1/4 full FIFO"] # [inline (always)] pub fn is_quarter (& self) -> bool { * self == Fth :: Quarter } # [doc = "1/2 full FIFO"] # [inline (always)] pub fn is_half (& self) -> bool { * self == Fth :: Half } # [doc = "3/4 full FIFO"] # [inline (always)] pub fn is_three_quarters (& self) -> bool { * self == Fth :: ThreeQuarters } # [doc = "Full FIFO"] # [inline (always)] pub fn is_full (& self) -> bool { * self == Fth :: Full } } # [doc = "Field `FTH` writer - FIFO threshold selection"] pub type FthW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Fth , crate :: Safe > ; impl < 'a , REG > FthW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "1/4 full FIFO"] # [inline (always)] pub fn quarter (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: Quarter) } # [doc = "1/2 full FIFO"] # [inline (always)] pub fn half (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: Half) } # [doc = "3/4 full FIFO"] # [inline (always)] pub fn three_quarters (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: ThreeQuarters) } # [doc = "Full FIFO"] # [inline (always)] pub fn full (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: Full) } } # [doc = "Direct mode disable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmdis { # [doc = "0: Direct mode is enabled"] Enabled = 0 , # [doc = "1: Direct mode is disabled"] Disabled = 1 , } impl From < Dmdis > for bool { # [inline (always)] fn from (variant : Dmdis) -> Self { variant as u8 != 0 } } # [doc = "Field `DMDIS` reader - Direct mode disable"] pub type DmdisR = crate :: BitReader < Dmdis > ; impl DmdisR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmdis { match self . bits { false => Dmdis :: Enabled , true => Dmdis :: Disabled , } } # [doc = "Direct mode is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmdis :: Enabled } # [doc = "Direct mode is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmdis :: Disabled } } # [doc = "Field `DMDIS` writer - Direct mode disable"] pub type DmdisW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmdis > ; impl < 'a , REG > DmdisW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Direct mode is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmdis :: Enabled) } # [doc = "Direct mode is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmdis :: Disabled) } } # [doc = "FIFO status\n\nValue on reset: 4"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Fs { # [doc = "0: 0 < fifo_level < 1/4"] Quarter1 = 0 , # [doc = "1: 1/4 <= fifo_level < 1/2"] Quarter2 = 1 , # [doc = "2: 1/2 <= fifo_level < 3/4"] Quarter3 = 2 , # [doc = "3: 3/4 <= fifo_level < full"] Quarter4 = 3 , # [doc = "4: FIFO is empty"] Empty = 4 , # [doc = "5: FIFO is full"] Full = 5 , } impl From < Fs > for u8 { # [inline (always)] fn from (variant : Fs) -> Self { variant as _ } } impl crate :: FieldSpec for Fs { type Ux = u8 ; } impl crate :: IsEnum for Fs { } # [doc = "Field `FS` reader - FIFO status"] pub type FsR = crate :: FieldReader < Fs > ; impl FsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Fs > { match self . bits { 0 => Some (Fs :: Quarter1) , 1 => Some (Fs :: Quarter2) , 2 => Some (Fs :: Quarter3) , 3 => Some (Fs :: Quarter4) , 4 => Some (Fs :: Empty) , 5 => Some (Fs :: Full) , _ => None , } } # [doc = "0 < fifo_level < 1/4"] # [inline (always)] pub fn is_quarter1 (& self) -> bool { * self == Fs :: Quarter1 } # [doc = "1/4 <= fifo_level < 1/2"] # [inline (always)] pub fn is_quarter2 (& self) -> bool { * self == Fs :: Quarter2 } # [doc = "1/2 <= fifo_level < 3/4"] # [inline (always)] pub fn is_quarter3 (& self) -> bool { * self == Fs :: Quarter3 } # [doc = "3/4 <= fifo_level < full"] # [inline (always)] pub fn is_quarter4 (& self) -> bool { * self == Fs :: Quarter4 } # [doc = "FIFO is empty"] # [inline (always)] pub fn is_empty (& self) -> bool { * self == Fs :: Empty } # [doc = "FIFO is full"] # [inline (always)] pub fn is_full (& self) -> bool { * self == Fs :: Full } } # [doc = "FIFO error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Feie { # [doc = "0: FE interrupt disabled"] Disabled = 0 , # [doc = "1: FE interrupt enabled"] Enabled = 1 , } impl From < Feie > for bool { # [inline (always)] fn from (variant : Feie) -> Self { variant as u8 != 0 } } # [doc = "Field `FEIE` reader - FIFO error interrupt enable"] pub type FeieR = crate :: BitReader < Feie > ; impl FeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Feie { match self . bits { false => Feie :: Disabled , true => Feie :: Enabled , } } # [doc = "FE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Feie :: Disabled } # [doc = "FE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Feie :: Enabled } } # [doc = "Field `FEIE` writer - FIFO error interrupt enable"] pub type FeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Feie > ; impl < 'a , REG > FeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "FE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Feie :: Disabled) } # [doc = "FE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Feie :: Enabled) } } impl R { # [doc = "Bits 0:1 - FIFO threshold selection"] # [inline (always)] pub fn fth (& self) -> FthR { FthR :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Direct mode disable"] # [inline (always)] pub fn dmdis (& self) -> DmdisR { DmdisR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:5 - FIFO status"] # [inline (always)] pub fn fs (& self) -> FsR { FsR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bit 7 - FIFO error interrupt enable"] # [inline (always)] pub fn feie (& self) -> FeieR { FeieR :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - FIFO threshold selection"] # [inline (always)] pub fn fth (& mut self) -> FthW <'_, FcrSpec > { FthW :: new (self , 0) } # [doc = "Bit 2 - Direct mode disable"] # [inline (always)] pub fn dmdis (& mut self) -> DmdisW < FcrSpec > { DmdisW :: new (self , 2) } # [doc = "Bit 7 - FIFO error interrupt enable"] # [inline (always)] pub fn feie (& mut self) -> FeieW < FcrSpec > { FeieW :: new (self , 7) } } # [doc = "stream x FIFO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`fcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FcrSpec ; impl crate :: RegisterSpec for FcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fcr::R`](R) reader structure"] impl crate :: Readable for FcrSpec { } # [doc = "`write(|w| ..)` method takes [`fcr::W`](W) writer structure"] impl crate :: Writable for FcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets FCR to value 0x21"] impl crate :: Resettable for FcrSpec { const RESET_VALUE : u32 = 0x21 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/fcr.rs:1:7536 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn dmdis (& mut self) -> DmdisW < FcrSpec > { DmdisW :: new (self , 2) } # [doc = "Bit 7 - FIFO error interrup... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FCR` reader"] pub type R = crate :: R < FcrSpec > ; # [doc = "Register `FCR` writer"] pub type W = crate :: W < FcrSpec > ; # [doc = "FIFO threshold selection\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Fth { # [doc = "0: 1/4 full FIFO"] Quarter = 0 , # [doc = "1: 1/2 full FIFO"] Half = 1 , # [doc = "2: 3/4 full FIFO"] ThreeQuarters = 2 , # [doc = "3: Full FIFO"] Full = 3 , } impl From < Fth > for u8 { # [inline (always)] fn from (variant : Fth) -> Self { variant as _ } } impl crate :: FieldSpec for Fth { type Ux = u8 ; } impl crate :: IsEnum for Fth { } # [doc = "Field `FTH` reader - FIFO threshold selection"] pub type FthR = crate :: FieldReader < Fth > ; impl FthR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Fth { match self . bits { 0 => Fth :: Quarter , 1 => Fth :: Half , 2 => Fth :: ThreeQuarters , 3 => Fth :: Full , _ => unreachable ! () , } } # [doc = "1/4 full FIFO"] # [inline (always)] pub fn is_quarter (& self) -> bool { * self == Fth :: Quarter } # [doc = "1/2 full FIFO"] # [inline (always)] pub fn is_half (& self) -> bool { * self == Fth :: Half } # [doc = "3/4 full FIFO"] # [inline (always)] pub fn is_three_quarters (& self) -> bool { * self == Fth :: ThreeQuarters } # [doc = "Full FIFO"] # [inline (always)] pub fn is_full (& self) -> bool { * self == Fth :: Full } } # [doc = "Field `FTH` writer - FIFO threshold selection"] pub type FthW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Fth , crate :: Safe > ; impl < 'a , REG > FthW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "1/4 full FIFO"] # [inline (always)] pub fn quarter (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: Quarter) } # [doc = "1/2 full FIFO"] # [inline (always)] pub fn half (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: Half) } # [doc = "3/4 full FIFO"] # [inline (always)] pub fn three_quarters (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: ThreeQuarters) } # [doc = "Full FIFO"] # [inline (always)] pub fn full (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: Full) } } # [doc = "Direct mode disable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmdis { # [doc = "0: Direct mode is enabled"] Enabled = 0 , # [doc = "1: Direct mode is disabled"] Disabled = 1 , } impl From < Dmdis > for bool { # [inline (always)] fn from (variant : Dmdis) -> Self { variant as u8 != 0 } } # [doc = "Field `DMDIS` reader - Direct mode disable"] pub type DmdisR = crate :: BitReader < Dmdis > ; impl DmdisR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmdis { match self . bits { false => Dmdis :: Enabled , true => Dmdis :: Disabled , } } # [doc = "Direct mode is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmdis :: Enabled } # [doc = "Direct mode is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmdis :: Disabled } } # [doc = "Field `DMDIS` writer - Direct mode disable"] pub type DmdisW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmdis > ; impl < 'a , REG > DmdisW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Direct mode is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmdis :: Enabled) } # [doc = "Direct mode is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmdis :: Disabled) } } # [doc = "FIFO status\n\nValue on reset: 4"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Fs { # [doc = "0: 0 < fifo_level < 1/4"] Quarter1 = 0 , # [doc = "1: 1/4 <= fifo_level < 1/2"] Quarter2 = 1 , # [doc = "2: 1/2 <= fifo_level < 3/4"] Quarter3 = 2 , # [doc = "3: 3/4 <= fifo_level < full"] Quarter4 = 3 , # [doc = "4: FIFO is empty"] Empty = 4 , # [doc = "5: FIFO is full"] Full = 5 , } impl From < Fs > for u8 { # [inline (always)] fn from (variant : Fs) -> Self { variant as _ } } impl crate :: FieldSpec for Fs { type Ux = u8 ; } impl crate :: IsEnum for Fs { } # [doc = "Field `FS` reader - FIFO status"] pub type FsR = crate :: FieldReader < Fs > ; impl FsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Fs > { match self . bits { 0 => Some (Fs :: Quarter1) , 1 => Some (Fs :: Quarter2) , 2 => Some (Fs :: Quarter3) , 3 => Some (Fs :: Quarter4) , 4 => Some (Fs :: Empty) , 5 => Some (Fs :: Full) , _ => None , } } # [doc = "0 < fifo_level < 1/4"] # [inline (always)] pub fn is_quarter1 (& self) -> bool { * self == Fs :: Quarter1 } # [doc = "1/4 <= fifo_level < 1/2"] # [inline (always)] pub fn is_quarter2 (& self) -> bool { * self == Fs :: Quarter2 } # [doc = "1/2 <= fifo_level < 3/4"] # [inline (always)] pub fn is_quarter3 (& self) -> bool { * self == Fs :: Quarter3 } # [doc = "3/4 <= fifo_level < full"] # [inline (always)] pub fn is_quarter4 (& self) -> bool { * self == Fs :: Quarter4 } # [doc = "FIFO is empty"] # [inline (always)] pub fn is_empty (& self) -> bool { * self == Fs :: Empty } # [doc = "FIFO is full"] # [inline (always)] pub fn is_full (& self) -> bool { * self == Fs :: Full } } # [doc = "FIFO error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Feie { # [doc = "0: FE interrupt disabled"] Disabled = 0 , # [doc = "1: FE interrupt enabled"] Enabled = 1 , } impl From < Feie > for bool { # [inline (always)] fn from (variant : Feie) -> Self { variant as u8 != 0 } } # [doc = "Field `FEIE` reader - FIFO error interrupt enable"] pub type FeieR = crate :: BitReader < Feie > ; impl FeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Feie { match self . bits { false => Feie :: Disabled , true => Feie :: Enabled , } } # [doc = "FE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Feie :: Disabled } # [doc = "FE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Feie :: Enabled } } # [doc = "Field `FEIE` writer - FIFO error interrupt enable"] pub type FeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Feie > ; impl < 'a , REG > FeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "FE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Feie :: Disabled) } # [doc = "FE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Feie :: Enabled) } } impl R { # [doc = "Bits 0:1 - FIFO threshold selection"] # [inline (always)] pub fn fth (& self) -> FthR { FthR :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Direct mode disable"] # [inline (always)] pub fn dmdis (& self) -> DmdisR { DmdisR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:5 - FIFO status"] # [inline (always)] pub fn fs (& self) -> FsR { FsR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bit 7 - FIFO error interrupt enable"] # [inline (always)] pub fn feie (& self) -> FeieR { FeieR :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - FIFO threshold selection"] # [inline (always)] pub fn fth (& mut self) -> FthW < FcrSpec > { FthW :: new (self , 0) } # [doc = "Bit 2 - Direct mode disable"] # [inline (always)] pub fn dmdis (& mut self) -> DmdisW <'_, FcrSpec > { DmdisW :: new (self , 2) } # [doc = "Bit 7 - FIFO error interrupt enable"] # [inline (always)] pub fn feie (& mut self) -> FeieW < FcrSpec > { FeieW :: new (self , 7) } } # [doc = "stream x FIFO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`fcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FcrSpec ; impl crate :: RegisterSpec for FcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fcr::R`](R) reader structure"] impl crate :: Readable for FcrSpec { } # [doc = "`write(|w| ..)` method takes [`fcr::W`](W) writer structure"] impl crate :: Writable for FcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets FCR to value 0x21"] impl crate :: Resettable for FcrSpec { const RESET_VALUE : u32 = 0x21 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dma2/st/fcr.rs:1:7680 [INFO] [stdout] | [INFO] [stdout] 1 | ... # [inline (always)] pub fn feie (& mut self) -> FeieW < FcrSpec > { FeieW :: new (self , 7) } } # [doc = "stream x FIFO control regis... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `FCR` reader"] pub type R = crate :: R < FcrSpec > ; # [doc = "Register `FCR` writer"] pub type W = crate :: W < FcrSpec > ; # [doc = "FIFO threshold selection\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Fth { # [doc = "0: 1/4 full FIFO"] Quarter = 0 , # [doc = "1: 1/2 full FIFO"] Half = 1 , # [doc = "2: 3/4 full FIFO"] ThreeQuarters = 2 , # [doc = "3: Full FIFO"] Full = 3 , } impl From < Fth > for u8 { # [inline (always)] fn from (variant : Fth) -> Self { variant as _ } } impl crate :: FieldSpec for Fth { type Ux = u8 ; } impl crate :: IsEnum for Fth { } # [doc = "Field `FTH` reader - FIFO threshold selection"] pub type FthR = crate :: FieldReader < Fth > ; impl FthR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Fth { match self . bits { 0 => Fth :: Quarter , 1 => Fth :: Half , 2 => Fth :: ThreeQuarters , 3 => Fth :: Full , _ => unreachable ! () , } } # [doc = "1/4 full FIFO"] # [inline (always)] pub fn is_quarter (& self) -> bool { * self == Fth :: Quarter } # [doc = "1/2 full FIFO"] # [inline (always)] pub fn is_half (& self) -> bool { * self == Fth :: Half } # [doc = "3/4 full FIFO"] # [inline (always)] pub fn is_three_quarters (& self) -> bool { * self == Fth :: ThreeQuarters } # [doc = "Full FIFO"] # [inline (always)] pub fn is_full (& self) -> bool { * self == Fth :: Full } } # [doc = "Field `FTH` writer - FIFO threshold selection"] pub type FthW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Fth , crate :: Safe > ; impl < 'a , REG > FthW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "1/4 full FIFO"] # [inline (always)] pub fn quarter (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: Quarter) } # [doc = "1/2 full FIFO"] # [inline (always)] pub fn half (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: Half) } # [doc = "3/4 full FIFO"] # [inline (always)] pub fn three_quarters (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: ThreeQuarters) } # [doc = "Full FIFO"] # [inline (always)] pub fn full (self) -> & 'a mut crate :: W < REG > { self . variant (Fth :: Full) } } # [doc = "Direct mode disable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Dmdis { # [doc = "0: Direct mode is enabled"] Enabled = 0 , # [doc = "1: Direct mode is disabled"] Disabled = 1 , } impl From < Dmdis > for bool { # [inline (always)] fn from (variant : Dmdis) -> Self { variant as u8 != 0 } } # [doc = "Field `DMDIS` reader - Direct mode disable"] pub type DmdisR = crate :: BitReader < Dmdis > ; impl DmdisR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Dmdis { match self . bits { false => Dmdis :: Enabled , true => Dmdis :: Disabled , } } # [doc = "Direct mode is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Dmdis :: Enabled } # [doc = "Direct mode is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Dmdis :: Disabled } } # [doc = "Field `DMDIS` writer - Direct mode disable"] pub type DmdisW < 'a , REG > = crate :: BitWriter < 'a , REG , Dmdis > ; impl < 'a , REG > DmdisW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Direct mode is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmdis :: Enabled) } # [doc = "Direct mode is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Dmdis :: Disabled) } } # [doc = "FIFO status\n\nValue on reset: 4"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Fs { # [doc = "0: 0 < fifo_level < 1/4"] Quarter1 = 0 , # [doc = "1: 1/4 <= fifo_level < 1/2"] Quarter2 = 1 , # [doc = "2: 1/2 <= fifo_level < 3/4"] Quarter3 = 2 , # [doc = "3: 3/4 <= fifo_level < full"] Quarter4 = 3 , # [doc = "4: FIFO is empty"] Empty = 4 , # [doc = "5: FIFO is full"] Full = 5 , } impl From < Fs > for u8 { # [inline (always)] fn from (variant : Fs) -> Self { variant as _ } } impl crate :: FieldSpec for Fs { type Ux = u8 ; } impl crate :: IsEnum for Fs { } # [doc = "Field `FS` reader - FIFO status"] pub type FsR = crate :: FieldReader < Fs > ; impl FsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Fs > { match self . bits { 0 => Some (Fs :: Quarter1) , 1 => Some (Fs :: Quarter2) , 2 => Some (Fs :: Quarter3) , 3 => Some (Fs :: Quarter4) , 4 => Some (Fs :: Empty) , 5 => Some (Fs :: Full) , _ => None , } } # [doc = "0 < fifo_level < 1/4"] # [inline (always)] pub fn is_quarter1 (& self) -> bool { * self == Fs :: Quarter1 } # [doc = "1/4 <= fifo_level < 1/2"] # [inline (always)] pub fn is_quarter2 (& self) -> bool { * self == Fs :: Quarter2 } # [doc = "1/2 <= fifo_level < 3/4"] # [inline (always)] pub fn is_quarter3 (& self) -> bool { * self == Fs :: Quarter3 } # [doc = "3/4 <= fifo_level < full"] # [inline (always)] pub fn is_quarter4 (& self) -> bool { * self == Fs :: Quarter4 } # [doc = "FIFO is empty"] # [inline (always)] pub fn is_empty (& self) -> bool { * self == Fs :: Empty } # [doc = "FIFO is full"] # [inline (always)] pub fn is_full (& self) -> bool { * self == Fs :: Full } } # [doc = "FIFO error interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Feie { # [doc = "0: FE interrupt disabled"] Disabled = 0 , # [doc = "1: FE interrupt enabled"] Enabled = 1 , } impl From < Feie > for bool { # [inline (always)] fn from (variant : Feie) -> Self { variant as u8 != 0 } } # [doc = "Field `FEIE` reader - FIFO error interrupt enable"] pub type FeieR = crate :: BitReader < Feie > ; impl FeieR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Feie { match self . bits { false => Feie :: Disabled , true => Feie :: Enabled , } } # [doc = "FE interrupt disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Feie :: Disabled } # [doc = "FE interrupt enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Feie :: Enabled } } # [doc = "Field `FEIE` writer - FIFO error interrupt enable"] pub type FeieW < 'a , REG > = crate :: BitWriter < 'a , REG , Feie > ; impl < 'a , REG > FeieW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "FE interrupt disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Feie :: Disabled) } # [doc = "FE interrupt enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Feie :: Enabled) } } impl R { # [doc = "Bits 0:1 - FIFO threshold selection"] # [inline (always)] pub fn fth (& self) -> FthR { FthR :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Direct mode disable"] # [inline (always)] pub fn dmdis (& self) -> DmdisR { DmdisR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:5 - FIFO status"] # [inline (always)] pub fn fs (& self) -> FsR { FsR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bit 7 - FIFO error interrupt enable"] # [inline (always)] pub fn feie (& self) -> FeieR { FeieR :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - FIFO threshold selection"] # [inline (always)] pub fn fth (& mut self) -> FthW < FcrSpec > { FthW :: new (self , 0) } # [doc = "Bit 2 - Direct mode disable"] # [inline (always)] pub fn dmdis (& mut self) -> DmdisW < FcrSpec > { DmdisW :: new (self , 2) } # [doc = "Bit 7 - FIFO error interrupt enable"] # [inline (always)] pub fn feie (& mut self) -> FeieW <'_, FcrSpec > { FeieW :: new (self , 7) } } # [doc = "stream x FIFO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`fcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FcrSpec ; impl crate :: RegisterSpec for FcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fcr::R`](R) reader structure"] impl crate :: Readable for FcrSpec { } # [doc = "`write(|w| ..)` method takes [`fcr::W`](W) writer structure"] impl crate :: Writable for FcrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets FCR to value 0x21"] impl crate :: Resettable for FcrSpec { const RESET_VALUE : u32 = 0x21 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cr.rs:1:8661 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn hsion (& mut self) -> HsionW < CrSpec > { HsionW :: new (self , 0) } # [doc = "Bits 3:7 - Internal high-spe... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Internal high-speed clock enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsion { # [doc = "0: Clock Off"] Off = 0 , # [doc = "1: Clock On"] On = 1 , } impl From < Hsion > for bool { # [inline (always)] fn from (variant : Hsion) -> Self { variant as u8 != 0 } } # [doc = "Field `HSION` reader - Internal high-speed clock enable"] pub type HsionR = crate :: BitReader < Hsion > ; impl HsionR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsion { match self . bits { false => Hsion :: Off , true => Hsion :: On , } } # [doc = "Clock Off"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Hsion :: Off } # [doc = "Clock On"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Hsion :: On } } # [doc = "Field `HSION` writer - Internal high-speed clock enable"] pub type HsionW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsion > ; impl < 'a , REG > HsionW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock Off"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: Off) } # [doc = "Clock On"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: On) } } # [doc = "Internal high-speed clock ready flag\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsirdyr { # [doc = "0: Clock not ready"] NotReady = 0 , # [doc = "1: Clock ready"] Ready = 1 , } impl From < Hsirdyr > for bool { # [inline (always)] fn from (variant : Hsirdyr) -> Self { variant as u8 != 0 } } # [doc = "Field `HSIRDY` reader - Internal high-speed clock ready flag"] pub type HsirdyR = crate :: BitReader < Hsirdyr > ; impl HsirdyR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsirdyr { match self . bits { false => Hsirdyr :: NotReady , true => Hsirdyr :: Ready , } } # [doc = "Clock not ready"] # [inline (always)] pub fn is_not_ready (& self) -> bool { * self == Hsirdyr :: NotReady } # [doc = "Clock ready"] # [inline (always)] pub fn is_ready (& self) -> bool { * self == Hsirdyr :: Ready } } # [doc = "Field `HSITRIM` reader - Internal high-speed clock trimming"] pub type HsitrimR = crate :: FieldReader ; # [doc = "Field `HSITRIM` writer - Internal high-speed clock trimming"] pub type HsitrimW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Field `HSICAL` reader - Internal high-speed clock calibration"] pub type HsicalR = crate :: FieldReader ; # [doc = "Field `HSEON` reader - HSE clock enable"] pub use HsionR as HseonR ; # [doc = "Field `HSEON` writer - HSE clock enable"] pub use HsionW as HseonW ; # [doc = "Field `HSERDY` reader - HSE clock ready flag"] pub use HsirdyR as HserdyR ; # [doc = "HSE clock bypass\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsebyp { # [doc = "0: HSE crystal oscillator not bypassed"] NotBypassed = 0 , # [doc = "1: HSE crystal oscillator bypassed with external clock"] Bypassed = 1 , } impl From < Hsebyp > for bool { # [inline (always)] fn from (variant : Hsebyp) -> Self { variant as u8 != 0 } } # [doc = "Field `HSEBYP` reader - HSE clock bypass"] pub type HsebypR = crate :: BitReader < Hsebyp > ; impl HsebypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsebyp { match self . bits { false => Hsebyp :: NotBypassed , true => Hsebyp :: Bypassed , } } # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn is_not_bypassed (& self) -> bool { * self == Hsebyp :: NotBypassed } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn is_bypassed (& self) -> bool { * self == Hsebyp :: Bypassed } } # [doc = "Field `HSEBYP` writer - HSE clock bypass"] pub type HsebypW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsebyp > ; impl < 'a , REG > HsebypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn not_bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: NotBypassed) } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: Bypassed) } } # [doc = "Clock security system enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Csson { # [doc = "0: Clock security system disabled (clock detector OFF)"] Off = 0 , # [doc = "1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] On = 1 , } impl From < Csson > for bool { # [inline (always)] fn from (variant : Csson) -> Self { variant as u8 != 0 } } # [doc = "Field `CSSON` reader - Clock security system enable"] pub type CssonR = crate :: BitReader < Csson > ; impl CssonR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Csson { match self . bits { false => Csson :: Off , true => Csson :: On , } } # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Csson :: Off } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Csson :: On } } # [doc = "Field `CSSON` writer - Clock security system enable"] pub type CssonW < 'a , REG > = crate :: BitWriter < 'a , REG , Csson > ; impl < 'a , REG > CssonW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: Off) } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: On) } } # [doc = "Field `PLLON` reader - Main PLL (PLL) enable"] pub use HsionR as PllonR ; # [doc = "Field `PLLON` writer - Main PLL (PLL) enable"] pub use HsionW as PllonW ; # [doc = "Field `PLLRDY` reader - Main PLL (PLL) clock ready flag"] pub use HsirdyR as PllrdyR ; # [doc = "Field `PLLI2SON` reader - PLLI2S enable"] pub use HsionR as Plli2sonR ; # [doc = "Field `PLLI2SON` writer - PLLI2S enable"] pub use HsionW as Plli2sonW ; # [doc = "Field `PLLI2SRDY` reader - PLLI2S clock ready flag"] pub use HsirdyR as Plli2srdyR ; impl R { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& self) -> HsionR { HsionR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Internal high-speed clock ready flag"] # [inline (always)] pub fn hsirdy (& self) -> HsirdyR { HsirdyR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& self) -> HsitrimR { HsitrimR :: new (((self . bits >> 3) & 0x1f) as u8) } # [doc = "Bits 8:15 - Internal high-speed clock calibration"] # [inline (always)] pub fn hsical (& self) -> HsicalR { HsicalR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& self) -> HseonR { HseonR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - HSE clock ready flag"] # [inline (always)] pub fn hserdy (& self) -> HserdyR { HserdyR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& self) -> HsebypR { HsebypR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& self) -> CssonR { CssonR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& self) -> PllonR { PllonR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Main PLL (PLL) clock ready flag"] # [inline (always)] pub fn pllrdy (& self) -> PllrdyR { PllrdyR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& self) -> Plli2sonR { Plli2sonR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - PLLI2S clock ready flag"] # [inline (always)] pub fn plli2srdy (& self) -> Plli2srdyR { Plli2srdyR :: new (((self . bits >> 27) & 1) != 0) } } impl W { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& mut self) -> HsionW <'_, CrSpec > { HsionW :: new (self , 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& mut self) -> HsitrimW < CrSpec > { HsitrimW :: new (self , 3) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& mut self) -> HseonW < CrSpec > { HseonW :: new (self , 16) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& mut self) -> HsebypW < CrSpec > { HsebypW :: new (self , 18) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& mut self) -> CssonW < CrSpec > { CssonW :: new (self , 19) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& mut self) -> PllonW < CrSpec > { PllonW :: new (self , 24) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& mut self) -> Plli2sonW < CrSpec > { Plli2sonW :: new (self , 26) } } # [doc = "clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0x83"] impl crate :: Resettable for CrSpec { const RESET_VALUE : u32 = 0x83 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cr.rs:1:8817 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn hsitrim (& mut self) -> HsitrimW < CrSpec > { HsitrimW :: new (self , 3) } # [doc = "Bit 16 - HSE clock enable... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Internal high-speed clock enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsion { # [doc = "0: Clock Off"] Off = 0 , # [doc = "1: Clock On"] On = 1 , } impl From < Hsion > for bool { # [inline (always)] fn from (variant : Hsion) -> Self { variant as u8 != 0 } } # [doc = "Field `HSION` reader - Internal high-speed clock enable"] pub type HsionR = crate :: BitReader < Hsion > ; impl HsionR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsion { match self . bits { false => Hsion :: Off , true => Hsion :: On , } } # [doc = "Clock Off"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Hsion :: Off } # [doc = "Clock On"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Hsion :: On } } # [doc = "Field `HSION` writer - Internal high-speed clock enable"] pub type HsionW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsion > ; impl < 'a , REG > HsionW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock Off"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: Off) } # [doc = "Clock On"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: On) } } # [doc = "Internal high-speed clock ready flag\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsirdyr { # [doc = "0: Clock not ready"] NotReady = 0 , # [doc = "1: Clock ready"] Ready = 1 , } impl From < Hsirdyr > for bool { # [inline (always)] fn from (variant : Hsirdyr) -> Self { variant as u8 != 0 } } # [doc = "Field `HSIRDY` reader - Internal high-speed clock ready flag"] pub type HsirdyR = crate :: BitReader < Hsirdyr > ; impl HsirdyR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsirdyr { match self . bits { false => Hsirdyr :: NotReady , true => Hsirdyr :: Ready , } } # [doc = "Clock not ready"] # [inline (always)] pub fn is_not_ready (& self) -> bool { * self == Hsirdyr :: NotReady } # [doc = "Clock ready"] # [inline (always)] pub fn is_ready (& self) -> bool { * self == Hsirdyr :: Ready } } # [doc = "Field `HSITRIM` reader - Internal high-speed clock trimming"] pub type HsitrimR = crate :: FieldReader ; # [doc = "Field `HSITRIM` writer - Internal high-speed clock trimming"] pub type HsitrimW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Field `HSICAL` reader - Internal high-speed clock calibration"] pub type HsicalR = crate :: FieldReader ; # [doc = "Field `HSEON` reader - HSE clock enable"] pub use HsionR as HseonR ; # [doc = "Field `HSEON` writer - HSE clock enable"] pub use HsionW as HseonW ; # [doc = "Field `HSERDY` reader - HSE clock ready flag"] pub use HsirdyR as HserdyR ; # [doc = "HSE clock bypass\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsebyp { # [doc = "0: HSE crystal oscillator not bypassed"] NotBypassed = 0 , # [doc = "1: HSE crystal oscillator bypassed with external clock"] Bypassed = 1 , } impl From < Hsebyp > for bool { # [inline (always)] fn from (variant : Hsebyp) -> Self { variant as u8 != 0 } } # [doc = "Field `HSEBYP` reader - HSE clock bypass"] pub type HsebypR = crate :: BitReader < Hsebyp > ; impl HsebypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsebyp { match self . bits { false => Hsebyp :: NotBypassed , true => Hsebyp :: Bypassed , } } # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn is_not_bypassed (& self) -> bool { * self == Hsebyp :: NotBypassed } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn is_bypassed (& self) -> bool { * self == Hsebyp :: Bypassed } } # [doc = "Field `HSEBYP` writer - HSE clock bypass"] pub type HsebypW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsebyp > ; impl < 'a , REG > HsebypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn not_bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: NotBypassed) } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: Bypassed) } } # [doc = "Clock security system enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Csson { # [doc = "0: Clock security system disabled (clock detector OFF)"] Off = 0 , # [doc = "1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] On = 1 , } impl From < Csson > for bool { # [inline (always)] fn from (variant : Csson) -> Self { variant as u8 != 0 } } # [doc = "Field `CSSON` reader - Clock security system enable"] pub type CssonR = crate :: BitReader < Csson > ; impl CssonR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Csson { match self . bits { false => Csson :: Off , true => Csson :: On , } } # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Csson :: Off } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Csson :: On } } # [doc = "Field `CSSON` writer - Clock security system enable"] pub type CssonW < 'a , REG > = crate :: BitWriter < 'a , REG , Csson > ; impl < 'a , REG > CssonW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: Off) } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: On) } } # [doc = "Field `PLLON` reader - Main PLL (PLL) enable"] pub use HsionR as PllonR ; # [doc = "Field `PLLON` writer - Main PLL (PLL) enable"] pub use HsionW as PllonW ; # [doc = "Field `PLLRDY` reader - Main PLL (PLL) clock ready flag"] pub use HsirdyR as PllrdyR ; # [doc = "Field `PLLI2SON` reader - PLLI2S enable"] pub use HsionR as Plli2sonR ; # [doc = "Field `PLLI2SON` writer - PLLI2S enable"] pub use HsionW as Plli2sonW ; # [doc = "Field `PLLI2SRDY` reader - PLLI2S clock ready flag"] pub use HsirdyR as Plli2srdyR ; impl R { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& self) -> HsionR { HsionR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Internal high-speed clock ready flag"] # [inline (always)] pub fn hsirdy (& self) -> HsirdyR { HsirdyR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& self) -> HsitrimR { HsitrimR :: new (((self . bits >> 3) & 0x1f) as u8) } # [doc = "Bits 8:15 - Internal high-speed clock calibration"] # [inline (always)] pub fn hsical (& self) -> HsicalR { HsicalR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& self) -> HseonR { HseonR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - HSE clock ready flag"] # [inline (always)] pub fn hserdy (& self) -> HserdyR { HserdyR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& self) -> HsebypR { HsebypR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& self) -> CssonR { CssonR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& self) -> PllonR { PllonR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Main PLL (PLL) clock ready flag"] # [inline (always)] pub fn pllrdy (& self) -> PllrdyR { PllrdyR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& self) -> Plli2sonR { Plli2sonR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - PLLI2S clock ready flag"] # [inline (always)] pub fn plli2srdy (& self) -> Plli2srdyR { Plli2srdyR :: new (((self . bits >> 27) & 1) != 0) } } impl W { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& mut self) -> HsionW < CrSpec > { HsionW :: new (self , 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& mut self) -> HsitrimW <'_, CrSpec > { HsitrimW :: new (self , 3) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& mut self) -> HseonW < CrSpec > { HseonW :: new (self , 16) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& mut self) -> HsebypW < CrSpec > { HsebypW :: new (self , 18) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& mut self) -> CssonW < CrSpec > { CssonW :: new (self , 19) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& mut self) -> PllonW < CrSpec > { PllonW :: new (self , 24) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& mut self) -> Plli2sonW < CrSpec > { Plli2sonW :: new (self , 26) } } # [doc = "clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0x83"] impl crate :: Resettable for CrSpec { const RESET_VALUE : u32 = 0x83 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cr.rs:1:8955 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn hseon (& mut self) -> HseonW < CrSpec > { HseonW :: new (self , 16) } # [doc = "Bit 18 - HSE clock bypass"]... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Internal high-speed clock enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsion { # [doc = "0: Clock Off"] Off = 0 , # [doc = "1: Clock On"] On = 1 , } impl From < Hsion > for bool { # [inline (always)] fn from (variant : Hsion) -> Self { variant as u8 != 0 } } # [doc = "Field `HSION` reader - Internal high-speed clock enable"] pub type HsionR = crate :: BitReader < Hsion > ; impl HsionR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsion { match self . bits { false => Hsion :: Off , true => Hsion :: On , } } # [doc = "Clock Off"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Hsion :: Off } # [doc = "Clock On"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Hsion :: On } } # [doc = "Field `HSION` writer - Internal high-speed clock enable"] pub type HsionW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsion > ; impl < 'a , REG > HsionW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock Off"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: Off) } # [doc = "Clock On"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: On) } } # [doc = "Internal high-speed clock ready flag\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsirdyr { # [doc = "0: Clock not ready"] NotReady = 0 , # [doc = "1: Clock ready"] Ready = 1 , } impl From < Hsirdyr > for bool { # [inline (always)] fn from (variant : Hsirdyr) -> Self { variant as u8 != 0 } } # [doc = "Field `HSIRDY` reader - Internal high-speed clock ready flag"] pub type HsirdyR = crate :: BitReader < Hsirdyr > ; impl HsirdyR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsirdyr { match self . bits { false => Hsirdyr :: NotReady , true => Hsirdyr :: Ready , } } # [doc = "Clock not ready"] # [inline (always)] pub fn is_not_ready (& self) -> bool { * self == Hsirdyr :: NotReady } # [doc = "Clock ready"] # [inline (always)] pub fn is_ready (& self) -> bool { * self == Hsirdyr :: Ready } } # [doc = "Field `HSITRIM` reader - Internal high-speed clock trimming"] pub type HsitrimR = crate :: FieldReader ; # [doc = "Field `HSITRIM` writer - Internal high-speed clock trimming"] pub type HsitrimW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Field `HSICAL` reader - Internal high-speed clock calibration"] pub type HsicalR = crate :: FieldReader ; # [doc = "Field `HSEON` reader - HSE clock enable"] pub use HsionR as HseonR ; # [doc = "Field `HSEON` writer - HSE clock enable"] pub use HsionW as HseonW ; # [doc = "Field `HSERDY` reader - HSE clock ready flag"] pub use HsirdyR as HserdyR ; # [doc = "HSE clock bypass\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsebyp { # [doc = "0: HSE crystal oscillator not bypassed"] NotBypassed = 0 , # [doc = "1: HSE crystal oscillator bypassed with external clock"] Bypassed = 1 , } impl From < Hsebyp > for bool { # [inline (always)] fn from (variant : Hsebyp) -> Self { variant as u8 != 0 } } # [doc = "Field `HSEBYP` reader - HSE clock bypass"] pub type HsebypR = crate :: BitReader < Hsebyp > ; impl HsebypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsebyp { match self . bits { false => Hsebyp :: NotBypassed , true => Hsebyp :: Bypassed , } } # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn is_not_bypassed (& self) -> bool { * self == Hsebyp :: NotBypassed } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn is_bypassed (& self) -> bool { * self == Hsebyp :: Bypassed } } # [doc = "Field `HSEBYP` writer - HSE clock bypass"] pub type HsebypW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsebyp > ; impl < 'a , REG > HsebypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn not_bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: NotBypassed) } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: Bypassed) } } # [doc = "Clock security system enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Csson { # [doc = "0: Clock security system disabled (clock detector OFF)"] Off = 0 , # [doc = "1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] On = 1 , } impl From < Csson > for bool { # [inline (always)] fn from (variant : Csson) -> Self { variant as u8 != 0 } } # [doc = "Field `CSSON` reader - Clock security system enable"] pub type CssonR = crate :: BitReader < Csson > ; impl CssonR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Csson { match self . bits { false => Csson :: Off , true => Csson :: On , } } # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Csson :: Off } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Csson :: On } } # [doc = "Field `CSSON` writer - Clock security system enable"] pub type CssonW < 'a , REG > = crate :: BitWriter < 'a , REG , Csson > ; impl < 'a , REG > CssonW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: Off) } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: On) } } # [doc = "Field `PLLON` reader - Main PLL (PLL) enable"] pub use HsionR as PllonR ; # [doc = "Field `PLLON` writer - Main PLL (PLL) enable"] pub use HsionW as PllonW ; # [doc = "Field `PLLRDY` reader - Main PLL (PLL) clock ready flag"] pub use HsirdyR as PllrdyR ; # [doc = "Field `PLLI2SON` reader - PLLI2S enable"] pub use HsionR as Plli2sonR ; # [doc = "Field `PLLI2SON` writer - PLLI2S enable"] pub use HsionW as Plli2sonW ; # [doc = "Field `PLLI2SRDY` reader - PLLI2S clock ready flag"] pub use HsirdyR as Plli2srdyR ; impl R { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& self) -> HsionR { HsionR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Internal high-speed clock ready flag"] # [inline (always)] pub fn hsirdy (& self) -> HsirdyR { HsirdyR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& self) -> HsitrimR { HsitrimR :: new (((self . bits >> 3) & 0x1f) as u8) } # [doc = "Bits 8:15 - Internal high-speed clock calibration"] # [inline (always)] pub fn hsical (& self) -> HsicalR { HsicalR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& self) -> HseonR { HseonR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - HSE clock ready flag"] # [inline (always)] pub fn hserdy (& self) -> HserdyR { HserdyR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& self) -> HsebypR { HsebypR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& self) -> CssonR { CssonR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& self) -> PllonR { PllonR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Main PLL (PLL) clock ready flag"] # [inline (always)] pub fn pllrdy (& self) -> PllrdyR { PllrdyR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& self) -> Plli2sonR { Plli2sonR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - PLLI2S clock ready flag"] # [inline (always)] pub fn plli2srdy (& self) -> Plli2srdyR { Plli2srdyR :: new (((self . bits >> 27) & 1) != 0) } } impl W { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& mut self) -> HsionW < CrSpec > { HsionW :: new (self , 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& mut self) -> HsitrimW < CrSpec > { HsitrimW :: new (self , 3) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& mut self) -> HseonW <'_, CrSpec > { HseonW :: new (self , 16) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& mut self) -> HsebypW < CrSpec > { HsebypW :: new (self , 18) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& mut self) -> CssonW < CrSpec > { CssonW :: new (self , 19) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& mut self) -> PllonW < CrSpec > { PllonW :: new (self , 24) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& mut self) -> Plli2sonW < CrSpec > { Plli2sonW :: new (self , 26) } } # [doc = "clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0x83"] impl crate :: Resettable for CrSpec { const RESET_VALUE : u32 = 0x83 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cr.rs:1:9091 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn hsebyp (& mut self) -> HsebypW < CrSpec > { HsebypW :: new (self , 18) } # [doc = "Bit 19 - Clock security s... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Internal high-speed clock enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsion { # [doc = "0: Clock Off"] Off = 0 , # [doc = "1: Clock On"] On = 1 , } impl From < Hsion > for bool { # [inline (always)] fn from (variant : Hsion) -> Self { variant as u8 != 0 } } # [doc = "Field `HSION` reader - Internal high-speed clock enable"] pub type HsionR = crate :: BitReader < Hsion > ; impl HsionR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsion { match self . bits { false => Hsion :: Off , true => Hsion :: On , } } # [doc = "Clock Off"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Hsion :: Off } # [doc = "Clock On"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Hsion :: On } } # [doc = "Field `HSION` writer - Internal high-speed clock enable"] pub type HsionW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsion > ; impl < 'a , REG > HsionW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock Off"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: Off) } # [doc = "Clock On"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: On) } } # [doc = "Internal high-speed clock ready flag\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsirdyr { # [doc = "0: Clock not ready"] NotReady = 0 , # [doc = "1: Clock ready"] Ready = 1 , } impl From < Hsirdyr > for bool { # [inline (always)] fn from (variant : Hsirdyr) -> Self { variant as u8 != 0 } } # [doc = "Field `HSIRDY` reader - Internal high-speed clock ready flag"] pub type HsirdyR = crate :: BitReader < Hsirdyr > ; impl HsirdyR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsirdyr { match self . bits { false => Hsirdyr :: NotReady , true => Hsirdyr :: Ready , } } # [doc = "Clock not ready"] # [inline (always)] pub fn is_not_ready (& self) -> bool { * self == Hsirdyr :: NotReady } # [doc = "Clock ready"] # [inline (always)] pub fn is_ready (& self) -> bool { * self == Hsirdyr :: Ready } } # [doc = "Field `HSITRIM` reader - Internal high-speed clock trimming"] pub type HsitrimR = crate :: FieldReader ; # [doc = "Field `HSITRIM` writer - Internal high-speed clock trimming"] pub type HsitrimW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Field `HSICAL` reader - Internal high-speed clock calibration"] pub type HsicalR = crate :: FieldReader ; # [doc = "Field `HSEON` reader - HSE clock enable"] pub use HsionR as HseonR ; # [doc = "Field `HSEON` writer - HSE clock enable"] pub use HsionW as HseonW ; # [doc = "Field `HSERDY` reader - HSE clock ready flag"] pub use HsirdyR as HserdyR ; # [doc = "HSE clock bypass\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsebyp { # [doc = "0: HSE crystal oscillator not bypassed"] NotBypassed = 0 , # [doc = "1: HSE crystal oscillator bypassed with external clock"] Bypassed = 1 , } impl From < Hsebyp > for bool { # [inline (always)] fn from (variant : Hsebyp) -> Self { variant as u8 != 0 } } # [doc = "Field `HSEBYP` reader - HSE clock bypass"] pub type HsebypR = crate :: BitReader < Hsebyp > ; impl HsebypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsebyp { match self . bits { false => Hsebyp :: NotBypassed , true => Hsebyp :: Bypassed , } } # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn is_not_bypassed (& self) -> bool { * self == Hsebyp :: NotBypassed } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn is_bypassed (& self) -> bool { * self == Hsebyp :: Bypassed } } # [doc = "Field `HSEBYP` writer - HSE clock bypass"] pub type HsebypW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsebyp > ; impl < 'a , REG > HsebypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn not_bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: NotBypassed) } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: Bypassed) } } # [doc = "Clock security system enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Csson { # [doc = "0: Clock security system disabled (clock detector OFF)"] Off = 0 , # [doc = "1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] On = 1 , } impl From < Csson > for bool { # [inline (always)] fn from (variant : Csson) -> Self { variant as u8 != 0 } } # [doc = "Field `CSSON` reader - Clock security system enable"] pub type CssonR = crate :: BitReader < Csson > ; impl CssonR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Csson { match self . bits { false => Csson :: Off , true => Csson :: On , } } # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Csson :: Off } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Csson :: On } } # [doc = "Field `CSSON` writer - Clock security system enable"] pub type CssonW < 'a , REG > = crate :: BitWriter < 'a , REG , Csson > ; impl < 'a , REG > CssonW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: Off) } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: On) } } # [doc = "Field `PLLON` reader - Main PLL (PLL) enable"] pub use HsionR as PllonR ; # [doc = "Field `PLLON` writer - Main PLL (PLL) enable"] pub use HsionW as PllonW ; # [doc = "Field `PLLRDY` reader - Main PLL (PLL) clock ready flag"] pub use HsirdyR as PllrdyR ; # [doc = "Field `PLLI2SON` reader - PLLI2S enable"] pub use HsionR as Plli2sonR ; # [doc = "Field `PLLI2SON` writer - PLLI2S enable"] pub use HsionW as Plli2sonW ; # [doc = "Field `PLLI2SRDY` reader - PLLI2S clock ready flag"] pub use HsirdyR as Plli2srdyR ; impl R { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& self) -> HsionR { HsionR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Internal high-speed clock ready flag"] # [inline (always)] pub fn hsirdy (& self) -> HsirdyR { HsirdyR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& self) -> HsitrimR { HsitrimR :: new (((self . bits >> 3) & 0x1f) as u8) } # [doc = "Bits 8:15 - Internal high-speed clock calibration"] # [inline (always)] pub fn hsical (& self) -> HsicalR { HsicalR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& self) -> HseonR { HseonR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - HSE clock ready flag"] # [inline (always)] pub fn hserdy (& self) -> HserdyR { HserdyR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& self) -> HsebypR { HsebypR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& self) -> CssonR { CssonR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& self) -> PllonR { PllonR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Main PLL (PLL) clock ready flag"] # [inline (always)] pub fn pllrdy (& self) -> PllrdyR { PllrdyR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& self) -> Plli2sonR { Plli2sonR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - PLLI2S clock ready flag"] # [inline (always)] pub fn plli2srdy (& self) -> Plli2srdyR { Plli2srdyR :: new (((self . bits >> 27) & 1) != 0) } } impl W { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& mut self) -> HsionW < CrSpec > { HsionW :: new (self , 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& mut self) -> HsitrimW < CrSpec > { HsitrimW :: new (self , 3) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& mut self) -> HseonW < CrSpec > { HseonW :: new (self , 16) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& mut self) -> HsebypW <'_, CrSpec > { HsebypW :: new (self , 18) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& mut self) -> CssonW < CrSpec > { CssonW :: new (self , 19) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& mut self) -> PllonW < CrSpec > { PllonW :: new (self , 24) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& mut self) -> Plli2sonW < CrSpec > { Plli2sonW :: new (self , 26) } } # [doc = "clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0x83"] impl crate :: Resettable for CrSpec { const RESET_VALUE : u32 = 0x83 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cr.rs:1:9240 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn csson (& mut self) -> CssonW < CrSpec > { CssonW :: new (self , 19) } # [doc = "Bit 24 - Main PLL (PLL) ena... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Internal high-speed clock enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsion { # [doc = "0: Clock Off"] Off = 0 , # [doc = "1: Clock On"] On = 1 , } impl From < Hsion > for bool { # [inline (always)] fn from (variant : Hsion) -> Self { variant as u8 != 0 } } # [doc = "Field `HSION` reader - Internal high-speed clock enable"] pub type HsionR = crate :: BitReader < Hsion > ; impl HsionR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsion { match self . bits { false => Hsion :: Off , true => Hsion :: On , } } # [doc = "Clock Off"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Hsion :: Off } # [doc = "Clock On"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Hsion :: On } } # [doc = "Field `HSION` writer - Internal high-speed clock enable"] pub type HsionW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsion > ; impl < 'a , REG > HsionW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock Off"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: Off) } # [doc = "Clock On"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: On) } } # [doc = "Internal high-speed clock ready flag\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsirdyr { # [doc = "0: Clock not ready"] NotReady = 0 , # [doc = "1: Clock ready"] Ready = 1 , } impl From < Hsirdyr > for bool { # [inline (always)] fn from (variant : Hsirdyr) -> Self { variant as u8 != 0 } } # [doc = "Field `HSIRDY` reader - Internal high-speed clock ready flag"] pub type HsirdyR = crate :: BitReader < Hsirdyr > ; impl HsirdyR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsirdyr { match self . bits { false => Hsirdyr :: NotReady , true => Hsirdyr :: Ready , } } # [doc = "Clock not ready"] # [inline (always)] pub fn is_not_ready (& self) -> bool { * self == Hsirdyr :: NotReady } # [doc = "Clock ready"] # [inline (always)] pub fn is_ready (& self) -> bool { * self == Hsirdyr :: Ready } } # [doc = "Field `HSITRIM` reader - Internal high-speed clock trimming"] pub type HsitrimR = crate :: FieldReader ; # [doc = "Field `HSITRIM` writer - Internal high-speed clock trimming"] pub type HsitrimW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Field `HSICAL` reader - Internal high-speed clock calibration"] pub type HsicalR = crate :: FieldReader ; # [doc = "Field `HSEON` reader - HSE clock enable"] pub use HsionR as HseonR ; # [doc = "Field `HSEON` writer - HSE clock enable"] pub use HsionW as HseonW ; # [doc = "Field `HSERDY` reader - HSE clock ready flag"] pub use HsirdyR as HserdyR ; # [doc = "HSE clock bypass\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsebyp { # [doc = "0: HSE crystal oscillator not bypassed"] NotBypassed = 0 , # [doc = "1: HSE crystal oscillator bypassed with external clock"] Bypassed = 1 , } impl From < Hsebyp > for bool { # [inline (always)] fn from (variant : Hsebyp) -> Self { variant as u8 != 0 } } # [doc = "Field `HSEBYP` reader - HSE clock bypass"] pub type HsebypR = crate :: BitReader < Hsebyp > ; impl HsebypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsebyp { match self . bits { false => Hsebyp :: NotBypassed , true => Hsebyp :: Bypassed , } } # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn is_not_bypassed (& self) -> bool { * self == Hsebyp :: NotBypassed } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn is_bypassed (& self) -> bool { * self == Hsebyp :: Bypassed } } # [doc = "Field `HSEBYP` writer - HSE clock bypass"] pub type HsebypW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsebyp > ; impl < 'a , REG > HsebypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn not_bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: NotBypassed) } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: Bypassed) } } # [doc = "Clock security system enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Csson { # [doc = "0: Clock security system disabled (clock detector OFF)"] Off = 0 , # [doc = "1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] On = 1 , } impl From < Csson > for bool { # [inline (always)] fn from (variant : Csson) -> Self { variant as u8 != 0 } } # [doc = "Field `CSSON` reader - Clock security system enable"] pub type CssonR = crate :: BitReader < Csson > ; impl CssonR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Csson { match self . bits { false => Csson :: Off , true => Csson :: On , } } # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Csson :: Off } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Csson :: On } } # [doc = "Field `CSSON` writer - Clock security system enable"] pub type CssonW < 'a , REG > = crate :: BitWriter < 'a , REG , Csson > ; impl < 'a , REG > CssonW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: Off) } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: On) } } # [doc = "Field `PLLON` reader - Main PLL (PLL) enable"] pub use HsionR as PllonR ; # [doc = "Field `PLLON` writer - Main PLL (PLL) enable"] pub use HsionW as PllonW ; # [doc = "Field `PLLRDY` reader - Main PLL (PLL) clock ready flag"] pub use HsirdyR as PllrdyR ; # [doc = "Field `PLLI2SON` reader - PLLI2S enable"] pub use HsionR as Plli2sonR ; # [doc = "Field `PLLI2SON` writer - PLLI2S enable"] pub use HsionW as Plli2sonW ; # [doc = "Field `PLLI2SRDY` reader - PLLI2S clock ready flag"] pub use HsirdyR as Plli2srdyR ; impl R { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& self) -> HsionR { HsionR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Internal high-speed clock ready flag"] # [inline (always)] pub fn hsirdy (& self) -> HsirdyR { HsirdyR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& self) -> HsitrimR { HsitrimR :: new (((self . bits >> 3) & 0x1f) as u8) } # [doc = "Bits 8:15 - Internal high-speed clock calibration"] # [inline (always)] pub fn hsical (& self) -> HsicalR { HsicalR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& self) -> HseonR { HseonR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - HSE clock ready flag"] # [inline (always)] pub fn hserdy (& self) -> HserdyR { HserdyR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& self) -> HsebypR { HsebypR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& self) -> CssonR { CssonR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& self) -> PllonR { PllonR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Main PLL (PLL) clock ready flag"] # [inline (always)] pub fn pllrdy (& self) -> PllrdyR { PllrdyR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& self) -> Plli2sonR { Plli2sonR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - PLLI2S clock ready flag"] # [inline (always)] pub fn plli2srdy (& self) -> Plli2srdyR { Plli2srdyR :: new (((self . bits >> 27) & 1) != 0) } } impl W { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& mut self) -> HsionW < CrSpec > { HsionW :: new (self , 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& mut self) -> HsitrimW < CrSpec > { HsitrimW :: new (self , 3) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& mut self) -> HseonW < CrSpec > { HseonW :: new (self , 16) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& mut self) -> HsebypW < CrSpec > { HsebypW :: new (self , 18) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& mut self) -> CssonW <'_, CrSpec > { CssonW :: new (self , 19) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& mut self) -> PllonW < CrSpec > { PllonW :: new (self , 24) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& mut self) -> Plli2sonW < CrSpec > { Plli2sonW :: new (self , 26) } } # [doc = "clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0x83"] impl crate :: Resettable for CrSpec { const RESET_VALUE : u32 = 0x83 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cr.rs:1:9380 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn pllon (& mut self) -> PllonW < CrSpec > { PllonW :: new (self , 24) } # [doc = "Bit 26 - PLLI2S enable"] # ... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Internal high-speed clock enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsion { # [doc = "0: Clock Off"] Off = 0 , # [doc = "1: Clock On"] On = 1 , } impl From < Hsion > for bool { # [inline (always)] fn from (variant : Hsion) -> Self { variant as u8 != 0 } } # [doc = "Field `HSION` reader - Internal high-speed clock enable"] pub type HsionR = crate :: BitReader < Hsion > ; impl HsionR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsion { match self . bits { false => Hsion :: Off , true => Hsion :: On , } } # [doc = "Clock Off"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Hsion :: Off } # [doc = "Clock On"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Hsion :: On } } # [doc = "Field `HSION` writer - Internal high-speed clock enable"] pub type HsionW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsion > ; impl < 'a , REG > HsionW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock Off"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: Off) } # [doc = "Clock On"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: On) } } # [doc = "Internal high-speed clock ready flag\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsirdyr { # [doc = "0: Clock not ready"] NotReady = 0 , # [doc = "1: Clock ready"] Ready = 1 , } impl From < Hsirdyr > for bool { # [inline (always)] fn from (variant : Hsirdyr) -> Self { variant as u8 != 0 } } # [doc = "Field `HSIRDY` reader - Internal high-speed clock ready flag"] pub type HsirdyR = crate :: BitReader < Hsirdyr > ; impl HsirdyR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsirdyr { match self . bits { false => Hsirdyr :: NotReady , true => Hsirdyr :: Ready , } } # [doc = "Clock not ready"] # [inline (always)] pub fn is_not_ready (& self) -> bool { * self == Hsirdyr :: NotReady } # [doc = "Clock ready"] # [inline (always)] pub fn is_ready (& self) -> bool { * self == Hsirdyr :: Ready } } # [doc = "Field `HSITRIM` reader - Internal high-speed clock trimming"] pub type HsitrimR = crate :: FieldReader ; # [doc = "Field `HSITRIM` writer - Internal high-speed clock trimming"] pub type HsitrimW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Field `HSICAL` reader - Internal high-speed clock calibration"] pub type HsicalR = crate :: FieldReader ; # [doc = "Field `HSEON` reader - HSE clock enable"] pub use HsionR as HseonR ; # [doc = "Field `HSEON` writer - HSE clock enable"] pub use HsionW as HseonW ; # [doc = "Field `HSERDY` reader - HSE clock ready flag"] pub use HsirdyR as HserdyR ; # [doc = "HSE clock bypass\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsebyp { # [doc = "0: HSE crystal oscillator not bypassed"] NotBypassed = 0 , # [doc = "1: HSE crystal oscillator bypassed with external clock"] Bypassed = 1 , } impl From < Hsebyp > for bool { # [inline (always)] fn from (variant : Hsebyp) -> Self { variant as u8 != 0 } } # [doc = "Field `HSEBYP` reader - HSE clock bypass"] pub type HsebypR = crate :: BitReader < Hsebyp > ; impl HsebypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsebyp { match self . bits { false => Hsebyp :: NotBypassed , true => Hsebyp :: Bypassed , } } # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn is_not_bypassed (& self) -> bool { * self == Hsebyp :: NotBypassed } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn is_bypassed (& self) -> bool { * self == Hsebyp :: Bypassed } } # [doc = "Field `HSEBYP` writer - HSE clock bypass"] pub type HsebypW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsebyp > ; impl < 'a , REG > HsebypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn not_bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: NotBypassed) } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: Bypassed) } } # [doc = "Clock security system enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Csson { # [doc = "0: Clock security system disabled (clock detector OFF)"] Off = 0 , # [doc = "1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] On = 1 , } impl From < Csson > for bool { # [inline (always)] fn from (variant : Csson) -> Self { variant as u8 != 0 } } # [doc = "Field `CSSON` reader - Clock security system enable"] pub type CssonR = crate :: BitReader < Csson > ; impl CssonR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Csson { match self . bits { false => Csson :: Off , true => Csson :: On , } } # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Csson :: Off } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Csson :: On } } # [doc = "Field `CSSON` writer - Clock security system enable"] pub type CssonW < 'a , REG > = crate :: BitWriter < 'a , REG , Csson > ; impl < 'a , REG > CssonW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: Off) } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: On) } } # [doc = "Field `PLLON` reader - Main PLL (PLL) enable"] pub use HsionR as PllonR ; # [doc = "Field `PLLON` writer - Main PLL (PLL) enable"] pub use HsionW as PllonW ; # [doc = "Field `PLLRDY` reader - Main PLL (PLL) clock ready flag"] pub use HsirdyR as PllrdyR ; # [doc = "Field `PLLI2SON` reader - PLLI2S enable"] pub use HsionR as Plli2sonR ; # [doc = "Field `PLLI2SON` writer - PLLI2S enable"] pub use HsionW as Plli2sonW ; # [doc = "Field `PLLI2SRDY` reader - PLLI2S clock ready flag"] pub use HsirdyR as Plli2srdyR ; impl R { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& self) -> HsionR { HsionR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Internal high-speed clock ready flag"] # [inline (always)] pub fn hsirdy (& self) -> HsirdyR { HsirdyR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& self) -> HsitrimR { HsitrimR :: new (((self . bits >> 3) & 0x1f) as u8) } # [doc = "Bits 8:15 - Internal high-speed clock calibration"] # [inline (always)] pub fn hsical (& self) -> HsicalR { HsicalR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& self) -> HseonR { HseonR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - HSE clock ready flag"] # [inline (always)] pub fn hserdy (& self) -> HserdyR { HserdyR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& self) -> HsebypR { HsebypR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& self) -> CssonR { CssonR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& self) -> PllonR { PllonR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Main PLL (PLL) clock ready flag"] # [inline (always)] pub fn pllrdy (& self) -> PllrdyR { PllrdyR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& self) -> Plli2sonR { Plli2sonR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - PLLI2S clock ready flag"] # [inline (always)] pub fn plli2srdy (& self) -> Plli2srdyR { Plli2srdyR :: new (((self . bits >> 27) & 1) != 0) } } impl W { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& mut self) -> HsionW < CrSpec > { HsionW :: new (self , 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& mut self) -> HsitrimW < CrSpec > { HsitrimW :: new (self , 3) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& mut self) -> HseonW < CrSpec > { HseonW :: new (self , 16) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& mut self) -> HsebypW < CrSpec > { HsebypW :: new (self , 18) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& mut self) -> CssonW < CrSpec > { CssonW :: new (self , 19) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& mut self) -> PllonW <'_, CrSpec > { PllonW :: new (self , 24) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& mut self) -> Plli2sonW < CrSpec > { Plli2sonW :: new (self , 26) } } # [doc = "clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0x83"] impl crate :: Resettable for CrSpec { const RESET_VALUE : u32 = 0x83 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cr.rs:1:9515 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn plli2son (& mut self) -> Plli2sonW < CrSpec > { Plli2sonW :: new (self , 26) } } # [doc = "clock control regist... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Internal high-speed clock enable\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsion { # [doc = "0: Clock Off"] Off = 0 , # [doc = "1: Clock On"] On = 1 , } impl From < Hsion > for bool { # [inline (always)] fn from (variant : Hsion) -> Self { variant as u8 != 0 } } # [doc = "Field `HSION` reader - Internal high-speed clock enable"] pub type HsionR = crate :: BitReader < Hsion > ; impl HsionR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsion { match self . bits { false => Hsion :: Off , true => Hsion :: On , } } # [doc = "Clock Off"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Hsion :: Off } # [doc = "Clock On"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Hsion :: On } } # [doc = "Field `HSION` writer - Internal high-speed clock enable"] pub type HsionW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsion > ; impl < 'a , REG > HsionW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock Off"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: Off) } # [doc = "Clock On"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Hsion :: On) } } # [doc = "Internal high-speed clock ready flag\n\nValue on reset: 1"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsirdyr { # [doc = "0: Clock not ready"] NotReady = 0 , # [doc = "1: Clock ready"] Ready = 1 , } impl From < Hsirdyr > for bool { # [inline (always)] fn from (variant : Hsirdyr) -> Self { variant as u8 != 0 } } # [doc = "Field `HSIRDY` reader - Internal high-speed clock ready flag"] pub type HsirdyR = crate :: BitReader < Hsirdyr > ; impl HsirdyR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsirdyr { match self . bits { false => Hsirdyr :: NotReady , true => Hsirdyr :: Ready , } } # [doc = "Clock not ready"] # [inline (always)] pub fn is_not_ready (& self) -> bool { * self == Hsirdyr :: NotReady } # [doc = "Clock ready"] # [inline (always)] pub fn is_ready (& self) -> bool { * self == Hsirdyr :: Ready } } # [doc = "Field `HSITRIM` reader - Internal high-speed clock trimming"] pub type HsitrimR = crate :: FieldReader ; # [doc = "Field `HSITRIM` writer - Internal high-speed clock trimming"] pub type HsitrimW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Field `HSICAL` reader - Internal high-speed clock calibration"] pub type HsicalR = crate :: FieldReader ; # [doc = "Field `HSEON` reader - HSE clock enable"] pub use HsionR as HseonR ; # [doc = "Field `HSEON` writer - HSE clock enable"] pub use HsionW as HseonW ; # [doc = "Field `HSERDY` reader - HSE clock ready flag"] pub use HsirdyR as HserdyR ; # [doc = "HSE clock bypass\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Hsebyp { # [doc = "0: HSE crystal oscillator not bypassed"] NotBypassed = 0 , # [doc = "1: HSE crystal oscillator bypassed with external clock"] Bypassed = 1 , } impl From < Hsebyp > for bool { # [inline (always)] fn from (variant : Hsebyp) -> Self { variant as u8 != 0 } } # [doc = "Field `HSEBYP` reader - HSE clock bypass"] pub type HsebypR = crate :: BitReader < Hsebyp > ; impl HsebypR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hsebyp { match self . bits { false => Hsebyp :: NotBypassed , true => Hsebyp :: Bypassed , } } # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn is_not_bypassed (& self) -> bool { * self == Hsebyp :: NotBypassed } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn is_bypassed (& self) -> bool { * self == Hsebyp :: Bypassed } } # [doc = "Field `HSEBYP` writer - HSE clock bypass"] pub type HsebypW < 'a , REG > = crate :: BitWriter < 'a , REG , Hsebyp > ; impl < 'a , REG > HsebypW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSE crystal oscillator not bypassed"] # [inline (always)] pub fn not_bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: NotBypassed) } # [doc = "HSE crystal oscillator bypassed with external clock"] # [inline (always)] pub fn bypassed (self) -> & 'a mut crate :: W < REG > { self . variant (Hsebyp :: Bypassed) } } # [doc = "Clock security system enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Csson { # [doc = "0: Clock security system disabled (clock detector OFF)"] Off = 0 , # [doc = "1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] On = 1 , } impl From < Csson > for bool { # [inline (always)] fn from (variant : Csson) -> Self { variant as u8 != 0 } } # [doc = "Field `CSSON` reader - Clock security system enable"] pub type CssonR = crate :: BitReader < Csson > ; impl CssonR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Csson { match self . bits { false => Csson :: Off , true => Csson :: On , } } # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn is_off (& self) -> bool { * self == Csson :: Off } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn is_on (& self) -> bool { * self == Csson :: On } } # [doc = "Field `CSSON` writer - Clock security system enable"] pub type CssonW < 'a , REG > = crate :: BitWriter < 'a , REG , Csson > ; impl < 'a , REG > CssonW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Clock security system disabled (clock detector OFF)"] # [inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: Off) } # [doc = "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] # [inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (Csson :: On) } } # [doc = "Field `PLLON` reader - Main PLL (PLL) enable"] pub use HsionR as PllonR ; # [doc = "Field `PLLON` writer - Main PLL (PLL) enable"] pub use HsionW as PllonW ; # [doc = "Field `PLLRDY` reader - Main PLL (PLL) clock ready flag"] pub use HsirdyR as PllrdyR ; # [doc = "Field `PLLI2SON` reader - PLLI2S enable"] pub use HsionR as Plli2sonR ; # [doc = "Field `PLLI2SON` writer - PLLI2S enable"] pub use HsionW as Plli2sonW ; # [doc = "Field `PLLI2SRDY` reader - PLLI2S clock ready flag"] pub use HsirdyR as Plli2srdyR ; impl R { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& self) -> HsionR { HsionR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Internal high-speed clock ready flag"] # [inline (always)] pub fn hsirdy (& self) -> HsirdyR { HsirdyR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& self) -> HsitrimR { HsitrimR :: new (((self . bits >> 3) & 0x1f) as u8) } # [doc = "Bits 8:15 - Internal high-speed clock calibration"] # [inline (always)] pub fn hsical (& self) -> HsicalR { HsicalR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& self) -> HseonR { HseonR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - HSE clock ready flag"] # [inline (always)] pub fn hserdy (& self) -> HserdyR { HserdyR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& self) -> HsebypR { HsebypR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& self) -> CssonR { CssonR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& self) -> PllonR { PllonR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Main PLL (PLL) clock ready flag"] # [inline (always)] pub fn pllrdy (& self) -> PllrdyR { PllrdyR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& self) -> Plli2sonR { Plli2sonR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - PLLI2S clock ready flag"] # [inline (always)] pub fn plli2srdy (& self) -> Plli2srdyR { Plli2srdyR :: new (((self . bits >> 27) & 1) != 0) } } impl W { # [doc = "Bit 0 - Internal high-speed clock enable"] # [inline (always)] pub fn hsion (& mut self) -> HsionW < CrSpec > { HsionW :: new (self , 0) } # [doc = "Bits 3:7 - Internal high-speed clock trimming"] # [inline (always)] pub fn hsitrim (& mut self) -> HsitrimW < CrSpec > { HsitrimW :: new (self , 3) } # [doc = "Bit 16 - HSE clock enable"] # [inline (always)] pub fn hseon (& mut self) -> HseonW < CrSpec > { HseonW :: new (self , 16) } # [doc = "Bit 18 - HSE clock bypass"] # [inline (always)] pub fn hsebyp (& mut self) -> HsebypW < CrSpec > { HsebypW :: new (self , 18) } # [doc = "Bit 19 - Clock security system enable"] # [inline (always)] pub fn csson (& mut self) -> CssonW < CrSpec > { CssonW :: new (self , 19) } # [doc = "Bit 24 - Main PLL (PLL) enable"] # [inline (always)] pub fn pllon (& mut self) -> PllonW < CrSpec > { PllonW :: new (self , 24) } # [doc = "Bit 26 - PLLI2S enable"] # [inline (always)] pub fn plli2son (& mut self) -> Plli2sonW <'_, CrSpec > { Plli2sonW :: new (self , 26) } } # [doc = "clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0x83"] impl crate :: Resettable for CrSpec { const RESET_VALUE : u32 = 0x83 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/pllcfgr.rs:1:5936 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn pllm (& mut self) -> PllmW < PllcfgrSpec > { PllmW :: new (self , 0) } # [doc = "Bits 6:14 - Main PLL (PLL) ... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PLLCFGR` reader"] pub type R = crate :: R < PllcfgrSpec > ; # [doc = "Register `PLLCFGR` writer"] pub type W = crate :: W < PllcfgrSpec > ; # [doc = "Field `PLLM` reader - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] pub type PllmR = crate :: FieldReader ; # [doc = "Field `PLLM` writer - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] pub type PllmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `PLLN` reader - Main PLL (PLL) multiplication factor for VCO"] pub type PllnR = crate :: FieldReader < u16 > ; # [doc = "Field `PLLN` writer - Main PLL (PLL) multiplication factor for VCO"] pub type PllnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Main PLL (PLL) division factor for main system clock\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pllp { # [doc = "0: PLLP=2"] Div2 = 0 , # [doc = "1: PLLP=4"] Div4 = 1 , # [doc = "2: PLLP=6"] Div6 = 2 , # [doc = "3: PLLP=8"] Div8 = 3 , } impl From < Pllp > for u8 { # [inline (always)] fn from (variant : Pllp) -> Self { variant as _ } } impl crate :: FieldSpec for Pllp { type Ux = u8 ; } impl crate :: IsEnum for Pllp { } # [doc = "Field `PLLP` reader - Main PLL (PLL) division factor for main system clock"] pub type PllpR = crate :: FieldReader < Pllp > ; impl PllpR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pllp { match self . bits { 0 => Pllp :: Div2 , 1 => Pllp :: Div4 , 2 => Pllp :: Div6 , 3 => Pllp :: Div8 , _ => unreachable ! () , } } # [doc = "PLLP=2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Pllp :: Div2 } # [doc = "PLLP=4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Pllp :: Div4 } # [doc = "PLLP=6"] # [inline (always)] pub fn is_div6 (& self) -> bool { * self == Pllp :: Div6 } # [doc = "PLLP=8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Pllp :: Div8 } } # [doc = "Field `PLLP` writer - Main PLL (PLL) division factor for main system clock"] pub type PllpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pllp , crate :: Safe > ; impl < 'a , REG > PllpW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "PLLP=2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div2) } # [doc = "PLLP=4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div4) } # [doc = "PLLP=6"] # [inline (always)] pub fn div6 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div6) } # [doc = "PLLP=8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div8) } } # [doc = "Main PLL(PLL) and audio PLL (PLLI2S) entry clock source\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pllsrc { # [doc = "0: HSI clock selected as PLL and PLLI2S clock entry"] Hsi = 0 , # [doc = "1: HSE oscillator clock selected as PLL and PLLI2S clock entry"] Hse = 1 , } impl From < Pllsrc > for bool { # [inline (always)] fn from (variant : Pllsrc) -> Self { variant as u8 != 0 } } # [doc = "Field `PLLSRC` reader - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] pub type PllsrcR = crate :: BitReader < Pllsrc > ; impl PllsrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pllsrc { match self . bits { false => Pllsrc :: Hsi , true => Pllsrc :: Hse , } } # [doc = "HSI clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Pllsrc :: Hsi } # [doc = "HSE oscillator clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Pllsrc :: Hse } } # [doc = "Field `PLLSRC` writer - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] pub type PllsrcW < 'a , REG > = crate :: BitWriter < 'a , REG , Pllsrc > ; impl < 'a , REG > PllsrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSI clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Pllsrc :: Hsi) } # [doc = "HSE oscillator clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Pllsrc :: Hse) } } # [doc = "Field `PLLQ` reader - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] pub type PllqR = crate :: FieldReader ; # [doc = "Field `PLLQ` writer - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] pub type PllqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] # [inline (always)] pub fn pllm (& self) -> PllmR { PllmR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:14 - Main PLL (PLL) multiplication factor for VCO"] # [inline (always)] pub fn plln (& self) -> PllnR { PllnR :: new (((self . bits >> 6) & 0x01ff) as u16) } # [doc = "Bits 16:17 - Main PLL (PLL) division factor for main system clock"] # [inline (always)] pub fn pllp (& self) -> PllpR { PllpR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] # [inline (always)] pub fn pllsrc (& self) -> PllsrcR { PllsrcR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] # [inline (always)] pub fn pllq (& self) -> PllqR { PllqR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] # [inline (always)] pub fn pllm (& mut self) -> PllmW <'_, PllcfgrSpec > { PllmW :: new (self , 0) } # [doc = "Bits 6:14 - Main PLL (PLL) multiplication factor for VCO"] # [inline (always)] pub fn plln (& mut self) -> PllnW < PllcfgrSpec > { PllnW :: new (self , 6) } # [doc = "Bits 16:17 - Main PLL (PLL) division factor for main system clock"] # [inline (always)] pub fn pllp (& mut self) -> PllpW < PllcfgrSpec > { PllpW :: new (self , 16) } # [doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] # [inline (always)] pub fn pllsrc (& mut self) -> PllsrcW < PllcfgrSpec > { PllsrcW :: new (self , 22) } # [doc = "Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] # [inline (always)] pub fn pllq (& mut self) -> PllqW < PllcfgrSpec > { PllqW :: new (self , 24) } } # [doc = "PLL configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pllcfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllcfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PllcfgrSpec ; impl crate :: RegisterSpec for PllcfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pllcfgr::R`](R) reader structure"] impl crate :: Readable for PllcfgrSpec { } # [doc = "`write(|w| ..)` method takes [`pllcfgr::W`](W) writer structure"] impl crate :: Writable for PllcfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PLLCFGR to value 0x2400_3010"] impl crate :: Resettable for PllcfgrSpec { const RESET_VALUE : u32 = 0x2400_3010 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/pllcfgr.rs:1:6103 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn plln (& mut self) -> PllnW < PllcfgrSpec > { PllnW :: new (self , 6) } # [doc = "Bits 16:17 - Main PLL (PLL)... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PLLCFGR` reader"] pub type R = crate :: R < PllcfgrSpec > ; # [doc = "Register `PLLCFGR` writer"] pub type W = crate :: W < PllcfgrSpec > ; # [doc = "Field `PLLM` reader - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] pub type PllmR = crate :: FieldReader ; # [doc = "Field `PLLM` writer - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] pub type PllmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `PLLN` reader - Main PLL (PLL) multiplication factor for VCO"] pub type PllnR = crate :: FieldReader < u16 > ; # [doc = "Field `PLLN` writer - Main PLL (PLL) multiplication factor for VCO"] pub type PllnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Main PLL (PLL) division factor for main system clock\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pllp { # [doc = "0: PLLP=2"] Div2 = 0 , # [doc = "1: PLLP=4"] Div4 = 1 , # [doc = "2: PLLP=6"] Div6 = 2 , # [doc = "3: PLLP=8"] Div8 = 3 , } impl From < Pllp > for u8 { # [inline (always)] fn from (variant : Pllp) -> Self { variant as _ } } impl crate :: FieldSpec for Pllp { type Ux = u8 ; } impl crate :: IsEnum for Pllp { } # [doc = "Field `PLLP` reader - Main PLL (PLL) division factor for main system clock"] pub type PllpR = crate :: FieldReader < Pllp > ; impl PllpR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pllp { match self . bits { 0 => Pllp :: Div2 , 1 => Pllp :: Div4 , 2 => Pllp :: Div6 , 3 => Pllp :: Div8 , _ => unreachable ! () , } } # [doc = "PLLP=2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Pllp :: Div2 } # [doc = "PLLP=4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Pllp :: Div4 } # [doc = "PLLP=6"] # [inline (always)] pub fn is_div6 (& self) -> bool { * self == Pllp :: Div6 } # [doc = "PLLP=8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Pllp :: Div8 } } # [doc = "Field `PLLP` writer - Main PLL (PLL) division factor for main system clock"] pub type PllpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pllp , crate :: Safe > ; impl < 'a , REG > PllpW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "PLLP=2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div2) } # [doc = "PLLP=4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div4) } # [doc = "PLLP=6"] # [inline (always)] pub fn div6 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div6) } # [doc = "PLLP=8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div8) } } # [doc = "Main PLL(PLL) and audio PLL (PLLI2S) entry clock source\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pllsrc { # [doc = "0: HSI clock selected as PLL and PLLI2S clock entry"] Hsi = 0 , # [doc = "1: HSE oscillator clock selected as PLL and PLLI2S clock entry"] Hse = 1 , } impl From < Pllsrc > for bool { # [inline (always)] fn from (variant : Pllsrc) -> Self { variant as u8 != 0 } } # [doc = "Field `PLLSRC` reader - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] pub type PllsrcR = crate :: BitReader < Pllsrc > ; impl PllsrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pllsrc { match self . bits { false => Pllsrc :: Hsi , true => Pllsrc :: Hse , } } # [doc = "HSI clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Pllsrc :: Hsi } # [doc = "HSE oscillator clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Pllsrc :: Hse } } # [doc = "Field `PLLSRC` writer - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] pub type PllsrcW < 'a , REG > = crate :: BitWriter < 'a , REG , Pllsrc > ; impl < 'a , REG > PllsrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSI clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Pllsrc :: Hsi) } # [doc = "HSE oscillator clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Pllsrc :: Hse) } } # [doc = "Field `PLLQ` reader - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] pub type PllqR = crate :: FieldReader ; # [doc = "Field `PLLQ` writer - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] pub type PllqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] # [inline (always)] pub fn pllm (& self) -> PllmR { PllmR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:14 - Main PLL (PLL) multiplication factor for VCO"] # [inline (always)] pub fn plln (& self) -> PllnR { PllnR :: new (((self . bits >> 6) & 0x01ff) as u16) } # [doc = "Bits 16:17 - Main PLL (PLL) division factor for main system clock"] # [inline (always)] pub fn pllp (& self) -> PllpR { PllpR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] # [inline (always)] pub fn pllsrc (& self) -> PllsrcR { PllsrcR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] # [inline (always)] pub fn pllq (& self) -> PllqR { PllqR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] # [inline (always)] pub fn pllm (& mut self) -> PllmW < PllcfgrSpec > { PllmW :: new (self , 0) } # [doc = "Bits 6:14 - Main PLL (PLL) multiplication factor for VCO"] # [inline (always)] pub fn plln (& mut self) -> PllnW <'_, PllcfgrSpec > { PllnW :: new (self , 6) } # [doc = "Bits 16:17 - Main PLL (PLL) division factor for main system clock"] # [inline (always)] pub fn pllp (& mut self) -> PllpW < PllcfgrSpec > { PllpW :: new (self , 16) } # [doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] # [inline (always)] pub fn pllsrc (& mut self) -> PllsrcW < PllcfgrSpec > { PllsrcW :: new (self , 22) } # [doc = "Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] # [inline (always)] pub fn pllq (& mut self) -> PllqW < PllcfgrSpec > { PllqW :: new (self , 24) } } # [doc = "PLL configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pllcfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllcfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PllcfgrSpec ; impl crate :: RegisterSpec for PllcfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pllcfgr::R`](R) reader structure"] impl crate :: Readable for PllcfgrSpec { } # [doc = "`write(|w| ..)` method takes [`pllcfgr::W`](W) writer structure"] impl crate :: Writable for PllcfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PLLCFGR to value 0x2400_3010"] impl crate :: Resettable for PllcfgrSpec { const RESET_VALUE : u32 = 0x2400_3010 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/pllcfgr.rs:1:6279 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn pllp (& mut self) -> PllpW < PllcfgrSpec > { PllpW :: new (self , 16) } # [doc = "Bit 22 - Main PLL(PLL) and... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PLLCFGR` reader"] pub type R = crate :: R < PllcfgrSpec > ; # [doc = "Register `PLLCFGR` writer"] pub type W = crate :: W < PllcfgrSpec > ; # [doc = "Field `PLLM` reader - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] pub type PllmR = crate :: FieldReader ; # [doc = "Field `PLLM` writer - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] pub type PllmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `PLLN` reader - Main PLL (PLL) multiplication factor for VCO"] pub type PllnR = crate :: FieldReader < u16 > ; # [doc = "Field `PLLN` writer - Main PLL (PLL) multiplication factor for VCO"] pub type PllnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Main PLL (PLL) division factor for main system clock\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pllp { # [doc = "0: PLLP=2"] Div2 = 0 , # [doc = "1: PLLP=4"] Div4 = 1 , # [doc = "2: PLLP=6"] Div6 = 2 , # [doc = "3: PLLP=8"] Div8 = 3 , } impl From < Pllp > for u8 { # [inline (always)] fn from (variant : Pllp) -> Self { variant as _ } } impl crate :: FieldSpec for Pllp { type Ux = u8 ; } impl crate :: IsEnum for Pllp { } # [doc = "Field `PLLP` reader - Main PLL (PLL) division factor for main system clock"] pub type PllpR = crate :: FieldReader < Pllp > ; impl PllpR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pllp { match self . bits { 0 => Pllp :: Div2 , 1 => Pllp :: Div4 , 2 => Pllp :: Div6 , 3 => Pllp :: Div8 , _ => unreachable ! () , } } # [doc = "PLLP=2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Pllp :: Div2 } # [doc = "PLLP=4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Pllp :: Div4 } # [doc = "PLLP=6"] # [inline (always)] pub fn is_div6 (& self) -> bool { * self == Pllp :: Div6 } # [doc = "PLLP=8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Pllp :: Div8 } } # [doc = "Field `PLLP` writer - Main PLL (PLL) division factor for main system clock"] pub type PllpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pllp , crate :: Safe > ; impl < 'a , REG > PllpW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "PLLP=2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div2) } # [doc = "PLLP=4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div4) } # [doc = "PLLP=6"] # [inline (always)] pub fn div6 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div6) } # [doc = "PLLP=8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div8) } } # [doc = "Main PLL(PLL) and audio PLL (PLLI2S) entry clock source\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pllsrc { # [doc = "0: HSI clock selected as PLL and PLLI2S clock entry"] Hsi = 0 , # [doc = "1: HSE oscillator clock selected as PLL and PLLI2S clock entry"] Hse = 1 , } impl From < Pllsrc > for bool { # [inline (always)] fn from (variant : Pllsrc) -> Self { variant as u8 != 0 } } # [doc = "Field `PLLSRC` reader - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] pub type PllsrcR = crate :: BitReader < Pllsrc > ; impl PllsrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pllsrc { match self . bits { false => Pllsrc :: Hsi , true => Pllsrc :: Hse , } } # [doc = "HSI clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Pllsrc :: Hsi } # [doc = "HSE oscillator clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Pllsrc :: Hse } } # [doc = "Field `PLLSRC` writer - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] pub type PllsrcW < 'a , REG > = crate :: BitWriter < 'a , REG , Pllsrc > ; impl < 'a , REG > PllsrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSI clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Pllsrc :: Hsi) } # [doc = "HSE oscillator clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Pllsrc :: Hse) } } # [doc = "Field `PLLQ` reader - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] pub type PllqR = crate :: FieldReader ; # [doc = "Field `PLLQ` writer - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] pub type PllqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] # [inline (always)] pub fn pllm (& self) -> PllmR { PllmR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:14 - Main PLL (PLL) multiplication factor for VCO"] # [inline (always)] pub fn plln (& self) -> PllnR { PllnR :: new (((self . bits >> 6) & 0x01ff) as u16) } # [doc = "Bits 16:17 - Main PLL (PLL) division factor for main system clock"] # [inline (always)] pub fn pllp (& self) -> PllpR { PllpR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] # [inline (always)] pub fn pllsrc (& self) -> PllsrcR { PllsrcR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] # [inline (always)] pub fn pllq (& self) -> PllqR { PllqR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] # [inline (always)] pub fn pllm (& mut self) -> PllmW < PllcfgrSpec > { PllmW :: new (self , 0) } # [doc = "Bits 6:14 - Main PLL (PLL) multiplication factor for VCO"] # [inline (always)] pub fn plln (& mut self) -> PllnW < PllcfgrSpec > { PllnW :: new (self , 6) } # [doc = "Bits 16:17 - Main PLL (PLL) division factor for main system clock"] # [inline (always)] pub fn pllp (& mut self) -> PllpW <'_, PllcfgrSpec > { PllpW :: new (self , 16) } # [doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] # [inline (always)] pub fn pllsrc (& mut self) -> PllsrcW < PllcfgrSpec > { PllsrcW :: new (self , 22) } # [doc = "Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] # [inline (always)] pub fn pllq (& mut self) -> PllqW < PllcfgrSpec > { PllqW :: new (self , 24) } } # [doc = "PLL configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pllcfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllcfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PllcfgrSpec ; impl crate :: RegisterSpec for PllcfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pllcfgr::R`](R) reader structure"] impl crate :: Readable for PllcfgrSpec { } # [doc = "`write(|w| ..)` method takes [`pllcfgr::W`](W) writer structure"] impl crate :: Writable for PllcfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PLLCFGR to value 0x2400_3010"] impl crate :: Resettable for PllcfgrSpec { const RESET_VALUE : u32 = 0x2400_3010 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/pllcfgr.rs:1:6457 [INFO] [stdout] | [INFO] [stdout] 1 | ...nline (always)] pub fn pllsrc (& mut self) -> PllsrcW < PllcfgrSpec > { PllsrcW :: new (self , 22) } # [doc = "Bits 24:27 - Main PLL (... [INFO] [stdout] | ^^^^^^^^^^ ----------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PLLCFGR` reader"] pub type R = crate :: R < PllcfgrSpec > ; # [doc = "Register `PLLCFGR` writer"] pub type W = crate :: W < PllcfgrSpec > ; # [doc = "Field `PLLM` reader - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] pub type PllmR = crate :: FieldReader ; # [doc = "Field `PLLM` writer - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] pub type PllmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `PLLN` reader - Main PLL (PLL) multiplication factor for VCO"] pub type PllnR = crate :: FieldReader < u16 > ; # [doc = "Field `PLLN` writer - Main PLL (PLL) multiplication factor for VCO"] pub type PllnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Main PLL (PLL) division factor for main system clock\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pllp { # [doc = "0: PLLP=2"] Div2 = 0 , # [doc = "1: PLLP=4"] Div4 = 1 , # [doc = "2: PLLP=6"] Div6 = 2 , # [doc = "3: PLLP=8"] Div8 = 3 , } impl From < Pllp > for u8 { # [inline (always)] fn from (variant : Pllp) -> Self { variant as _ } } impl crate :: FieldSpec for Pllp { type Ux = u8 ; } impl crate :: IsEnum for Pllp { } # [doc = "Field `PLLP` reader - Main PLL (PLL) division factor for main system clock"] pub type PllpR = crate :: FieldReader < Pllp > ; impl PllpR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pllp { match self . bits { 0 => Pllp :: Div2 , 1 => Pllp :: Div4 , 2 => Pllp :: Div6 , 3 => Pllp :: Div8 , _ => unreachable ! () , } } # [doc = "PLLP=2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Pllp :: Div2 } # [doc = "PLLP=4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Pllp :: Div4 } # [doc = "PLLP=6"] # [inline (always)] pub fn is_div6 (& self) -> bool { * self == Pllp :: Div6 } # [doc = "PLLP=8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Pllp :: Div8 } } # [doc = "Field `PLLP` writer - Main PLL (PLL) division factor for main system clock"] pub type PllpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pllp , crate :: Safe > ; impl < 'a , REG > PllpW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "PLLP=2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div2) } # [doc = "PLLP=4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div4) } # [doc = "PLLP=6"] # [inline (always)] pub fn div6 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div6) } # [doc = "PLLP=8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div8) } } # [doc = "Main PLL(PLL) and audio PLL (PLLI2S) entry clock source\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pllsrc { # [doc = "0: HSI clock selected as PLL and PLLI2S clock entry"] Hsi = 0 , # [doc = "1: HSE oscillator clock selected as PLL and PLLI2S clock entry"] Hse = 1 , } impl From < Pllsrc > for bool { # [inline (always)] fn from (variant : Pllsrc) -> Self { variant as u8 != 0 } } # [doc = "Field `PLLSRC` reader - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] pub type PllsrcR = crate :: BitReader < Pllsrc > ; impl PllsrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pllsrc { match self . bits { false => Pllsrc :: Hsi , true => Pllsrc :: Hse , } } # [doc = "HSI clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Pllsrc :: Hsi } # [doc = "HSE oscillator clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Pllsrc :: Hse } } # [doc = "Field `PLLSRC` writer - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] pub type PllsrcW < 'a , REG > = crate :: BitWriter < 'a , REG , Pllsrc > ; impl < 'a , REG > PllsrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSI clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Pllsrc :: Hsi) } # [doc = "HSE oscillator clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Pllsrc :: Hse) } } # [doc = "Field `PLLQ` reader - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] pub type PllqR = crate :: FieldReader ; # [doc = "Field `PLLQ` writer - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] pub type PllqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] # [inline (always)] pub fn pllm (& self) -> PllmR { PllmR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:14 - Main PLL (PLL) multiplication factor for VCO"] # [inline (always)] pub fn plln (& self) -> PllnR { PllnR :: new (((self . bits >> 6) & 0x01ff) as u16) } # [doc = "Bits 16:17 - Main PLL (PLL) division factor for main system clock"] # [inline (always)] pub fn pllp (& self) -> PllpR { PllpR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] # [inline (always)] pub fn pllsrc (& self) -> PllsrcR { PllsrcR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] # [inline (always)] pub fn pllq (& self) -> PllqR { PllqR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] # [inline (always)] pub fn pllm (& mut self) -> PllmW < PllcfgrSpec > { PllmW :: new (self , 0) } # [doc = "Bits 6:14 - Main PLL (PLL) multiplication factor for VCO"] # [inline (always)] pub fn plln (& mut self) -> PllnW < PllcfgrSpec > { PllnW :: new (self , 6) } # [doc = "Bits 16:17 - Main PLL (PLL) division factor for main system clock"] # [inline (always)] pub fn pllp (& mut self) -> PllpW < PllcfgrSpec > { PllpW :: new (self , 16) } # [doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] # [inline (always)] pub fn pllsrc (& mut self) -> PllsrcW <'_, PllcfgrSpec > { PllsrcW :: new (self , 22) } # [doc = "Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] # [inline (always)] pub fn pllq (& mut self) -> PllqW < PllcfgrSpec > { PllqW :: new (self , 24) } } # [doc = "PLL configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pllcfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllcfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PllcfgrSpec ; impl crate :: RegisterSpec for PllcfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pllcfgr::R`](R) reader structure"] impl crate :: Readable for PllcfgrSpec { } # [doc = "`write(|w| ..)` method takes [`pllcfgr::W`](W) writer structure"] impl crate :: Writable for PllcfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PLLCFGR to value 0x2400_3010"] impl crate :: Resettable for PllcfgrSpec { const RESET_VALUE : u32 = 0x2400_3010 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/pllcfgr.rs:1:6672 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn pllq (& mut self) -> PllqW < PllcfgrSpec > { PllqW :: new (self , 24) } } # [doc = "PLL configuration regist... [INFO] [stdout] | ^^^^^^^^^^ --------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `PLLCFGR` reader"] pub type R = crate :: R < PllcfgrSpec > ; # [doc = "Register `PLLCFGR` writer"] pub type W = crate :: W < PllcfgrSpec > ; # [doc = "Field `PLLM` reader - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] pub type PllmR = crate :: FieldReader ; # [doc = "Field `PLLM` writer - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] pub type PllmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `PLLN` reader - Main PLL (PLL) multiplication factor for VCO"] pub type PllnR = crate :: FieldReader < u16 > ; # [doc = "Field `PLLN` writer - Main PLL (PLL) multiplication factor for VCO"] pub type PllnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Main PLL (PLL) division factor for main system clock\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Pllp { # [doc = "0: PLLP=2"] Div2 = 0 , # [doc = "1: PLLP=4"] Div4 = 1 , # [doc = "2: PLLP=6"] Div6 = 2 , # [doc = "3: PLLP=8"] Div8 = 3 , } impl From < Pllp > for u8 { # [inline (always)] fn from (variant : Pllp) -> Self { variant as _ } } impl crate :: FieldSpec for Pllp { type Ux = u8 ; } impl crate :: IsEnum for Pllp { } # [doc = "Field `PLLP` reader - Main PLL (PLL) division factor for main system clock"] pub type PllpR = crate :: FieldReader < Pllp > ; impl PllpR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pllp { match self . bits { 0 => Pllp :: Div2 , 1 => Pllp :: Div4 , 2 => Pllp :: Div6 , 3 => Pllp :: Div8 , _ => unreachable ! () , } } # [doc = "PLLP=2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Pllp :: Div2 } # [doc = "PLLP=4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Pllp :: Div4 } # [doc = "PLLP=6"] # [inline (always)] pub fn is_div6 (& self) -> bool { * self == Pllp :: Div6 } # [doc = "PLLP=8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Pllp :: Div8 } } # [doc = "Field `PLLP` writer - Main PLL (PLL) division factor for main system clock"] pub type PllpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Pllp , crate :: Safe > ; impl < 'a , REG > PllpW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "PLLP=2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div2) } # [doc = "PLLP=4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div4) } # [doc = "PLLP=6"] # [inline (always)] pub fn div6 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div6) } # [doc = "PLLP=8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Pllp :: Div8) } } # [doc = "Main PLL(PLL) and audio PLL (PLLI2S) entry clock source\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pllsrc { # [doc = "0: HSI clock selected as PLL and PLLI2S clock entry"] Hsi = 0 , # [doc = "1: HSE oscillator clock selected as PLL and PLLI2S clock entry"] Hse = 1 , } impl From < Pllsrc > for bool { # [inline (always)] fn from (variant : Pllsrc) -> Self { variant as u8 != 0 } } # [doc = "Field `PLLSRC` reader - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] pub type PllsrcR = crate :: BitReader < Pllsrc > ; impl PllsrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Pllsrc { match self . bits { false => Pllsrc :: Hsi , true => Pllsrc :: Hse , } } # [doc = "HSI clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Pllsrc :: Hsi } # [doc = "HSE oscillator clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Pllsrc :: Hse } } # [doc = "Field `PLLSRC` writer - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] pub type PllsrcW < 'a , REG > = crate :: BitWriter < 'a , REG , Pllsrc > ; impl < 'a , REG > PllsrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HSI clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Pllsrc :: Hsi) } # [doc = "HSE oscillator clock selected as PLL and PLLI2S clock entry"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Pllsrc :: Hse) } } # [doc = "Field `PLLQ` reader - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] pub type PllqR = crate :: FieldReader ; # [doc = "Field `PLLQ` writer - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] pub type PllqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] # [inline (always)] pub fn pllm (& self) -> PllmR { PllmR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:14 - Main PLL (PLL) multiplication factor for VCO"] # [inline (always)] pub fn plln (& self) -> PllnR { PllnR :: new (((self . bits >> 6) & 0x01ff) as u16) } # [doc = "Bits 16:17 - Main PLL (PLL) division factor for main system clock"] # [inline (always)] pub fn pllp (& self) -> PllpR { PllpR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] # [inline (always)] pub fn pllsrc (& self) -> PllsrcR { PllsrcR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] # [inline (always)] pub fn pllq (& self) -> PllqR { PllqR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"] # [inline (always)] pub fn pllm (& mut self) -> PllmW < PllcfgrSpec > { PllmW :: new (self , 0) } # [doc = "Bits 6:14 - Main PLL (PLL) multiplication factor for VCO"] # [inline (always)] pub fn plln (& mut self) -> PllnW < PllcfgrSpec > { PllnW :: new (self , 6) } # [doc = "Bits 16:17 - Main PLL (PLL) division factor for main system clock"] # [inline (always)] pub fn pllp (& mut self) -> PllpW < PllcfgrSpec > { PllpW :: new (self , 16) } # [doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"] # [inline (always)] pub fn pllsrc (& mut self) -> PllsrcW < PllcfgrSpec > { PllsrcW :: new (self , 22) } # [doc = "Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"] # [inline (always)] pub fn pllq (& mut self) -> PllqW <'_, PllcfgrSpec > { PllqW :: new (self , 24) } } # [doc = "PLL configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pllcfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllcfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PllcfgrSpec ; impl crate :: RegisterSpec for PllcfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pllcfgr::R`](R) reader structure"] impl crate :: Readable for PllcfgrSpec { } # [doc = "`write(|w| ..)` method takes [`pllcfgr::W`](W) writer structure"] impl crate :: Writable for PllcfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets PLLCFGR to value 0x2400_3010"] impl crate :: Resettable for PllcfgrSpec { const RESET_VALUE : u32 = 0x2400_3010 ; } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rng/cr.rs:1:3399 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn rngen (& mut self) -> RngenW < CrSpec > { RngenW :: new (self , 2) } # [doc = "Bit 3 - Interrupt enable"] #... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] = note: `#[warn(mismatched_lifetime_syntaxes)]` on by default [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Random number generator enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Rngen { # [doc = "0: Random number generator is disabled"] Disabled = 0 , # [doc = "1: Random number generator is enabled"] Enabled = 1 , } impl From < Rngen > for bool { # [inline (always)] fn from (variant : Rngen) -> Self { variant as u8 != 0 } } # [doc = "Field `RNGEN` reader - Random number generator enable"] pub type RngenR = crate :: BitReader < Rngen > ; impl RngenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Rngen { match self . bits { false => Rngen :: Disabled , true => Rngen :: Enabled , } } # [doc = "Random number generator is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Rngen :: Disabled } # [doc = "Random number generator is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Rngen :: Enabled } } # [doc = "Field `RNGEN` writer - Random number generator enable"] pub type RngenW < 'a , REG > = crate :: BitWriter < 'a , REG , Rngen > ; impl < 'a , REG > RngenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Random number generator is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Rngen :: Disabled) } # [doc = "Random number generator is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Rngen :: Enabled) } } # [doc = "Interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ie { # [doc = "0: RNG interrupt is disabled"] Disabled = 0 , # [doc = "1: RNG interrupt is enabled"] Enabled = 1 , } impl From < Ie > for bool { # [inline (always)] fn from (variant : Ie) -> Self { variant as u8 != 0 } } # [doc = "Field `IE` reader - Interrupt enable"] pub type IeR = crate :: BitReader < Ie > ; impl IeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ie { match self . bits { false => Ie :: Disabled , true => Ie :: Enabled , } } # [doc = "RNG interrupt is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ie :: Disabled } # [doc = "RNG interrupt is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ie :: Enabled } } # [doc = "Field `IE` writer - Interrupt enable"] pub type IeW < 'a , REG > = crate :: BitWriter < 'a , REG , Ie > ; impl < 'a , REG > IeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RNG interrupt is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ie :: Disabled) } # [doc = "RNG interrupt is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ie :: Enabled) } } impl R { # [doc = "Bit 2 - Random number generator enable"] # [inline (always)] pub fn rngen (& self) -> RngenR { RngenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Interrupt enable"] # [inline (always)] pub fn ie (& self) -> IeR { IeR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 2 - Random number generator enable"] # [inline (always)] pub fn rngen (& mut self) -> RngenW <'_, CrSpec > { RngenW :: new (self , 2) } # [doc = "Bit 3 - Interrupt enable"] # [inline (always)] pub fn ie (& mut self) -> IeW < CrSpec > { IeW :: new (self , 3) } } # [doc = "control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rng/cr.rs:1:3529 [INFO] [stdout] | [INFO] [stdout] 1 | ...le"] # [inline (always)] pub fn ie (& mut self) -> IeW < CrSpec > { IeW :: new (self , 3) } } # [doc = "control register\n\nYou can [`... [INFO] [stdout] | ^^^^^^^^^^ -------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Random number generator enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Rngen { # [doc = "0: Random number generator is disabled"] Disabled = 0 , # [doc = "1: Random number generator is enabled"] Enabled = 1 , } impl From < Rngen > for bool { # [inline (always)] fn from (variant : Rngen) -> Self { variant as u8 != 0 } } # [doc = "Field `RNGEN` reader - Random number generator enable"] pub type RngenR = crate :: BitReader < Rngen > ; impl RngenR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Rngen { match self . bits { false => Rngen :: Disabled , true => Rngen :: Enabled , } } # [doc = "Random number generator is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Rngen :: Disabled } # [doc = "Random number generator is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Rngen :: Enabled } } # [doc = "Field `RNGEN` writer - Random number generator enable"] pub type RngenW < 'a , REG > = crate :: BitWriter < 'a , REG , Rngen > ; impl < 'a , REG > RngenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "Random number generator is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Rngen :: Disabled) } # [doc = "Random number generator is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Rngen :: Enabled) } } # [doc = "Interrupt enable\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ie { # [doc = "0: RNG interrupt is disabled"] Disabled = 0 , # [doc = "1: RNG interrupt is enabled"] Enabled = 1 , } impl From < Ie > for bool { # [inline (always)] fn from (variant : Ie) -> Self { variant as u8 != 0 } } # [doc = "Field `IE` reader - Interrupt enable"] pub type IeR = crate :: BitReader < Ie > ; impl IeR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ie { match self . bits { false => Ie :: Disabled , true => Ie :: Enabled , } } # [doc = "RNG interrupt is disabled"] # [inline (always)] pub fn is_disabled (& self) -> bool { * self == Ie :: Disabled } # [doc = "RNG interrupt is enabled"] # [inline (always)] pub fn is_enabled (& self) -> bool { * self == Ie :: Enabled } } # [doc = "Field `IE` writer - Interrupt enable"] pub type IeW < 'a , REG > = crate :: BitWriter < 'a , REG , Ie > ; impl < 'a , REG > IeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RNG interrupt is disabled"] # [inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ie :: Disabled) } # [doc = "RNG interrupt is enabled"] # [inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Ie :: Enabled) } } impl R { # [doc = "Bit 2 - Random number generator enable"] # [inline (always)] pub fn rngen (& self) -> RngenR { RngenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Interrupt enable"] # [inline (always)] pub fn ie (& self) -> IeR { IeR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 2 - Random number generator enable"] # [inline (always)] pub fn rngen (& mut self) -> RngenW < CrSpec > { RngenW :: new (self , 2) } # [doc = "Bit 3 - Interrupt enable"] # [inline (always)] pub fn ie (& mut self) -> IeW <'_, CrSpec > { IeW :: new (self , 3) } } # [doc = "control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cfgr.rs:1:20811 [INFO] [stdout] | [INFO] [stdout] 1 | ...h"] # [inline (always)] pub fn sw (& mut self) -> SwW < CfgrSpec > { SwW :: new (self , 0) } # [doc = "Bits 2:3 - System clock switch ... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGR` reader"] pub type R = crate :: R < CfgrSpec > ; # [doc = "Register `CFGR` writer"] pub type W = crate :: W < CfgrSpec > ; # [doc = "System clock switch\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Sw { # [doc = "0: HSI selected as system clock"] Hsi = 0 , # [doc = "1: HSE selected as system clock"] Hse = 1 , # [doc = "2: PLL selected as system clock"] Pll = 2 , } impl From < Sw > for u8 { # [inline (always)] fn from (variant : Sw) -> Self { variant as _ } } impl crate :: FieldSpec for Sw { type Ux = u8 ; } impl crate :: IsEnum for Sw { } # [doc = "Field `SW` reader - System clock switch"] pub type SwR = crate :: FieldReader < Sw > ; impl SwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Sw > { match self . bits { 0 => Some (Sw :: Hsi) , 1 => Some (Sw :: Hse) , 2 => Some (Sw :: Pll) , _ => None , } } # [doc = "HSI selected as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Sw :: Hsi } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Sw :: Hse } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Sw :: Pll } } # [doc = "Field `SW` writer - System clock switch"] pub type SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Sw > ; impl < 'a , REG > SwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI selected as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hsi) } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hse) } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Pll) } } # [doc = "System clock switch status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Swsr { # [doc = "0: HSI oscillator used as system clock"] Hsi = 0 , # [doc = "1: HSE oscillator used as system clock"] Hse = 1 , # [doc = "2: PLL used as system clock"] Pll = 2 , } impl From < Swsr > for u8 { # [inline (always)] fn from (variant : Swsr) -> Self { variant as _ } } impl crate :: FieldSpec for Swsr { type Ux = u8 ; } impl crate :: IsEnum for Swsr { } # [doc = "Field `SWS` reader - System clock switch status"] pub type SwsR = crate :: FieldReader < Swsr > ; impl SwsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Swsr > { match self . bits { 0 => Some (Swsr :: Hsi) , 1 => Some (Swsr :: Hse) , 2 => Some (Swsr :: Pll) , _ => None , } } # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Swsr :: Hsi } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Swsr :: Hse } # [doc = "PLL used as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Swsr :: Pll } } # [doc = "Field `SWS` writer - System clock switch status"] pub type SwsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Swsr > ; impl < 'a , REG > SwsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hsi) } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hse) } # [doc = "PLL used as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Pll) } } # [doc = "AHB prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Hpre { # [doc = "8: SYSCLK divided by 2"] Div2 = 8 , # [doc = "9: SYSCLK divided by 4"] Div4 = 9 , # [doc = "10: SYSCLK divided by 8"] Div8 = 10 , # [doc = "11: SYSCLK divided by 16"] Div16 = 11 , # [doc = "12: SYSCLK divided by 64"] Div64 = 12 , # [doc = "13: SYSCLK divided by 128"] Div128 = 13 , # [doc = "14: SYSCLK divided by 256"] Div256 = 14 , # [doc = "15: SYSCLK divided by 512"] Div512 = 15 , # [doc = "0: SYSCLK not divided"] Div1 = 0 , } impl From < Hpre > for u8 { # [inline (always)] fn from (variant : Hpre) -> Self { variant as _ } } impl crate :: FieldSpec for Hpre { type Ux = u8 ; } impl crate :: IsEnum for Hpre { } # [doc = "Field `HPRE` reader - AHB prescaler"] pub type HpreR = crate :: FieldReader < Hpre > ; impl HpreR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hpre { match self . bits { 8 => Hpre :: Div2 , 9 => Hpre :: Div4 , 10 => Hpre :: Div8 , 11 => Hpre :: Div16 , 12 => Hpre :: Div64 , 13 => Hpre :: Div128 , 14 => Hpre :: Div256 , 15 => Hpre :: Div512 , _ => Hpre :: Div1 , } } # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Hpre :: Div2 } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Hpre :: Div4 } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Hpre :: Div8 } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Hpre :: Div16 } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn is_div64 (& self) -> bool { * self == Hpre :: Div64 } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn is_div128 (& self) -> bool { * self == Hpre :: Div128 } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn is_div256 (& self) -> bool { * self == Hpre :: Div256 } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn is_div512 (& self) -> bool { * self == Hpre :: Div512 } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Hpre :: Div1) } } # [doc = "Field `HPRE` writer - AHB prescaler"] pub type HpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , Hpre , crate :: Safe > ; impl < 'a , REG > HpreW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div2) } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div4) } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div8) } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div16) } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn div64 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div64) } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn div128 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div128) } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn div256 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div256) } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn div512 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div512) } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div1) } } # [doc = "APB Low speed prescaler (APB1)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Ppre1 { # [doc = "4: HCLK divided by 2"] Div2 = 4 , # [doc = "5: HCLK divided by 4"] Div4 = 5 , # [doc = "6: HCLK divided by 8"] Div8 = 6 , # [doc = "7: HCLK divided by 16"] Div16 = 7 , # [doc = "0: HCLK not divided"] Div1 = 0 , } impl From < Ppre1 > for u8 { # [inline (always)] fn from (variant : Ppre1) -> Self { variant as _ } } impl crate :: FieldSpec for Ppre1 { type Ux = u8 ; } impl crate :: IsEnum for Ppre1 { } # [doc = "Field `PPRE1` reader - APB Low speed prescaler (APB1)"] pub type Ppre1R = crate :: FieldReader < Ppre1 > ; impl Ppre1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ppre1 { match self . bits { 4 => Ppre1 :: Div2 , 5 => Ppre1 :: Div4 , 6 => Ppre1 :: Div8 , 7 => Ppre1 :: Div16 , _ => Ppre1 :: Div1 , } } # [doc = "HCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Ppre1 :: Div2 } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Ppre1 :: Div4 } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Ppre1 :: Div8 } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Ppre1 :: Div16 } # [doc = "HCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Ppre1 :: Div1) } } # [doc = "Field `PPRE1` writer - APB Low speed prescaler (APB1)"] pub type Ppre1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Ppre1 , crate :: Safe > ; impl < 'a , REG > Ppre1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div2) } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div4) } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div8) } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div16) } # [doc = "HCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div1) } } # [doc = "Field `PPRE2` reader - APB high-speed prescaler (APB2)"] pub use Ppre1R as Ppre2R ; # [doc = "Field `PPRE2` writer - APB high-speed prescaler (APB2)"] pub use Ppre1W as Ppre2W ; # [doc = "Field `RTCPRE` reader - HSE division factor for RTC clock"] pub type RtcpreR = crate :: FieldReader ; # [doc = "Field `RTCPRE` writer - HSE division factor for RTC clock"] pub type RtcpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Microcontroller clock output 1\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1 { # [doc = "0: HSI clock selected"] Hsi = 0 , # [doc = "1: LSE oscillator selected"] Lse = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco1 > for u8 { # [inline (always)] fn from (variant : Mco1) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1 { type Ux = u8 ; } impl crate :: IsEnum for Mco1 { } # [doc = "Field `MCO1` reader - Microcontroller clock output 1"] pub type Mco1R = crate :: FieldReader < Mco1 > ; impl Mco1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1 { match self . bits { 0 => Mco1 :: Hsi , 1 => Mco1 :: Lse , 2 => Mco1 :: Hse , 3 => Mco1 :: Pll , _ => unreachable ! () , } } # [doc = "HSI clock selected"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Mco1 :: Hsi } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn is_lse (& self) -> bool { * self == Mco1 :: Lse } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco1 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco1 :: Pll } } # [doc = "Field `MCO1` writer - Microcontroller clock output 1"] pub type Mco1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco1 , crate :: Safe > ; impl < 'a , REG > Mco1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI clock selected"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hsi) } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn lse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Lse) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Pll) } } # [doc = "I2S clock selection\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum I2ssrc { # [doc = "0: PLLI2S clock used as I2S clock source"] Plli2s = 0 , # [doc = "1: External clock mapped on the I2S_CKIN pin used as I2S clock source"] Ckin = 1 , } impl From < I2ssrc > for bool { # [inline (always)] fn from (variant : I2ssrc) -> Self { variant as u8 != 0 } } # [doc = "Field `I2SSRC` reader - I2S clock selection"] pub type I2ssrcR = crate :: BitReader < I2ssrc > ; impl I2ssrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> I2ssrc { match self . bits { false => I2ssrc :: Plli2s , true => I2ssrc :: Ckin , } } # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == I2ssrc :: Plli2s } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn is_ckin (& self) -> bool { * self == I2ssrc :: Ckin } } # [doc = "Field `I2SSRC` writer - I2S clock selection"] pub type I2ssrcW < 'a , REG > = crate :: BitWriter < 'a , REG , I2ssrc > ; impl < 'a , REG > I2ssrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Plli2s) } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn ckin (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Ckin) } } # [doc = "MCO1 prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1pre { # [doc = "4: Division by 2"] Div2 = 4 , # [doc = "5: Division by 3"] Div3 = 5 , # [doc = "6: Division by 4"] Div4 = 6 , # [doc = "7: Division by 5"] Div5 = 7 , # [doc = "0: No division"] Div1 = 0 , } impl From < Mco1pre > for u8 { # [inline (always)] fn from (variant : Mco1pre) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1pre { type Ux = u8 ; } impl crate :: IsEnum for Mco1pre { } # [doc = "Field `MCO1PRE` reader - MCO1 prescaler"] pub type Mco1preR = crate :: FieldReader < Mco1pre > ; impl Mco1preR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1pre { match self . bits { 4 => Mco1pre :: Div2 , 5 => Mco1pre :: Div3 , 6 => Mco1pre :: Div4 , 7 => Mco1pre :: Div5 , _ => Mco1pre :: Div1 , } } # [doc = "Division by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Mco1pre :: Div2 } # [doc = "Division by 3"] # [inline (always)] pub fn is_div3 (& self) -> bool { * self == Mco1pre :: Div3 } # [doc = "Division by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Mco1pre :: Div4 } # [doc = "Division by 5"] # [inline (always)] pub fn is_div5 (& self) -> bool { * self == Mco1pre :: Div5 } # [doc = "No division"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Mco1pre :: Div1) } } # [doc = "Field `MCO1PRE` writer - MCO1 prescaler"] pub type Mco1preW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Mco1pre , crate :: Safe > ; impl < 'a , REG > Mco1preW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Division by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div2) } # [doc = "Division by 3"] # [inline (always)] pub fn div3 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div3) } # [doc = "Division by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div4) } # [doc = "Division by 5"] # [inline (always)] pub fn div5 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div5) } # [doc = "No division"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div1) } } # [doc = "Field `MCO2PRE` reader - MCO2 prescaler"] pub use Mco1preR as Mco2preR ; # [doc = "Field `MCO2PRE` writer - MCO2 prescaler"] pub use Mco1preW as Mco2preW ; # [doc = "Microcontroller clock output 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco2 { # [doc = "0: System clock (SYSCLK) selected"] Sysclk = 0 , # [doc = "1: PLLI2S clock selected"] Plli2s = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco2 > for u8 { # [inline (always)] fn from (variant : Mco2) -> Self { variant as _ } } impl crate :: FieldSpec for Mco2 { type Ux = u8 ; } impl crate :: IsEnum for Mco2 { } # [doc = "Field `MCO2` reader - Microcontroller clock output 2"] pub type Mco2R = crate :: FieldReader < Mco2 > ; impl Mco2R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco2 { match self . bits { 0 => Mco2 :: Sysclk , 1 => Mco2 :: Plli2s , 2 => Mco2 :: Hse , 3 => Mco2 :: Pll , _ => unreachable ! () , } } # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn is_sysclk (& self) -> bool { * self == Mco2 :: Sysclk } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == Mco2 :: Plli2s } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco2 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco2 :: Pll } } # [doc = "Field `MCO2` writer - Microcontroller clock output 2"] pub type Mco2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco2 , crate :: Safe > ; impl < 'a , REG > Mco2W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn sysclk (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Sysclk) } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Plli2s) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Pll) } } impl R { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& self) -> SwR { SwR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& self) -> SwsR { SwsR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& self) -> HpreR { HpreR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& self) -> Ppre1R { Ppre1R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& self) -> Ppre2R { Ppre2R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& self) -> RtcpreR { RtcpreR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& self) -> Mco1R { Mco1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& self) -> I2ssrcR { I2ssrcR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& self) -> Mco1preR { Mco1preR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& self) -> Mco2preR { Mco2preR :: new (((self . bits >> 27) & 7) as u8) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& self) -> Mco2R { Mco2R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& mut self) -> SwW <'_, CfgrSpec > { SwW :: new (self , 0) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& mut self) -> SwsW < CfgrSpec > { SwsW :: new (self , 2) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& mut self) -> HpreW < CfgrSpec > { HpreW :: new (self , 4) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& mut self) -> Ppre1W < CfgrSpec > { Ppre1W :: new (self , 10) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& mut self) -> Ppre2W < CfgrSpec > { Ppre2W :: new (self , 13) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& mut self) -> RtcpreW < CfgrSpec > { RtcpreW :: new (self , 16) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& mut self) -> Mco1W < CfgrSpec > { Mco1W :: new (self , 21) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& mut self) -> I2ssrcW < CfgrSpec > { I2ssrcW :: new (self , 23) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& mut self) -> Mco1preW < CfgrSpec > { Mco1preW :: new (self , 24) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& mut self) -> Mco2preW < CfgrSpec > { Mco2preW :: new (self , 27) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& mut self) -> Mco2W < CfgrSpec > { Mco2W :: new (self , 30) } } # [doc = "clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgrSpec ; impl crate :: RegisterSpec for CfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr::R`](R) reader structure"] impl crate :: Readable for CfgrSpec { } # [doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"] impl crate :: Writable for CfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CFGR to value 0"] impl crate :: Resettable for CfgrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rng/sr.rs:1:8324 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn ceis (& mut self) -> CeisW < SrSpec > { CeisW :: new (self , 5) } # [doc = "Bit 6 - Seed error interrupt ... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SR` reader"] pub type R = crate :: R < SrSpec > ; # [doc = "Register `SR` writer"] pub type W = crate :: W < SrSpec > ; # [doc = "Data ready\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Drdy { # [doc = "0: The RNG_DR register is not yet valid, no random data is available"] NotValid = 0 , # [doc = "1: The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated."] Valid = 1 , } impl From < Drdy > for bool { # [inline (always)] fn from (variant : Drdy) -> Self { variant as u8 != 0 } } # [doc = "Field `DRDY` reader - Data ready"] pub type DrdyR = crate :: BitReader < Drdy > ; impl DrdyR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Drdy { match self . bits { false => Drdy :: NotValid , true => Drdy :: Valid , } } # [doc = "The RNG_DR register is not yet valid, no random data is available"] # [inline (always)] pub fn is_not_valid (& self) -> bool { * self == Drdy :: NotValid } # [doc = "The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated."] # [inline (always)] pub fn is_valid (& self) -> bool { * self == Drdy :: Valid } } # [doc = "Clock error current status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cecs { # [doc = "0: The RNG clock is correct (fRNGCLK> fHCLK/16). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered."] Correct = 0 , # [doc = "1: The RNG clock is too slow (fRNGCLK< fHCLK/16)"] TooSlow = 1 , } impl From < Cecs > for bool { # [inline (always)] fn from (variant : Cecs) -> Self { variant as u8 != 0 } } # [doc = "Field `CECS` reader - Clock error current status"] pub type CecsR = crate :: BitReader < Cecs > ; impl CecsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cecs { match self . bits { false => Cecs :: Correct , true => Cecs :: TooSlow , } } # [doc = "The RNG clock is correct (fRNGCLK> fHCLK/16). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered."] # [inline (always)] pub fn is_correct (& self) -> bool { * self == Cecs :: Correct } # [doc = "The RNG clock is too slow (fRNGCLK< fHCLK/16)"] # [inline (always)] pub fn is_too_slow (& self) -> bool { * self == Cecs :: TooSlow } } # [doc = "Seed error current status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Secs { # [doc = "0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered."] NoFaulty = 0 , # [doc = "1: One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bits patterns (“01” or “10”)"] Faulty = 1 , } impl From < Secs > for bool { # [inline (always)] fn from (variant : Secs) -> Self { variant as u8 != 0 } } # [doc = "Field `SECS` reader - Seed error current status"] pub type SecsR = crate :: BitReader < Secs > ; impl SecsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Secs { match self . bits { false => Secs :: NoFaulty , true => Secs :: Faulty , } } # [doc = "No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered."] # [inline (always)] pub fn is_no_faulty (& self) -> bool { * self == Secs :: NoFaulty } # [doc = "One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bits patterns (“01” or “10”)"] # [inline (always)] pub fn is_faulty (& self) -> bool { * self == Secs :: Faulty } } # [doc = "Clock error interrupt status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ceis { # [doc = "0: The RNG clock is correct (fRNGCLK > fHCLK/16)"] Correct = 0 , # [doc = "1: The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] TooSlow = 1 , } impl From < Ceis > for bool { # [inline (always)] fn from (variant : Ceis) -> Self { variant as u8 != 0 } } # [doc = "Field `CEIS` reader - Clock error interrupt status"] pub type CeisR = crate :: BitReader < Ceis > ; impl CeisR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ceis { match self . bits { false => Ceis :: Correct , true => Ceis :: TooSlow , } } # [doc = "The RNG clock is correct (fRNGCLK > fHCLK/16)"] # [inline (always)] pub fn is_correct (& self) -> bool { * self == Ceis :: Correct } # [doc = "The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] # [inline (always)] pub fn is_too_slow (& self) -> bool { * self == Ceis :: TooSlow } } # [doc = "Field `CEIS` writer - Clock error interrupt status"] pub type CeisW < 'a , REG > = crate :: BitWriter < 'a , REG , Ceis > ; impl < 'a , REG > CeisW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The RNG clock is correct (fRNGCLK > fHCLK/16)"] # [inline (always)] pub fn correct (self) -> & 'a mut crate :: W < REG > { self . variant (Ceis :: Correct) } # [doc = "The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] # [inline (always)] pub fn too_slow (self) -> & 'a mut crate :: W < REG > { self . variant (Ceis :: TooSlow) } } # [doc = "Seed error interrupt status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Seis { # [doc = "0: No faulty sequence detected"] NoFaulty = 0 , # [doc = "1: At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] Faulty = 1 , } impl From < Seis > for bool { # [inline (always)] fn from (variant : Seis) -> Self { variant as u8 != 0 } } # [doc = "Field `SEIS` reader - Seed error interrupt status"] pub type SeisR = crate :: BitReader < Seis > ; impl SeisR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Seis { match self . bits { false => Seis :: NoFaulty , true => Seis :: Faulty , } } # [doc = "No faulty sequence detected"] # [inline (always)] pub fn is_no_faulty (& self) -> bool { * self == Seis :: NoFaulty } # [doc = "At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] # [inline (always)] pub fn is_faulty (& self) -> bool { * self == Seis :: Faulty } } # [doc = "Field `SEIS` writer - Seed error interrupt status"] pub type SeisW < 'a , REG > = crate :: BitWriter < 'a , REG , Seis > ; impl < 'a , REG > SeisW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No faulty sequence detected"] # [inline (always)] pub fn no_faulty (self) -> & 'a mut crate :: W < REG > { self . variant (Seis :: NoFaulty) } # [doc = "At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] # [inline (always)] pub fn faulty (self) -> & 'a mut crate :: W < REG > { self . variant (Seis :: Faulty) } } impl R { # [doc = "Bit 0 - Data ready"] # [inline (always)] pub fn drdy (& self) -> DrdyR { DrdyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Clock error current status"] # [inline (always)] pub fn cecs (& self) -> CecsR { CecsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Seed error current status"] # [inline (always)] pub fn secs (& self) -> SecsR { SecsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - Clock error interrupt status"] # [inline (always)] pub fn ceis (& self) -> CeisR { CeisR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Seed error interrupt status"] # [inline (always)] pub fn seis (& self) -> SeisR { SeisR :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bit 5 - Clock error interrupt status"] # [inline (always)] pub fn ceis (& mut self) -> CeisW <'_, SrSpec > { CeisW :: new (self , 5) } # [doc = "Bit 6 - Seed error interrupt status"] # [inline (always)] pub fn seis (& mut self) -> SeisW < SrSpec > { SeisW :: new (self , 6) } } # [doc = "status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SrSpec ; impl crate :: RegisterSpec for SrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sr::R`](R) reader structure"] impl crate :: Readable for SrSpec { } # [doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] impl crate :: Writable for SrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SR to value 0"] impl crate :: Resettable for SrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rng/sr.rs:1:8465 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn seis (& mut self) -> SeisW < SrSpec > { SeisW :: new (self , 6) } } # [doc = "status register\n\nYou can ... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `SR` reader"] pub type R = crate :: R < SrSpec > ; # [doc = "Register `SR` writer"] pub type W = crate :: W < SrSpec > ; # [doc = "Data ready\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Drdy { # [doc = "0: The RNG_DR register is not yet valid, no random data is available"] NotValid = 0 , # [doc = "1: The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated."] Valid = 1 , } impl From < Drdy > for bool { # [inline (always)] fn from (variant : Drdy) -> Self { variant as u8 != 0 } } # [doc = "Field `DRDY` reader - Data ready"] pub type DrdyR = crate :: BitReader < Drdy > ; impl DrdyR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Drdy { match self . bits { false => Drdy :: NotValid , true => Drdy :: Valid , } } # [doc = "The RNG_DR register is not yet valid, no random data is available"] # [inline (always)] pub fn is_not_valid (& self) -> bool { * self == Drdy :: NotValid } # [doc = "The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated."] # [inline (always)] pub fn is_valid (& self) -> bool { * self == Drdy :: Valid } } # [doc = "Clock error current status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Cecs { # [doc = "0: The RNG clock is correct (fRNGCLK> fHCLK/16). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered."] Correct = 0 , # [doc = "1: The RNG clock is too slow (fRNGCLK< fHCLK/16)"] TooSlow = 1 , } impl From < Cecs > for bool { # [inline (always)] fn from (variant : Cecs) -> Self { variant as u8 != 0 } } # [doc = "Field `CECS` reader - Clock error current status"] pub type CecsR = crate :: BitReader < Cecs > ; impl CecsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Cecs { match self . bits { false => Cecs :: Correct , true => Cecs :: TooSlow , } } # [doc = "The RNG clock is correct (fRNGCLK> fHCLK/16). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered."] # [inline (always)] pub fn is_correct (& self) -> bool { * self == Cecs :: Correct } # [doc = "The RNG clock is too slow (fRNGCLK< fHCLK/16)"] # [inline (always)] pub fn is_too_slow (& self) -> bool { * self == Cecs :: TooSlow } } # [doc = "Seed error current status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Secs { # [doc = "0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered."] NoFaulty = 0 , # [doc = "1: One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bits patterns (“01” or “10”)"] Faulty = 1 , } impl From < Secs > for bool { # [inline (always)] fn from (variant : Secs) -> Self { variant as u8 != 0 } } # [doc = "Field `SECS` reader - Seed error current status"] pub type SecsR = crate :: BitReader < Secs > ; impl SecsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Secs { match self . bits { false => Secs :: NoFaulty , true => Secs :: Faulty , } } # [doc = "No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered."] # [inline (always)] pub fn is_no_faulty (& self) -> bool { * self == Secs :: NoFaulty } # [doc = "One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bits patterns (“01” or “10”)"] # [inline (always)] pub fn is_faulty (& self) -> bool { * self == Secs :: Faulty } } # [doc = "Clock error interrupt status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Ceis { # [doc = "0: The RNG clock is correct (fRNGCLK > fHCLK/16)"] Correct = 0 , # [doc = "1: The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] TooSlow = 1 , } impl From < Ceis > for bool { # [inline (always)] fn from (variant : Ceis) -> Self { variant as u8 != 0 } } # [doc = "Field `CEIS` reader - Clock error interrupt status"] pub type CeisR = crate :: BitReader < Ceis > ; impl CeisR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ceis { match self . bits { false => Ceis :: Correct , true => Ceis :: TooSlow , } } # [doc = "The RNG clock is correct (fRNGCLK > fHCLK/16)"] # [inline (always)] pub fn is_correct (& self) -> bool { * self == Ceis :: Correct } # [doc = "The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] # [inline (always)] pub fn is_too_slow (& self) -> bool { * self == Ceis :: TooSlow } } # [doc = "Field `CEIS` writer - Clock error interrupt status"] pub type CeisW < 'a , REG > = crate :: BitWriter < 'a , REG , Ceis > ; impl < 'a , REG > CeisW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "The RNG clock is correct (fRNGCLK > fHCLK/16)"] # [inline (always)] pub fn correct (self) -> & 'a mut crate :: W < REG > { self . variant (Ceis :: Correct) } # [doc = "The RNG has been detected too slow (fRNGCLK < fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register"] # [inline (always)] pub fn too_slow (self) -> & 'a mut crate :: W < REG > { self . variant (Ceis :: TooSlow) } } # [doc = "Seed error interrupt status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Seis { # [doc = "0: No faulty sequence detected"] NoFaulty = 0 , # [doc = "1: At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] Faulty = 1 , } impl From < Seis > for bool { # [inline (always)] fn from (variant : Seis) -> Self { variant as u8 != 0 } } # [doc = "Field `SEIS` reader - Seed error interrupt status"] pub type SeisR = crate :: BitReader < Seis > ; impl SeisR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Seis { match self . bits { false => Seis :: NoFaulty , true => Seis :: Faulty , } } # [doc = "No faulty sequence detected"] # [inline (always)] pub fn is_no_faulty (& self) -> bool { * self == Seis :: NoFaulty } # [doc = "At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] # [inline (always)] pub fn is_faulty (& self) -> bool { * self == Seis :: Faulty } } # [doc = "Field `SEIS` writer - Seed error interrupt status"] pub type SeisW < 'a , REG > = crate :: BitWriter < 'a , REG , Seis > ; impl < 'a , REG > SeisW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "No faulty sequence detected"] # [inline (always)] pub fn no_faulty (self) -> & 'a mut crate :: W < REG > { self . variant (Seis :: NoFaulty) } # [doc = "At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register."] # [inline (always)] pub fn faulty (self) -> & 'a mut crate :: W < REG > { self . variant (Seis :: Faulty) } } impl R { # [doc = "Bit 0 - Data ready"] # [inline (always)] pub fn drdy (& self) -> DrdyR { DrdyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Clock error current status"] # [inline (always)] pub fn cecs (& self) -> CecsR { CecsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Seed error current status"] # [inline (always)] pub fn secs (& self) -> SecsR { SecsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - Clock error interrupt status"] # [inline (always)] pub fn ceis (& self) -> CeisR { CeisR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Seed error interrupt status"] # [inline (always)] pub fn seis (& self) -> SeisR { SeisR :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bit 5 - Clock error interrupt status"] # [inline (always)] pub fn ceis (& mut self) -> CeisW < SrSpec > { CeisW :: new (self , 5) } # [doc = "Bit 6 - Seed error interrupt status"] # [inline (always)] pub fn seis (& mut self) -> SeisW <'_, SrSpec > { SeisW :: new (self , 6) } } # [doc = "status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SrSpec ; impl crate :: RegisterSpec for SrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sr::R`](R) reader structure"] impl crate :: Readable for SrSpec { } # [doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] impl crate :: Writable for SrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets SR to value 0"] impl crate :: Resettable for SrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4170 [INFO] [stdout] | [INFO] [stdout] 1 | ...inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # ... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW <'_, CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4300 [INFO] [stdout] | [INFO] [stdout] 1 | ...de"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline... [INFO] [stdout] | ^^^^^^^^^^ -------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW <'_, CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4422 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inli... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW <'_, CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4547 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronizat... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW <'_, CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cfgr.rs:1:20951 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn sws (& mut self) -> SwsW < CfgrSpec > { SwsW :: new (self , 2) } # [doc = "Bits 4:7 - AHB prescaler"] # [... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGR` reader"] pub type R = crate :: R < CfgrSpec > ; # [doc = "Register `CFGR` writer"] pub type W = crate :: W < CfgrSpec > ; # [doc = "System clock switch\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Sw { # [doc = "0: HSI selected as system clock"] Hsi = 0 , # [doc = "1: HSE selected as system clock"] Hse = 1 , # [doc = "2: PLL selected as system clock"] Pll = 2 , } impl From < Sw > for u8 { # [inline (always)] fn from (variant : Sw) -> Self { variant as _ } } impl crate :: FieldSpec for Sw { type Ux = u8 ; } impl crate :: IsEnum for Sw { } # [doc = "Field `SW` reader - System clock switch"] pub type SwR = crate :: FieldReader < Sw > ; impl SwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Sw > { match self . bits { 0 => Some (Sw :: Hsi) , 1 => Some (Sw :: Hse) , 2 => Some (Sw :: Pll) , _ => None , } } # [doc = "HSI selected as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Sw :: Hsi } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Sw :: Hse } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Sw :: Pll } } # [doc = "Field `SW` writer - System clock switch"] pub type SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Sw > ; impl < 'a , REG > SwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI selected as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hsi) } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hse) } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Pll) } } # [doc = "System clock switch status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Swsr { # [doc = "0: HSI oscillator used as system clock"] Hsi = 0 , # [doc = "1: HSE oscillator used as system clock"] Hse = 1 , # [doc = "2: PLL used as system clock"] Pll = 2 , } impl From < Swsr > for u8 { # [inline (always)] fn from (variant : Swsr) -> Self { variant as _ } } impl crate :: FieldSpec for Swsr { type Ux = u8 ; } impl crate :: IsEnum for Swsr { } # [doc = "Field `SWS` reader - System clock switch status"] pub type SwsR = crate :: FieldReader < Swsr > ; impl SwsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Swsr > { match self . bits { 0 => Some (Swsr :: Hsi) , 1 => Some (Swsr :: Hse) , 2 => Some (Swsr :: Pll) , _ => None , } } # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Swsr :: Hsi } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Swsr :: Hse } # [doc = "PLL used as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Swsr :: Pll } } # [doc = "Field `SWS` writer - System clock switch status"] pub type SwsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Swsr > ; impl < 'a , REG > SwsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hsi) } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hse) } # [doc = "PLL used as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Pll) } } # [doc = "AHB prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Hpre { # [doc = "8: SYSCLK divided by 2"] Div2 = 8 , # [doc = "9: SYSCLK divided by 4"] Div4 = 9 , # [doc = "10: SYSCLK divided by 8"] Div8 = 10 , # [doc = "11: SYSCLK divided by 16"] Div16 = 11 , # [doc = "12: SYSCLK divided by 64"] Div64 = 12 , # [doc = "13: SYSCLK divided by 128"] Div128 = 13 , # [doc = "14: SYSCLK divided by 256"] Div256 = 14 , # [doc = "15: SYSCLK divided by 512"] Div512 = 15 , # [doc = "0: SYSCLK not divided"] Div1 = 0 , } impl From < Hpre > for u8 { # [inline (always)] fn from (variant : Hpre) -> Self { variant as _ } } impl crate :: FieldSpec for Hpre { type Ux = u8 ; } impl crate :: IsEnum for Hpre { } # [doc = "Field `HPRE` reader - AHB prescaler"] pub type HpreR = crate :: FieldReader < Hpre > ; impl HpreR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hpre { match self . bits { 8 => Hpre :: Div2 , 9 => Hpre :: Div4 , 10 => Hpre :: Div8 , 11 => Hpre :: Div16 , 12 => Hpre :: Div64 , 13 => Hpre :: Div128 , 14 => Hpre :: Div256 , 15 => Hpre :: Div512 , _ => Hpre :: Div1 , } } # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Hpre :: Div2 } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Hpre :: Div4 } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Hpre :: Div8 } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Hpre :: Div16 } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn is_div64 (& self) -> bool { * self == Hpre :: Div64 } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn is_div128 (& self) -> bool { * self == Hpre :: Div128 } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn is_div256 (& self) -> bool { * self == Hpre :: Div256 } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn is_div512 (& self) -> bool { * self == Hpre :: Div512 } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Hpre :: Div1) } } # [doc = "Field `HPRE` writer - AHB prescaler"] pub type HpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , Hpre , crate :: Safe > ; impl < 'a , REG > HpreW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div2) } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div4) } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div8) } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div16) } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn div64 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div64) } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn div128 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div128) } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn div256 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div256) } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn div512 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div512) } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div1) } } # [doc = "APB Low speed prescaler (APB1)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Ppre1 { # [doc = "4: HCLK divided by 2"] Div2 = 4 , # [doc = "5: HCLK divided by 4"] Div4 = 5 , # [doc = "6: HCLK divided by 8"] Div8 = 6 , # [doc = "7: HCLK divided by 16"] Div16 = 7 , # [doc = "0: HCLK not divided"] Div1 = 0 , } impl From < Ppre1 > for u8 { # [inline (always)] fn from (variant : Ppre1) -> Self { variant as _ } } impl crate :: FieldSpec for Ppre1 { type Ux = u8 ; } impl crate :: IsEnum for Ppre1 { } # [doc = "Field `PPRE1` reader - APB Low speed prescaler (APB1)"] pub type Ppre1R = crate :: FieldReader < Ppre1 > ; impl Ppre1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ppre1 { match self . bits { 4 => Ppre1 :: Div2 , 5 => Ppre1 :: Div4 , 6 => Ppre1 :: Div8 , 7 => Ppre1 :: Div16 , _ => Ppre1 :: Div1 , } } # [doc = "HCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Ppre1 :: Div2 } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Ppre1 :: Div4 } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Ppre1 :: Div8 } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Ppre1 :: Div16 } # [doc = "HCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Ppre1 :: Div1) } } # [doc = "Field `PPRE1` writer - APB Low speed prescaler (APB1)"] pub type Ppre1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Ppre1 , crate :: Safe > ; impl < 'a , REG > Ppre1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div2) } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div4) } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div8) } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div16) } # [doc = "HCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div1) } } # [doc = "Field `PPRE2` reader - APB high-speed prescaler (APB2)"] pub use Ppre1R as Ppre2R ; # [doc = "Field `PPRE2` writer - APB high-speed prescaler (APB2)"] pub use Ppre1W as Ppre2W ; # [doc = "Field `RTCPRE` reader - HSE division factor for RTC clock"] pub type RtcpreR = crate :: FieldReader ; # [doc = "Field `RTCPRE` writer - HSE division factor for RTC clock"] pub type RtcpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Microcontroller clock output 1\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1 { # [doc = "0: HSI clock selected"] Hsi = 0 , # [doc = "1: LSE oscillator selected"] Lse = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco1 > for u8 { # [inline (always)] fn from (variant : Mco1) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1 { type Ux = u8 ; } impl crate :: IsEnum for Mco1 { } # [doc = "Field `MCO1` reader - Microcontroller clock output 1"] pub type Mco1R = crate :: FieldReader < Mco1 > ; impl Mco1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1 { match self . bits { 0 => Mco1 :: Hsi , 1 => Mco1 :: Lse , 2 => Mco1 :: Hse , 3 => Mco1 :: Pll , _ => unreachable ! () , } } # [doc = "HSI clock selected"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Mco1 :: Hsi } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn is_lse (& self) -> bool { * self == Mco1 :: Lse } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco1 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco1 :: Pll } } # [doc = "Field `MCO1` writer - Microcontroller clock output 1"] pub type Mco1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco1 , crate :: Safe > ; impl < 'a , REG > Mco1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI clock selected"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hsi) } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn lse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Lse) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Pll) } } # [doc = "I2S clock selection\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum I2ssrc { # [doc = "0: PLLI2S clock used as I2S clock source"] Plli2s = 0 , # [doc = "1: External clock mapped on the I2S_CKIN pin used as I2S clock source"] Ckin = 1 , } impl From < I2ssrc > for bool { # [inline (always)] fn from (variant : I2ssrc) -> Self { variant as u8 != 0 } } # [doc = "Field `I2SSRC` reader - I2S clock selection"] pub type I2ssrcR = crate :: BitReader < I2ssrc > ; impl I2ssrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> I2ssrc { match self . bits { false => I2ssrc :: Plli2s , true => I2ssrc :: Ckin , } } # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == I2ssrc :: Plli2s } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn is_ckin (& self) -> bool { * self == I2ssrc :: Ckin } } # [doc = "Field `I2SSRC` writer - I2S clock selection"] pub type I2ssrcW < 'a , REG > = crate :: BitWriter < 'a , REG , I2ssrc > ; impl < 'a , REG > I2ssrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Plli2s) } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn ckin (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Ckin) } } # [doc = "MCO1 prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1pre { # [doc = "4: Division by 2"] Div2 = 4 , # [doc = "5: Division by 3"] Div3 = 5 , # [doc = "6: Division by 4"] Div4 = 6 , # [doc = "7: Division by 5"] Div5 = 7 , # [doc = "0: No division"] Div1 = 0 , } impl From < Mco1pre > for u8 { # [inline (always)] fn from (variant : Mco1pre) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1pre { type Ux = u8 ; } impl crate :: IsEnum for Mco1pre { } # [doc = "Field `MCO1PRE` reader - MCO1 prescaler"] pub type Mco1preR = crate :: FieldReader < Mco1pre > ; impl Mco1preR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1pre { match self . bits { 4 => Mco1pre :: Div2 , 5 => Mco1pre :: Div3 , 6 => Mco1pre :: Div4 , 7 => Mco1pre :: Div5 , _ => Mco1pre :: Div1 , } } # [doc = "Division by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Mco1pre :: Div2 } # [doc = "Division by 3"] # [inline (always)] pub fn is_div3 (& self) -> bool { * self == Mco1pre :: Div3 } # [doc = "Division by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Mco1pre :: Div4 } # [doc = "Division by 5"] # [inline (always)] pub fn is_div5 (& self) -> bool { * self == Mco1pre :: Div5 } # [doc = "No division"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Mco1pre :: Div1) } } # [doc = "Field `MCO1PRE` writer - MCO1 prescaler"] pub type Mco1preW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Mco1pre , crate :: Safe > ; impl < 'a , REG > Mco1preW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Division by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div2) } # [doc = "Division by 3"] # [inline (always)] pub fn div3 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div3) } # [doc = "Division by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div4) } # [doc = "Division by 5"] # [inline (always)] pub fn div5 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div5) } # [doc = "No division"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div1) } } # [doc = "Field `MCO2PRE` reader - MCO2 prescaler"] pub use Mco1preR as Mco2preR ; # [doc = "Field `MCO2PRE` writer - MCO2 prescaler"] pub use Mco1preW as Mco2preW ; # [doc = "Microcontroller clock output 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco2 { # [doc = "0: System clock (SYSCLK) selected"] Sysclk = 0 , # [doc = "1: PLLI2S clock selected"] Plli2s = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco2 > for u8 { # [inline (always)] fn from (variant : Mco2) -> Self { variant as _ } } impl crate :: FieldSpec for Mco2 { type Ux = u8 ; } impl crate :: IsEnum for Mco2 { } # [doc = "Field `MCO2` reader - Microcontroller clock output 2"] pub type Mco2R = crate :: FieldReader < Mco2 > ; impl Mco2R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco2 { match self . bits { 0 => Mco2 :: Sysclk , 1 => Mco2 :: Plli2s , 2 => Mco2 :: Hse , 3 => Mco2 :: Pll , _ => unreachable ! () , } } # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn is_sysclk (& self) -> bool { * self == Mco2 :: Sysclk } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == Mco2 :: Plli2s } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco2 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco2 :: Pll } } # [doc = "Field `MCO2` writer - Microcontroller clock output 2"] pub type Mco2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco2 , crate :: Safe > ; impl < 'a , REG > Mco2W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn sysclk (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Sysclk) } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Plli2s) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Pll) } } impl R { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& self) -> SwR { SwR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& self) -> SwsR { SwsR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& self) -> HpreR { HpreR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& self) -> Ppre1R { Ppre1R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& self) -> Ppre2R { Ppre2R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& self) -> RtcpreR { RtcpreR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& self) -> Mco1R { Mco1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& self) -> I2ssrcR { I2ssrcR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& self) -> Mco1preR { Mco1preR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& self) -> Mco2preR { Mco2preR :: new (((self . bits >> 27) & 7) as u8) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& self) -> Mco2R { Mco2R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& mut self) -> SwW < CfgrSpec > { SwW :: new (self , 0) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& mut self) -> SwsW <'_, CfgrSpec > { SwsW :: new (self , 2) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& mut self) -> HpreW < CfgrSpec > { HpreW :: new (self , 4) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& mut self) -> Ppre1W < CfgrSpec > { Ppre1W :: new (self , 10) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& mut self) -> Ppre2W < CfgrSpec > { Ppre2W :: new (self , 13) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& mut self) -> RtcpreW < CfgrSpec > { RtcpreW :: new (self , 16) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& mut self) -> Mco1W < CfgrSpec > { Mco1W :: new (self , 21) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& mut self) -> I2ssrcW < CfgrSpec > { I2ssrcW :: new (self , 23) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& mut self) -> Mco1preW < CfgrSpec > { Mco1preW :: new (self , 24) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& mut self) -> Mco2preW < CfgrSpec > { Mco2preW :: new (self , 27) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& mut self) -> Mco2W < CfgrSpec > { Mco2W :: new (self , 30) } } # [doc = "clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgrSpec ; impl crate :: RegisterSpec for CfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr::R`](R) reader structure"] impl crate :: Readable for CfgrSpec { } # [doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"] impl crate :: Writable for CfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CFGR to value 0"] impl crate :: Resettable for CfgrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cfgr.rs:1:21081 [INFO] [stdout] | [INFO] [stdout] 1 | ... # [inline (always)] pub fn hpre (& mut self) -> HpreW < CfgrSpec > { HpreW :: new (self , 4) } # [doc = "Bits 10:12 - APB Low speed p... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGR` reader"] pub type R = crate :: R < CfgrSpec > ; # [doc = "Register `CFGR` writer"] pub type W = crate :: W < CfgrSpec > ; # [doc = "System clock switch\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Sw { # [doc = "0: HSI selected as system clock"] Hsi = 0 , # [doc = "1: HSE selected as system clock"] Hse = 1 , # [doc = "2: PLL selected as system clock"] Pll = 2 , } impl From < Sw > for u8 { # [inline (always)] fn from (variant : Sw) -> Self { variant as _ } } impl crate :: FieldSpec for Sw { type Ux = u8 ; } impl crate :: IsEnum for Sw { } # [doc = "Field `SW` reader - System clock switch"] pub type SwR = crate :: FieldReader < Sw > ; impl SwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Sw > { match self . bits { 0 => Some (Sw :: Hsi) , 1 => Some (Sw :: Hse) , 2 => Some (Sw :: Pll) , _ => None , } } # [doc = "HSI selected as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Sw :: Hsi } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Sw :: Hse } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Sw :: Pll } } # [doc = "Field `SW` writer - System clock switch"] pub type SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Sw > ; impl < 'a , REG > SwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI selected as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hsi) } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hse) } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Pll) } } # [doc = "System clock switch status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Swsr { # [doc = "0: HSI oscillator used as system clock"] Hsi = 0 , # [doc = "1: HSE oscillator used as system clock"] Hse = 1 , # [doc = "2: PLL used as system clock"] Pll = 2 , } impl From < Swsr > for u8 { # [inline (always)] fn from (variant : Swsr) -> Self { variant as _ } } impl crate :: FieldSpec for Swsr { type Ux = u8 ; } impl crate :: IsEnum for Swsr { } # [doc = "Field `SWS` reader - System clock switch status"] pub type SwsR = crate :: FieldReader < Swsr > ; impl SwsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Swsr > { match self . bits { 0 => Some (Swsr :: Hsi) , 1 => Some (Swsr :: Hse) , 2 => Some (Swsr :: Pll) , _ => None , } } # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Swsr :: Hsi } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Swsr :: Hse } # [doc = "PLL used as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Swsr :: Pll } } # [doc = "Field `SWS` writer - System clock switch status"] pub type SwsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Swsr > ; impl < 'a , REG > SwsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hsi) } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hse) } # [doc = "PLL used as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Pll) } } # [doc = "AHB prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Hpre { # [doc = "8: SYSCLK divided by 2"] Div2 = 8 , # [doc = "9: SYSCLK divided by 4"] Div4 = 9 , # [doc = "10: SYSCLK divided by 8"] Div8 = 10 , # [doc = "11: SYSCLK divided by 16"] Div16 = 11 , # [doc = "12: SYSCLK divided by 64"] Div64 = 12 , # [doc = "13: SYSCLK divided by 128"] Div128 = 13 , # [doc = "14: SYSCLK divided by 256"] Div256 = 14 , # [doc = "15: SYSCLK divided by 512"] Div512 = 15 , # [doc = "0: SYSCLK not divided"] Div1 = 0 , } impl From < Hpre > for u8 { # [inline (always)] fn from (variant : Hpre) -> Self { variant as _ } } impl crate :: FieldSpec for Hpre { type Ux = u8 ; } impl crate :: IsEnum for Hpre { } # [doc = "Field `HPRE` reader - AHB prescaler"] pub type HpreR = crate :: FieldReader < Hpre > ; impl HpreR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hpre { match self . bits { 8 => Hpre :: Div2 , 9 => Hpre :: Div4 , 10 => Hpre :: Div8 , 11 => Hpre :: Div16 , 12 => Hpre :: Div64 , 13 => Hpre :: Div128 , 14 => Hpre :: Div256 , 15 => Hpre :: Div512 , _ => Hpre :: Div1 , } } # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Hpre :: Div2 } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Hpre :: Div4 } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Hpre :: Div8 } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Hpre :: Div16 } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn is_div64 (& self) -> bool { * self == Hpre :: Div64 } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn is_div128 (& self) -> bool { * self == Hpre :: Div128 } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn is_div256 (& self) -> bool { * self == Hpre :: Div256 } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn is_div512 (& self) -> bool { * self == Hpre :: Div512 } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Hpre :: Div1) } } # [doc = "Field `HPRE` writer - AHB prescaler"] pub type HpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , Hpre , crate :: Safe > ; impl < 'a , REG > HpreW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div2) } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div4) } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div8) } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div16) } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn div64 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div64) } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn div128 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div128) } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn div256 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div256) } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn div512 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div512) } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div1) } } # [doc = "APB Low speed prescaler (APB1)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Ppre1 { # [doc = "4: HCLK divided by 2"] Div2 = 4 , # [doc = "5: HCLK divided by 4"] Div4 = 5 , # [doc = "6: HCLK divided by 8"] Div8 = 6 , # [doc = "7: HCLK divided by 16"] Div16 = 7 , # [doc = "0: HCLK not divided"] Div1 = 0 , } impl From < Ppre1 > for u8 { # [inline (always)] fn from (variant : Ppre1) -> Self { variant as _ } } impl crate :: FieldSpec for Ppre1 { type Ux = u8 ; } impl crate :: IsEnum for Ppre1 { } # [doc = "Field `PPRE1` reader - APB Low speed prescaler (APB1)"] pub type Ppre1R = crate :: FieldReader < Ppre1 > ; impl Ppre1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ppre1 { match self . bits { 4 => Ppre1 :: Div2 , 5 => Ppre1 :: Div4 , 6 => Ppre1 :: Div8 , 7 => Ppre1 :: Div16 , _ => Ppre1 :: Div1 , } } # [doc = "HCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Ppre1 :: Div2 } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Ppre1 :: Div4 } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Ppre1 :: Div8 } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Ppre1 :: Div16 } # [doc = "HCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Ppre1 :: Div1) } } # [doc = "Field `PPRE1` writer - APB Low speed prescaler (APB1)"] pub type Ppre1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Ppre1 , crate :: Safe > ; impl < 'a , REG > Ppre1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div2) } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div4) } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div8) } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div16) } # [doc = "HCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div1) } } # [doc = "Field `PPRE2` reader - APB high-speed prescaler (APB2)"] pub use Ppre1R as Ppre2R ; # [doc = "Field `PPRE2` writer - APB high-speed prescaler (APB2)"] pub use Ppre1W as Ppre2W ; # [doc = "Field `RTCPRE` reader - HSE division factor for RTC clock"] pub type RtcpreR = crate :: FieldReader ; # [doc = "Field `RTCPRE` writer - HSE division factor for RTC clock"] pub type RtcpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Microcontroller clock output 1\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1 { # [doc = "0: HSI clock selected"] Hsi = 0 , # [doc = "1: LSE oscillator selected"] Lse = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco1 > for u8 { # [inline (always)] fn from (variant : Mco1) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1 { type Ux = u8 ; } impl crate :: IsEnum for Mco1 { } # [doc = "Field `MCO1` reader - Microcontroller clock output 1"] pub type Mco1R = crate :: FieldReader < Mco1 > ; impl Mco1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1 { match self . bits { 0 => Mco1 :: Hsi , 1 => Mco1 :: Lse , 2 => Mco1 :: Hse , 3 => Mco1 :: Pll , _ => unreachable ! () , } } # [doc = "HSI clock selected"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Mco1 :: Hsi } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn is_lse (& self) -> bool { * self == Mco1 :: Lse } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco1 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco1 :: Pll } } # [doc = "Field `MCO1` writer - Microcontroller clock output 1"] pub type Mco1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco1 , crate :: Safe > ; impl < 'a , REG > Mco1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI clock selected"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hsi) } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn lse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Lse) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Pll) } } # [doc = "I2S clock selection\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum I2ssrc { # [doc = "0: PLLI2S clock used as I2S clock source"] Plli2s = 0 , # [doc = "1: External clock mapped on the I2S_CKIN pin used as I2S clock source"] Ckin = 1 , } impl From < I2ssrc > for bool { # [inline (always)] fn from (variant : I2ssrc) -> Self { variant as u8 != 0 } } # [doc = "Field `I2SSRC` reader - I2S clock selection"] pub type I2ssrcR = crate :: BitReader < I2ssrc > ; impl I2ssrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> I2ssrc { match self . bits { false => I2ssrc :: Plli2s , true => I2ssrc :: Ckin , } } # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == I2ssrc :: Plli2s } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn is_ckin (& self) -> bool { * self == I2ssrc :: Ckin } } # [doc = "Field `I2SSRC` writer - I2S clock selection"] pub type I2ssrcW < 'a , REG > = crate :: BitWriter < 'a , REG , I2ssrc > ; impl < 'a , REG > I2ssrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Plli2s) } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn ckin (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Ckin) } } # [doc = "MCO1 prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1pre { # [doc = "4: Division by 2"] Div2 = 4 , # [doc = "5: Division by 3"] Div3 = 5 , # [doc = "6: Division by 4"] Div4 = 6 , # [doc = "7: Division by 5"] Div5 = 7 , # [doc = "0: No division"] Div1 = 0 , } impl From < Mco1pre > for u8 { # [inline (always)] fn from (variant : Mco1pre) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1pre { type Ux = u8 ; } impl crate :: IsEnum for Mco1pre { } # [doc = "Field `MCO1PRE` reader - MCO1 prescaler"] pub type Mco1preR = crate :: FieldReader < Mco1pre > ; impl Mco1preR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1pre { match self . bits { 4 => Mco1pre :: Div2 , 5 => Mco1pre :: Div3 , 6 => Mco1pre :: Div4 , 7 => Mco1pre :: Div5 , _ => Mco1pre :: Div1 , } } # [doc = "Division by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Mco1pre :: Div2 } # [doc = "Division by 3"] # [inline (always)] pub fn is_div3 (& self) -> bool { * self == Mco1pre :: Div3 } # [doc = "Division by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Mco1pre :: Div4 } # [doc = "Division by 5"] # [inline (always)] pub fn is_div5 (& self) -> bool { * self == Mco1pre :: Div5 } # [doc = "No division"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Mco1pre :: Div1) } } # [doc = "Field `MCO1PRE` writer - MCO1 prescaler"] pub type Mco1preW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Mco1pre , crate :: Safe > ; impl < 'a , REG > Mco1preW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Division by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div2) } # [doc = "Division by 3"] # [inline (always)] pub fn div3 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div3) } # [doc = "Division by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div4) } # [doc = "Division by 5"] # [inline (always)] pub fn div5 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div5) } # [doc = "No division"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div1) } } # [doc = "Field `MCO2PRE` reader - MCO2 prescaler"] pub use Mco1preR as Mco2preR ; # [doc = "Field `MCO2PRE` writer - MCO2 prescaler"] pub use Mco1preW as Mco2preW ; # [doc = "Microcontroller clock output 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco2 { # [doc = "0: System clock (SYSCLK) selected"] Sysclk = 0 , # [doc = "1: PLLI2S clock selected"] Plli2s = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco2 > for u8 { # [inline (always)] fn from (variant : Mco2) -> Self { variant as _ } } impl crate :: FieldSpec for Mco2 { type Ux = u8 ; } impl crate :: IsEnum for Mco2 { } # [doc = "Field `MCO2` reader - Microcontroller clock output 2"] pub type Mco2R = crate :: FieldReader < Mco2 > ; impl Mco2R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco2 { match self . bits { 0 => Mco2 :: Sysclk , 1 => Mco2 :: Plli2s , 2 => Mco2 :: Hse , 3 => Mco2 :: Pll , _ => unreachable ! () , } } # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn is_sysclk (& self) -> bool { * self == Mco2 :: Sysclk } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == Mco2 :: Plli2s } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco2 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco2 :: Pll } } # [doc = "Field `MCO2` writer - Microcontroller clock output 2"] pub type Mco2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco2 , crate :: Safe > ; impl < 'a , REG > Mco2W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn sysclk (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Sysclk) } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Plli2s) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Pll) } } impl R { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& self) -> SwR { SwR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& self) -> SwsR { SwsR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& self) -> HpreR { HpreR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& self) -> Ppre1R { Ppre1R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& self) -> Ppre2R { Ppre2R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& self) -> RtcpreR { RtcpreR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& self) -> Mco1R { Mco1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& self) -> I2ssrcR { I2ssrcR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& self) -> Mco1preR { Mco1preR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& self) -> Mco2preR { Mco2preR :: new (((self . bits >> 27) & 7) as u8) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& self) -> Mco2R { Mco2R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& mut self) -> SwW < CfgrSpec > { SwW :: new (self , 0) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& mut self) -> SwsW < CfgrSpec > { SwsW :: new (self , 2) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& mut self) -> HpreW <'_, CfgrSpec > { HpreW :: new (self , 4) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& mut self) -> Ppre1W < CfgrSpec > { Ppre1W :: new (self , 10) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& mut self) -> Ppre2W < CfgrSpec > { Ppre2W :: new (self , 13) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& mut self) -> RtcpreW < CfgrSpec > { RtcpreW :: new (self , 16) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& mut self) -> Mco1W < CfgrSpec > { Mco1W :: new (self , 21) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& mut self) -> I2ssrcW < CfgrSpec > { I2ssrcW :: new (self , 23) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& mut self) -> Mco1preW < CfgrSpec > { Mco1preW :: new (self , 24) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& mut self) -> Mco2preW < CfgrSpec > { Mco2preW :: new (self , 27) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& mut self) -> Mco2W < CfgrSpec > { Mco2W :: new (self , 30) } } # [doc = "clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgrSpec ; impl crate :: RegisterSpec for CfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr::R`](R) reader structure"] impl crate :: Readable for CfgrSpec { } # [doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"] impl crate :: Writable for CfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CFGR to value 0"] impl crate :: Resettable for CfgrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4691 [INFO] [stdout] | [INFO] [stdout] 1 | ..."] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] ... [INFO] [stdout] | ^^^^^^^^^^ --------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW <'_, CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4825 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchro... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW <'_, CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:4979 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchroniza... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW <'_, CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:5129 [INFO] [stdout] | [INFO] [stdout] 1 | ...# [inline (always)] pub fn vspol (& mut self) -> VspolW < CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rat... [INFO] [stdout] | ^^^^^^^^^^ ----------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CR` reader"] pub type R = crate :: R < CrSpec > ; # [doc = "Register `CR` writer"] pub type W = crate :: W < CrSpec > ; # [doc = "Field `CAPTURE` reader - Capture enable"] pub type CaptureR = crate :: BitReader ; # [doc = "Field `CAPTURE` writer - Capture enable"] pub type CaptureW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM` reader - Capture mode"] pub type CmR = crate :: BitReader ; # [doc = "Field `CM` writer - Capture mode"] pub type CmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CROP` reader - Crop feature"] pub type CropR = crate :: BitReader ; # [doc = "Field `CROP` writer - Crop feature"] pub type CropW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JPEG` reader - JPEG format"] pub type JpegR = crate :: BitReader ; # [doc = "Field `JPEG` writer - JPEG format"] pub type JpegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESS` reader - Embedded synchronization select"] pub type EssR = crate :: BitReader ; # [doc = "Field `ESS` writer - Embedded synchronization select"] pub type EssW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCKPOL` reader - Pixel clock polarity"] pub type PckpolR = crate :: BitReader ; # [doc = "Field `PCKPOL` writer - Pixel clock polarity"] pub type PckpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSPOL` reader - Horizontal synchronization polarity"] pub type HspolR = crate :: BitReader ; # [doc = "Field `HSPOL` writer - Horizontal synchronization polarity"] pub type HspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VSPOL` reader - Vertical synchronization polarity"] pub type VspolR = crate :: BitReader ; # [doc = "Field `VSPOL` writer - Vertical synchronization polarity"] pub type VspolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FCRC` reader - Frame capture rate control"] pub type FcrcR = crate :: FieldReader ; # [doc = "Field `FCRC` writer - Frame capture rate control"] pub type FcrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EDM` reader - Extended data mode"] pub type EdmR = crate :: FieldReader ; # [doc = "Field `EDM` writer - Extended data mode"] pub type EdmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ENABLE` reader - DCMI enable"] pub type EnableR = crate :: BitReader ; # [doc = "Field `ENABLE` writer - DCMI enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& self) -> CaptureR { CaptureR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& self) -> CmR { CmR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& self) -> CropR { CropR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& self) -> JpegR { JpegR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& self) -> EssR { EssR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& self) -> PckpolR { PckpolR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& self) -> HspolR { HspolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& self) -> VspolR { VspolR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& self) -> FcrcR { FcrcR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& self) -> EdmR { EdmR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture enable"] # [inline (always)] pub fn capture (& mut self) -> CaptureW < CrSpec > { CaptureW :: new (self , 0) } # [doc = "Bit 1 - Capture mode"] # [inline (always)] pub fn cm (& mut self) -> CmW < CrSpec > { CmW :: new (self , 1) } # [doc = "Bit 2 - Crop feature"] # [inline (always)] pub fn crop (& mut self) -> CropW < CrSpec > { CropW :: new (self , 2) } # [doc = "Bit 3 - JPEG format"] # [inline (always)] pub fn jpeg (& mut self) -> JpegW < CrSpec > { JpegW :: new (self , 3) } # [doc = "Bit 4 - Embedded synchronization select"] # [inline (always)] pub fn ess (& mut self) -> EssW < CrSpec > { EssW :: new (self , 4) } # [doc = "Bit 5 - Pixel clock polarity"] # [inline (always)] pub fn pckpol (& mut self) -> PckpolW < CrSpec > { PckpolW :: new (self , 5) } # [doc = "Bit 6 - Horizontal synchronization polarity"] # [inline (always)] pub fn hspol (& mut self) -> HspolW < CrSpec > { HspolW :: new (self , 6) } # [doc = "Bit 7 - Vertical synchronization polarity"] # [inline (always)] pub fn vspol (& mut self) -> VspolW <'_, CrSpec > { VspolW :: new (self , 7) } # [doc = "Bits 8:9 - Frame capture rate control"] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mode"] # [inline (always)] pub fn edm (& mut self) -> EdmW < CrSpec > { EdmW :: new (self , 10) } # [doc = "Bit 14 - DCMI enable"] # [inline (always)] pub fn enable (& mut self) -> EnableW < CrSpec > { EnableW :: new (self , 14) } } # [doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CrSpec ; impl crate :: RegisterSpec for CrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cr::R`](R) reader structure"] impl crate :: Readable for CrSpec { } # [doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate :: Writable for CrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CR to value 0"] impl crate :: Resettable for CrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cfgr.rs:1:21233 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn ppre1 (& mut self) -> Ppre1W < CfgrSpec > { Ppre1W :: new (self , 10) } # [doc = "Bits 13:15 - APB high-spee... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGR` reader"] pub type R = crate :: R < CfgrSpec > ; # [doc = "Register `CFGR` writer"] pub type W = crate :: W < CfgrSpec > ; # [doc = "System clock switch\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Sw { # [doc = "0: HSI selected as system clock"] Hsi = 0 , # [doc = "1: HSE selected as system clock"] Hse = 1 , # [doc = "2: PLL selected as system clock"] Pll = 2 , } impl From < Sw > for u8 { # [inline (always)] fn from (variant : Sw) -> Self { variant as _ } } impl crate :: FieldSpec for Sw { type Ux = u8 ; } impl crate :: IsEnum for Sw { } # [doc = "Field `SW` reader - System clock switch"] pub type SwR = crate :: FieldReader < Sw > ; impl SwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Sw > { match self . bits { 0 => Some (Sw :: Hsi) , 1 => Some (Sw :: Hse) , 2 => Some (Sw :: Pll) , _ => None , } } # [doc = "HSI selected as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Sw :: Hsi } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Sw :: Hse } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Sw :: Pll } } # [doc = "Field `SW` writer - System clock switch"] pub type SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Sw > ; impl < 'a , REG > SwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI selected as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hsi) } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hse) } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Pll) } } # [doc = "System clock switch status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Swsr { # [doc = "0: HSI oscillator used as system clock"] Hsi = 0 , # [doc = "1: HSE oscillator used as system clock"] Hse = 1 , # [doc = "2: PLL used as system clock"] Pll = 2 , } impl From < Swsr > for u8 { # [inline (always)] fn from (variant : Swsr) -> Self { variant as _ } } impl crate :: FieldSpec for Swsr { type Ux = u8 ; } impl crate :: IsEnum for Swsr { } # [doc = "Field `SWS` reader - System clock switch status"] pub type SwsR = crate :: FieldReader < Swsr > ; impl SwsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Swsr > { match self . bits { 0 => Some (Swsr :: Hsi) , 1 => Some (Swsr :: Hse) , 2 => Some (Swsr :: Pll) , _ => None , } } # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Swsr :: Hsi } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Swsr :: Hse } # [doc = "PLL used as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Swsr :: Pll } } # [doc = "Field `SWS` writer - System clock switch status"] pub type SwsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Swsr > ; impl < 'a , REG > SwsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hsi) } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hse) } # [doc = "PLL used as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Pll) } } # [doc = "AHB prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Hpre { # [doc = "8: SYSCLK divided by 2"] Div2 = 8 , # [doc = "9: SYSCLK divided by 4"] Div4 = 9 , # [doc = "10: SYSCLK divided by 8"] Div8 = 10 , # [doc = "11: SYSCLK divided by 16"] Div16 = 11 , # [doc = "12: SYSCLK divided by 64"] Div64 = 12 , # [doc = "13: SYSCLK divided by 128"] Div128 = 13 , # [doc = "14: SYSCLK divided by 256"] Div256 = 14 , # [doc = "15: SYSCLK divided by 512"] Div512 = 15 , # [doc = "0: SYSCLK not divided"] Div1 = 0 , } impl From < Hpre > for u8 { # [inline (always)] fn from (variant : Hpre) -> Self { variant as _ } } impl crate :: FieldSpec for Hpre { type Ux = u8 ; } impl crate :: IsEnum for Hpre { } # [doc = "Field `HPRE` reader - AHB prescaler"] pub type HpreR = crate :: FieldReader < Hpre > ; impl HpreR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hpre { match self . bits { 8 => Hpre :: Div2 , 9 => Hpre :: Div4 , 10 => Hpre :: Div8 , 11 => Hpre :: Div16 , 12 => Hpre :: Div64 , 13 => Hpre :: Div128 , 14 => Hpre :: Div256 , 15 => Hpre :: Div512 , _ => Hpre :: Div1 , } } # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Hpre :: Div2 } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Hpre :: Div4 } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Hpre :: Div8 } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Hpre :: Div16 } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn is_div64 (& self) -> bool { * self == Hpre :: Div64 } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn is_div128 (& self) -> bool { * self == Hpre :: Div128 } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn is_div256 (& self) -> bool { * self == Hpre :: Div256 } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn is_div512 (& self) -> bool { * self == Hpre :: Div512 } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Hpre :: Div1) } } # [doc = "Field `HPRE` writer - AHB prescaler"] pub type HpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , Hpre , crate :: Safe > ; impl < 'a , REG > HpreW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div2) } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div4) } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div8) } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div16) } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn div64 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div64) } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn div128 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div128) } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn div256 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div256) } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn div512 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div512) } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div1) } } # [doc = "APB Low speed prescaler (APB1)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Ppre1 { # [doc = "4: HCLK divided by 2"] Div2 = 4 , # [doc = "5: HCLK divided by 4"] Div4 = 5 , # [doc = "6: HCLK divided by 8"] Div8 = 6 , # [doc = "7: HCLK divided by 16"] Div16 = 7 , # [doc = "0: HCLK not divided"] Div1 = 0 , } impl From < Ppre1 > for u8 { # [inline (always)] fn from (variant : Ppre1) -> Self { variant as _ } } impl crate :: FieldSpec for Ppre1 { type Ux = u8 ; } impl crate :: IsEnum for Ppre1 { } # [doc = "Field `PPRE1` reader - APB Low speed prescaler (APB1)"] pub type Ppre1R = crate :: FieldReader < Ppre1 > ; impl Ppre1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ppre1 { match self . bits { 4 => Ppre1 :: Div2 , 5 => Ppre1 :: Div4 , 6 => Ppre1 :: Div8 , 7 => Ppre1 :: Div16 , _ => Ppre1 :: Div1 , } } # [doc = "HCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Ppre1 :: Div2 } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Ppre1 :: Div4 } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Ppre1 :: Div8 } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Ppre1 :: Div16 } # [doc = "HCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Ppre1 :: Div1) } } # [doc = "Field `PPRE1` writer - APB Low speed prescaler (APB1)"] pub type Ppre1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Ppre1 , crate :: Safe > ; impl < 'a , REG > Ppre1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div2) } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div4) } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div8) } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div16) } # [doc = "HCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div1) } } # [doc = "Field `PPRE2` reader - APB high-speed prescaler (APB2)"] pub use Ppre1R as Ppre2R ; # [doc = "Field `PPRE2` writer - APB high-speed prescaler (APB2)"] pub use Ppre1W as Ppre2W ; # [doc = "Field `RTCPRE` reader - HSE division factor for RTC clock"] pub type RtcpreR = crate :: FieldReader ; # [doc = "Field `RTCPRE` writer - HSE division factor for RTC clock"] pub type RtcpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Microcontroller clock output 1\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1 { # [doc = "0: HSI clock selected"] Hsi = 0 , # [doc = "1: LSE oscillator selected"] Lse = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco1 > for u8 { # [inline (always)] fn from (variant : Mco1) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1 { type Ux = u8 ; } impl crate :: IsEnum for Mco1 { } # [doc = "Field `MCO1` reader - Microcontroller clock output 1"] pub type Mco1R = crate :: FieldReader < Mco1 > ; impl Mco1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1 { match self . bits { 0 => Mco1 :: Hsi , 1 => Mco1 :: Lse , 2 => Mco1 :: Hse , 3 => Mco1 :: Pll , _ => unreachable ! () , } } # [doc = "HSI clock selected"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Mco1 :: Hsi } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn is_lse (& self) -> bool { * self == Mco1 :: Lse } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco1 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco1 :: Pll } } # [doc = "Field `MCO1` writer - Microcontroller clock output 1"] pub type Mco1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco1 , crate :: Safe > ; impl < 'a , REG > Mco1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI clock selected"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hsi) } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn lse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Lse) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Pll) } } # [doc = "I2S clock selection\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum I2ssrc { # [doc = "0: PLLI2S clock used as I2S clock source"] Plli2s = 0 , # [doc = "1: External clock mapped on the I2S_CKIN pin used as I2S clock source"] Ckin = 1 , } impl From < I2ssrc > for bool { # [inline (always)] fn from (variant : I2ssrc) -> Self { variant as u8 != 0 } } # [doc = "Field `I2SSRC` reader - I2S clock selection"] pub type I2ssrcR = crate :: BitReader < I2ssrc > ; impl I2ssrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> I2ssrc { match self . bits { false => I2ssrc :: Plli2s , true => I2ssrc :: Ckin , } } # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == I2ssrc :: Plli2s } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn is_ckin (& self) -> bool { * self == I2ssrc :: Ckin } } # [doc = "Field `I2SSRC` writer - I2S clock selection"] pub type I2ssrcW < 'a , REG > = crate :: BitWriter < 'a , REG , I2ssrc > ; impl < 'a , REG > I2ssrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Plli2s) } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn ckin (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Ckin) } } # [doc = "MCO1 prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1pre { # [doc = "4: Division by 2"] Div2 = 4 , # [doc = "5: Division by 3"] Div3 = 5 , # [doc = "6: Division by 4"] Div4 = 6 , # [doc = "7: Division by 5"] Div5 = 7 , # [doc = "0: No division"] Div1 = 0 , } impl From < Mco1pre > for u8 { # [inline (always)] fn from (variant : Mco1pre) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1pre { type Ux = u8 ; } impl crate :: IsEnum for Mco1pre { } # [doc = "Field `MCO1PRE` reader - MCO1 prescaler"] pub type Mco1preR = crate :: FieldReader < Mco1pre > ; impl Mco1preR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1pre { match self . bits { 4 => Mco1pre :: Div2 , 5 => Mco1pre :: Div3 , 6 => Mco1pre :: Div4 , 7 => Mco1pre :: Div5 , _ => Mco1pre :: Div1 , } } # [doc = "Division by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Mco1pre :: Div2 } # [doc = "Division by 3"] # [inline (always)] pub fn is_div3 (& self) -> bool { * self == Mco1pre :: Div3 } # [doc = "Division by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Mco1pre :: Div4 } # [doc = "Division by 5"] # [inline (always)] pub fn is_div5 (& self) -> bool { * self == Mco1pre :: Div5 } # [doc = "No division"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Mco1pre :: Div1) } } # [doc = "Field `MCO1PRE` writer - MCO1 prescaler"] pub type Mco1preW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Mco1pre , crate :: Safe > ; impl < 'a , REG > Mco1preW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Division by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div2) } # [doc = "Division by 3"] # [inline (always)] pub fn div3 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div3) } # [doc = "Division by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div4) } # [doc = "Division by 5"] # [inline (always)] pub fn div5 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div5) } # [doc = "No division"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div1) } } # [doc = "Field `MCO2PRE` reader - MCO2 prescaler"] pub use Mco1preR as Mco2preR ; # [doc = "Field `MCO2PRE` writer - MCO2 prescaler"] pub use Mco1preW as Mco2preW ; # [doc = "Microcontroller clock output 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco2 { # [doc = "0: System clock (SYSCLK) selected"] Sysclk = 0 , # [doc = "1: PLLI2S clock selected"] Plli2s = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco2 > for u8 { # [inline (always)] fn from (variant : Mco2) -> Self { variant as _ } } impl crate :: FieldSpec for Mco2 { type Ux = u8 ; } impl crate :: IsEnum for Mco2 { } # [doc = "Field `MCO2` reader - Microcontroller clock output 2"] pub type Mco2R = crate :: FieldReader < Mco2 > ; impl Mco2R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco2 { match self . bits { 0 => Mco2 :: Sysclk , 1 => Mco2 :: Plli2s , 2 => Mco2 :: Hse , 3 => Mco2 :: Pll , _ => unreachable ! () , } } # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn is_sysclk (& self) -> bool { * self == Mco2 :: Sysclk } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == Mco2 :: Plli2s } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco2 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco2 :: Pll } } # [doc = "Field `MCO2` writer - Microcontroller clock output 2"] pub type Mco2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco2 , crate :: Safe > ; impl < 'a , REG > Mco2W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn sysclk (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Sysclk) } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Plli2s) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Pll) } } impl R { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& self) -> SwR { SwR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& self) -> SwsR { SwsR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& self) -> HpreR { HpreR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& self) -> Ppre1R { Ppre1R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& self) -> Ppre2R { Ppre2R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& self) -> RtcpreR { RtcpreR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& self) -> Mco1R { Mco1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& self) -> I2ssrcR { I2ssrcR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& self) -> Mco1preR { Mco1preR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& self) -> Mco2preR { Mco2preR :: new (((self . bits >> 27) & 7) as u8) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& self) -> Mco2R { Mco2R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& mut self) -> SwW < CfgrSpec > { SwW :: new (self , 0) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& mut self) -> SwsW < CfgrSpec > { SwsW :: new (self , 2) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& mut self) -> HpreW < CfgrSpec > { HpreW :: new (self , 4) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& mut self) -> Ppre1W <'_, CfgrSpec > { Ppre1W :: new (self , 10) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& mut self) -> Ppre2W < CfgrSpec > { Ppre2W :: new (self , 13) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& mut self) -> RtcpreW < CfgrSpec > { RtcpreW :: new (self , 16) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& mut self) -> Mco1W < CfgrSpec > { Mco1W :: new (self , 21) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& mut self) -> I2ssrcW < CfgrSpec > { I2ssrcW :: new (self , 23) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& mut self) -> Mco1preW < CfgrSpec > { Mco1preW :: new (self , 24) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& mut self) -> Mco2preW < CfgrSpec > { Mco2preW :: new (self , 27) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& mut self) -> Mco2W < CfgrSpec > { Mco2W :: new (self , 30) } } # [doc = "clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgrSpec ; impl crate :: RegisterSpec for CfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr::R`](R) reader structure"] impl crate :: Readable for CfgrSpec { } # [doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"] impl crate :: Writable for CfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CFGR to value 0"] impl crate :: Resettable for CfgrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cfgr.rs:1:21389 [INFO] [stdout] | [INFO] [stdout] 1 | ... [inline (always)] pub fn ppre2 (& mut self) -> Ppre2W < CfgrSpec > { Ppre2W :: new (self , 13) } # [doc = "Bits 16:20 - HSE division ... [INFO] [stdout] | ^^^^^^^^^^ ------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGR` reader"] pub type R = crate :: R < CfgrSpec > ; # [doc = "Register `CFGR` writer"] pub type W = crate :: W < CfgrSpec > ; # [doc = "System clock switch\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Sw { # [doc = "0: HSI selected as system clock"] Hsi = 0 , # [doc = "1: HSE selected as system clock"] Hse = 1 , # [doc = "2: PLL selected as system clock"] Pll = 2 , } impl From < Sw > for u8 { # [inline (always)] fn from (variant : Sw) -> Self { variant as _ } } impl crate :: FieldSpec for Sw { type Ux = u8 ; } impl crate :: IsEnum for Sw { } # [doc = "Field `SW` reader - System clock switch"] pub type SwR = crate :: FieldReader < Sw > ; impl SwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Sw > { match self . bits { 0 => Some (Sw :: Hsi) , 1 => Some (Sw :: Hse) , 2 => Some (Sw :: Pll) , _ => None , } } # [doc = "HSI selected as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Sw :: Hsi } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Sw :: Hse } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Sw :: Pll } } # [doc = "Field `SW` writer - System clock switch"] pub type SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Sw > ; impl < 'a , REG > SwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI selected as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hsi) } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hse) } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Pll) } } # [doc = "System clock switch status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Swsr { # [doc = "0: HSI oscillator used as system clock"] Hsi = 0 , # [doc = "1: HSE oscillator used as system clock"] Hse = 1 , # [doc = "2: PLL used as system clock"] Pll = 2 , } impl From < Swsr > for u8 { # [inline (always)] fn from (variant : Swsr) -> Self { variant as _ } } impl crate :: FieldSpec for Swsr { type Ux = u8 ; } impl crate :: IsEnum for Swsr { } # [doc = "Field `SWS` reader - System clock switch status"] pub type SwsR = crate :: FieldReader < Swsr > ; impl SwsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Swsr > { match self . bits { 0 => Some (Swsr :: Hsi) , 1 => Some (Swsr :: Hse) , 2 => Some (Swsr :: Pll) , _ => None , } } # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Swsr :: Hsi } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Swsr :: Hse } # [doc = "PLL used as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Swsr :: Pll } } # [doc = "Field `SWS` writer - System clock switch status"] pub type SwsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Swsr > ; impl < 'a , REG > SwsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hsi) } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hse) } # [doc = "PLL used as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Pll) } } # [doc = "AHB prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Hpre { # [doc = "8: SYSCLK divided by 2"] Div2 = 8 , # [doc = "9: SYSCLK divided by 4"] Div4 = 9 , # [doc = "10: SYSCLK divided by 8"] Div8 = 10 , # [doc = "11: SYSCLK divided by 16"] Div16 = 11 , # [doc = "12: SYSCLK divided by 64"] Div64 = 12 , # [doc = "13: SYSCLK divided by 128"] Div128 = 13 , # [doc = "14: SYSCLK divided by 256"] Div256 = 14 , # [doc = "15: SYSCLK divided by 512"] Div512 = 15 , # [doc = "0: SYSCLK not divided"] Div1 = 0 , } impl From < Hpre > for u8 { # [inline (always)] fn from (variant : Hpre) -> Self { variant as _ } } impl crate :: FieldSpec for Hpre { type Ux = u8 ; } impl crate :: IsEnum for Hpre { } # [doc = "Field `HPRE` reader - AHB prescaler"] pub type HpreR = crate :: FieldReader < Hpre > ; impl HpreR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hpre { match self . bits { 8 => Hpre :: Div2 , 9 => Hpre :: Div4 , 10 => Hpre :: Div8 , 11 => Hpre :: Div16 , 12 => Hpre :: Div64 , 13 => Hpre :: Div128 , 14 => Hpre :: Div256 , 15 => Hpre :: Div512 , _ => Hpre :: Div1 , } } # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Hpre :: Div2 } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Hpre :: Div4 } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Hpre :: Div8 } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Hpre :: Div16 } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn is_div64 (& self) -> bool { * self == Hpre :: Div64 } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn is_div128 (& self) -> bool { * self == Hpre :: Div128 } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn is_div256 (& self) -> bool { * self == Hpre :: Div256 } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn is_div512 (& self) -> bool { * self == Hpre :: Div512 } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Hpre :: Div1) } } # [doc = "Field `HPRE` writer - AHB prescaler"] pub type HpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , Hpre , crate :: Safe > ; impl < 'a , REG > HpreW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div2) } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div4) } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div8) } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div16) } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn div64 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div64) } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn div128 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div128) } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn div256 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div256) } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn div512 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div512) } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div1) } } # [doc = "APB Low speed prescaler (APB1)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Ppre1 { # [doc = "4: HCLK divided by 2"] Div2 = 4 , # [doc = "5: HCLK divided by 4"] Div4 = 5 , # [doc = "6: HCLK divided by 8"] Div8 = 6 , # [doc = "7: HCLK divided by 16"] Div16 = 7 , # [doc = "0: HCLK not divided"] Div1 = 0 , } impl From < Ppre1 > for u8 { # [inline (always)] fn from (variant : Ppre1) -> Self { variant as _ } } impl crate :: FieldSpec for Ppre1 { type Ux = u8 ; } impl crate :: IsEnum for Ppre1 { } # [doc = "Field `PPRE1` reader - APB Low speed prescaler (APB1)"] pub type Ppre1R = crate :: FieldReader < Ppre1 > ; impl Ppre1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ppre1 { match self . bits { 4 => Ppre1 :: Div2 , 5 => Ppre1 :: Div4 , 6 => Ppre1 :: Div8 , 7 => Ppre1 :: Div16 , _ => Ppre1 :: Div1 , } } # [doc = "HCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Ppre1 :: Div2 } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Ppre1 :: Div4 } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Ppre1 :: Div8 } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Ppre1 :: Div16 } # [doc = "HCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Ppre1 :: Div1) } } # [doc = "Field `PPRE1` writer - APB Low speed prescaler (APB1)"] pub type Ppre1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Ppre1 , crate :: Safe > ; impl < 'a , REG > Ppre1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div2) } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div4) } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div8) } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div16) } # [doc = "HCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div1) } } # [doc = "Field `PPRE2` reader - APB high-speed prescaler (APB2)"] pub use Ppre1R as Ppre2R ; # [doc = "Field `PPRE2` writer - APB high-speed prescaler (APB2)"] pub use Ppre1W as Ppre2W ; # [doc = "Field `RTCPRE` reader - HSE division factor for RTC clock"] pub type RtcpreR = crate :: FieldReader ; # [doc = "Field `RTCPRE` writer - HSE division factor for RTC clock"] pub type RtcpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Microcontroller clock output 1\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1 { # [doc = "0: HSI clock selected"] Hsi = 0 , # [doc = "1: LSE oscillator selected"] Lse = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco1 > for u8 { # [inline (always)] fn from (variant : Mco1) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1 { type Ux = u8 ; } impl crate :: IsEnum for Mco1 { } # [doc = "Field `MCO1` reader - Microcontroller clock output 1"] pub type Mco1R = crate :: FieldReader < Mco1 > ; impl Mco1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1 { match self . bits { 0 => Mco1 :: Hsi , 1 => Mco1 :: Lse , 2 => Mco1 :: Hse , 3 => Mco1 :: Pll , _ => unreachable ! () , } } # [doc = "HSI clock selected"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Mco1 :: Hsi } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn is_lse (& self) -> bool { * self == Mco1 :: Lse } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco1 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco1 :: Pll } } # [doc = "Field `MCO1` writer - Microcontroller clock output 1"] pub type Mco1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco1 , crate :: Safe > ; impl < 'a , REG > Mco1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI clock selected"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hsi) } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn lse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Lse) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Pll) } } # [doc = "I2S clock selection\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum I2ssrc { # [doc = "0: PLLI2S clock used as I2S clock source"] Plli2s = 0 , # [doc = "1: External clock mapped on the I2S_CKIN pin used as I2S clock source"] Ckin = 1 , } impl From < I2ssrc > for bool { # [inline (always)] fn from (variant : I2ssrc) -> Self { variant as u8 != 0 } } # [doc = "Field `I2SSRC` reader - I2S clock selection"] pub type I2ssrcR = crate :: BitReader < I2ssrc > ; impl I2ssrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> I2ssrc { match self . bits { false => I2ssrc :: Plli2s , true => I2ssrc :: Ckin , } } # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == I2ssrc :: Plli2s } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn is_ckin (& self) -> bool { * self == I2ssrc :: Ckin } } # [doc = "Field `I2SSRC` writer - I2S clock selection"] pub type I2ssrcW < 'a , REG > = crate :: BitWriter < 'a , REG , I2ssrc > ; impl < 'a , REG > I2ssrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Plli2s) } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn ckin (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Ckin) } } # [doc = "MCO1 prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1pre { # [doc = "4: Division by 2"] Div2 = 4 , # [doc = "5: Division by 3"] Div3 = 5 , # [doc = "6: Division by 4"] Div4 = 6 , # [doc = "7: Division by 5"] Div5 = 7 , # [doc = "0: No division"] Div1 = 0 , } impl From < Mco1pre > for u8 { # [inline (always)] fn from (variant : Mco1pre) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1pre { type Ux = u8 ; } impl crate :: IsEnum for Mco1pre { } # [doc = "Field `MCO1PRE` reader - MCO1 prescaler"] pub type Mco1preR = crate :: FieldReader < Mco1pre > ; impl Mco1preR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1pre { match self . bits { 4 => Mco1pre :: Div2 , 5 => Mco1pre :: Div3 , 6 => Mco1pre :: Div4 , 7 => Mco1pre :: Div5 , _ => Mco1pre :: Div1 , } } # [doc = "Division by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Mco1pre :: Div2 } # [doc = "Division by 3"] # [inline (always)] pub fn is_div3 (& self) -> bool { * self == Mco1pre :: Div3 } # [doc = "Division by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Mco1pre :: Div4 } # [doc = "Division by 5"] # [inline (always)] pub fn is_div5 (& self) -> bool { * self == Mco1pre :: Div5 } # [doc = "No division"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Mco1pre :: Div1) } } # [doc = "Field `MCO1PRE` writer - MCO1 prescaler"] pub type Mco1preW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Mco1pre , crate :: Safe > ; impl < 'a , REG > Mco1preW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Division by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div2) } # [doc = "Division by 3"] # [inline (always)] pub fn div3 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div3) } # [doc = "Division by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div4) } # [doc = "Division by 5"] # [inline (always)] pub fn div5 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div5) } # [doc = "No division"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div1) } } # [doc = "Field `MCO2PRE` reader - MCO2 prescaler"] pub use Mco1preR as Mco2preR ; # [doc = "Field `MCO2PRE` writer - MCO2 prescaler"] pub use Mco1preW as Mco2preW ; # [doc = "Microcontroller clock output 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco2 { # [doc = "0: System clock (SYSCLK) selected"] Sysclk = 0 , # [doc = "1: PLLI2S clock selected"] Plli2s = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco2 > for u8 { # [inline (always)] fn from (variant : Mco2) -> Self { variant as _ } } impl crate :: FieldSpec for Mco2 { type Ux = u8 ; } impl crate :: IsEnum for Mco2 { } # [doc = "Field `MCO2` reader - Microcontroller clock output 2"] pub type Mco2R = crate :: FieldReader < Mco2 > ; impl Mco2R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco2 { match self . bits { 0 => Mco2 :: Sysclk , 1 => Mco2 :: Plli2s , 2 => Mco2 :: Hse , 3 => Mco2 :: Pll , _ => unreachable ! () , } } # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn is_sysclk (& self) -> bool { * self == Mco2 :: Sysclk } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == Mco2 :: Plli2s } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco2 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco2 :: Pll } } # [doc = "Field `MCO2` writer - Microcontroller clock output 2"] pub type Mco2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco2 , crate :: Safe > ; impl < 'a , REG > Mco2W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn sysclk (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Sysclk) } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Plli2s) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Pll) } } impl R { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& self) -> SwR { SwR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& self) -> SwsR { SwsR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& self) -> HpreR { HpreR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& self) -> Ppre1R { Ppre1R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& self) -> Ppre2R { Ppre2R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& self) -> RtcpreR { RtcpreR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& self) -> Mco1R { Mco1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& self) -> I2ssrcR { I2ssrcR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& self) -> Mco1preR { Mco1preR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& self) -> Mco2preR { Mco2preR :: new (((self . bits >> 27) & 7) as u8) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& self) -> Mco2R { Mco2R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& mut self) -> SwW < CfgrSpec > { SwW :: new (self , 0) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& mut self) -> SwsW < CfgrSpec > { SwsW :: new (self , 2) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& mut self) -> HpreW < CfgrSpec > { HpreW :: new (self , 4) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& mut self) -> Ppre1W < CfgrSpec > { Ppre1W :: new (self , 10) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& mut self) -> Ppre2W <'_, CfgrSpec > { Ppre2W :: new (self , 13) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& mut self) -> RtcpreW < CfgrSpec > { RtcpreW :: new (self , 16) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& mut self) -> Mco1W < CfgrSpec > { Mco1W :: new (self , 21) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& mut self) -> I2ssrcW < CfgrSpec > { I2ssrcW :: new (self , 23) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& mut self) -> Mco1preW < CfgrSpec > { Mco1preW :: new (self , 24) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& mut self) -> Mco2preW < CfgrSpec > { Mco2preW :: new (self , 27) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& mut self) -> Mco2W < CfgrSpec > { Mco2W :: new (self , 30) } } # [doc = "clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgrSpec ; impl crate :: RegisterSpec for CfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr::R`](R) reader structure"] impl crate :: Readable for CfgrSpec { } # [doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"] impl crate :: Writable for CfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CFGR to value 0"] impl crate :: Resettable for CfgrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cfgr.rs:1:21548 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn rtcpre (& mut self) -> RtcpreW < CfgrSpec > { RtcpreW :: new (self , 16) } # [doc = "Bits 21:22 - Microcontro... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGR` reader"] pub type R = crate :: R < CfgrSpec > ; # [doc = "Register `CFGR` writer"] pub type W = crate :: W < CfgrSpec > ; # [doc = "System clock switch\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Sw { # [doc = "0: HSI selected as system clock"] Hsi = 0 , # [doc = "1: HSE selected as system clock"] Hse = 1 , # [doc = "2: PLL selected as system clock"] Pll = 2 , } impl From < Sw > for u8 { # [inline (always)] fn from (variant : Sw) -> Self { variant as _ } } impl crate :: FieldSpec for Sw { type Ux = u8 ; } impl crate :: IsEnum for Sw { } # [doc = "Field `SW` reader - System clock switch"] pub type SwR = crate :: FieldReader < Sw > ; impl SwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Sw > { match self . bits { 0 => Some (Sw :: Hsi) , 1 => Some (Sw :: Hse) , 2 => Some (Sw :: Pll) , _ => None , } } # [doc = "HSI selected as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Sw :: Hsi } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Sw :: Hse } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Sw :: Pll } } # [doc = "Field `SW` writer - System clock switch"] pub type SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Sw > ; impl < 'a , REG > SwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI selected as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hsi) } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hse) } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Pll) } } # [doc = "System clock switch status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Swsr { # [doc = "0: HSI oscillator used as system clock"] Hsi = 0 , # [doc = "1: HSE oscillator used as system clock"] Hse = 1 , # [doc = "2: PLL used as system clock"] Pll = 2 , } impl From < Swsr > for u8 { # [inline (always)] fn from (variant : Swsr) -> Self { variant as _ } } impl crate :: FieldSpec for Swsr { type Ux = u8 ; } impl crate :: IsEnum for Swsr { } # [doc = "Field `SWS` reader - System clock switch status"] pub type SwsR = crate :: FieldReader < Swsr > ; impl SwsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Swsr > { match self . bits { 0 => Some (Swsr :: Hsi) , 1 => Some (Swsr :: Hse) , 2 => Some (Swsr :: Pll) , _ => None , } } # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Swsr :: Hsi } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Swsr :: Hse } # [doc = "PLL used as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Swsr :: Pll } } # [doc = "Field `SWS` writer - System clock switch status"] pub type SwsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Swsr > ; impl < 'a , REG > SwsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hsi) } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hse) } # [doc = "PLL used as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Pll) } } # [doc = "AHB prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Hpre { # [doc = "8: SYSCLK divided by 2"] Div2 = 8 , # [doc = "9: SYSCLK divided by 4"] Div4 = 9 , # [doc = "10: SYSCLK divided by 8"] Div8 = 10 , # [doc = "11: SYSCLK divided by 16"] Div16 = 11 , # [doc = "12: SYSCLK divided by 64"] Div64 = 12 , # [doc = "13: SYSCLK divided by 128"] Div128 = 13 , # [doc = "14: SYSCLK divided by 256"] Div256 = 14 , # [doc = "15: SYSCLK divided by 512"] Div512 = 15 , # [doc = "0: SYSCLK not divided"] Div1 = 0 , } impl From < Hpre > for u8 { # [inline (always)] fn from (variant : Hpre) -> Self { variant as _ } } impl crate :: FieldSpec for Hpre { type Ux = u8 ; } impl crate :: IsEnum for Hpre { } # [doc = "Field `HPRE` reader - AHB prescaler"] pub type HpreR = crate :: FieldReader < Hpre > ; impl HpreR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hpre { match self . bits { 8 => Hpre :: Div2 , 9 => Hpre :: Div4 , 10 => Hpre :: Div8 , 11 => Hpre :: Div16 , 12 => Hpre :: Div64 , 13 => Hpre :: Div128 , 14 => Hpre :: Div256 , 15 => Hpre :: Div512 , _ => Hpre :: Div1 , } } # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Hpre :: Div2 } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Hpre :: Div4 } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Hpre :: Div8 } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Hpre :: Div16 } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn is_div64 (& self) -> bool { * self == Hpre :: Div64 } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn is_div128 (& self) -> bool { * self == Hpre :: Div128 } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn is_div256 (& self) -> bool { * self == Hpre :: Div256 } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn is_div512 (& self) -> bool { * self == Hpre :: Div512 } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Hpre :: Div1) } } # [doc = "Field `HPRE` writer - AHB prescaler"] pub type HpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , Hpre , crate :: Safe > ; impl < 'a , REG > HpreW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div2) } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div4) } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div8) } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div16) } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn div64 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div64) } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn div128 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div128) } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn div256 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div256) } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn div512 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div512) } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div1) } } # [doc = "APB Low speed prescaler (APB1)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Ppre1 { # [doc = "4: HCLK divided by 2"] Div2 = 4 , # [doc = "5: HCLK divided by 4"] Div4 = 5 , # [doc = "6: HCLK divided by 8"] Div8 = 6 , # [doc = "7: HCLK divided by 16"] Div16 = 7 , # [doc = "0: HCLK not divided"] Div1 = 0 , } impl From < Ppre1 > for u8 { # [inline (always)] fn from (variant : Ppre1) -> Self { variant as _ } } impl crate :: FieldSpec for Ppre1 { type Ux = u8 ; } impl crate :: IsEnum for Ppre1 { } # [doc = "Field `PPRE1` reader - APB Low speed prescaler (APB1)"] pub type Ppre1R = crate :: FieldReader < Ppre1 > ; impl Ppre1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ppre1 { match self . bits { 4 => Ppre1 :: Div2 , 5 => Ppre1 :: Div4 , 6 => Ppre1 :: Div8 , 7 => Ppre1 :: Div16 , _ => Ppre1 :: Div1 , } } # [doc = "HCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Ppre1 :: Div2 } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Ppre1 :: Div4 } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Ppre1 :: Div8 } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Ppre1 :: Div16 } # [doc = "HCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Ppre1 :: Div1) } } # [doc = "Field `PPRE1` writer - APB Low speed prescaler (APB1)"] pub type Ppre1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Ppre1 , crate :: Safe > ; impl < 'a , REG > Ppre1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div2) } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div4) } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div8) } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div16) } # [doc = "HCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div1) } } # [doc = "Field `PPRE2` reader - APB high-speed prescaler (APB2)"] pub use Ppre1R as Ppre2R ; # [doc = "Field `PPRE2` writer - APB high-speed prescaler (APB2)"] pub use Ppre1W as Ppre2W ; # [doc = "Field `RTCPRE` reader - HSE division factor for RTC clock"] pub type RtcpreR = crate :: FieldReader ; # [doc = "Field `RTCPRE` writer - HSE division factor for RTC clock"] pub type RtcpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Microcontroller clock output 1\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1 { # [doc = "0: HSI clock selected"] Hsi = 0 , # [doc = "1: LSE oscillator selected"] Lse = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco1 > for u8 { # [inline (always)] fn from (variant : Mco1) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1 { type Ux = u8 ; } impl crate :: IsEnum for Mco1 { } # [doc = "Field `MCO1` reader - Microcontroller clock output 1"] pub type Mco1R = crate :: FieldReader < Mco1 > ; impl Mco1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1 { match self . bits { 0 => Mco1 :: Hsi , 1 => Mco1 :: Lse , 2 => Mco1 :: Hse , 3 => Mco1 :: Pll , _ => unreachable ! () , } } # [doc = "HSI clock selected"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Mco1 :: Hsi } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn is_lse (& self) -> bool { * self == Mco1 :: Lse } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco1 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco1 :: Pll } } # [doc = "Field `MCO1` writer - Microcontroller clock output 1"] pub type Mco1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco1 , crate :: Safe > ; impl < 'a , REG > Mco1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI clock selected"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hsi) } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn lse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Lse) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Pll) } } # [doc = "I2S clock selection\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum I2ssrc { # [doc = "0: PLLI2S clock used as I2S clock source"] Plli2s = 0 , # [doc = "1: External clock mapped on the I2S_CKIN pin used as I2S clock source"] Ckin = 1 , } impl From < I2ssrc > for bool { # [inline (always)] fn from (variant : I2ssrc) -> Self { variant as u8 != 0 } } # [doc = "Field `I2SSRC` reader - I2S clock selection"] pub type I2ssrcR = crate :: BitReader < I2ssrc > ; impl I2ssrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> I2ssrc { match self . bits { false => I2ssrc :: Plli2s , true => I2ssrc :: Ckin , } } # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == I2ssrc :: Plli2s } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn is_ckin (& self) -> bool { * self == I2ssrc :: Ckin } } # [doc = "Field `I2SSRC` writer - I2S clock selection"] pub type I2ssrcW < 'a , REG > = crate :: BitWriter < 'a , REG , I2ssrc > ; impl < 'a , REG > I2ssrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Plli2s) } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn ckin (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Ckin) } } # [doc = "MCO1 prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1pre { # [doc = "4: Division by 2"] Div2 = 4 , # [doc = "5: Division by 3"] Div3 = 5 , # [doc = "6: Division by 4"] Div4 = 6 , # [doc = "7: Division by 5"] Div5 = 7 , # [doc = "0: No division"] Div1 = 0 , } impl From < Mco1pre > for u8 { # [inline (always)] fn from (variant : Mco1pre) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1pre { type Ux = u8 ; } impl crate :: IsEnum for Mco1pre { } # [doc = "Field `MCO1PRE` reader - MCO1 prescaler"] pub type Mco1preR = crate :: FieldReader < Mco1pre > ; impl Mco1preR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1pre { match self . bits { 4 => Mco1pre :: Div2 , 5 => Mco1pre :: Div3 , 6 => Mco1pre :: Div4 , 7 => Mco1pre :: Div5 , _ => Mco1pre :: Div1 , } } # [doc = "Division by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Mco1pre :: Div2 } # [doc = "Division by 3"] # [inline (always)] pub fn is_div3 (& self) -> bool { * self == Mco1pre :: Div3 } # [doc = "Division by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Mco1pre :: Div4 } # [doc = "Division by 5"] # [inline (always)] pub fn is_div5 (& self) -> bool { * self == Mco1pre :: Div5 } # [doc = "No division"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Mco1pre :: Div1) } } # [doc = "Field `MCO1PRE` writer - MCO1 prescaler"] pub type Mco1preW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Mco1pre , crate :: Safe > ; impl < 'a , REG > Mco1preW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Division by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div2) } # [doc = "Division by 3"] # [inline (always)] pub fn div3 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div3) } # [doc = "Division by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div4) } # [doc = "Division by 5"] # [inline (always)] pub fn div5 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div5) } # [doc = "No division"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div1) } } # [doc = "Field `MCO2PRE` reader - MCO2 prescaler"] pub use Mco1preR as Mco2preR ; # [doc = "Field `MCO2PRE` writer - MCO2 prescaler"] pub use Mco1preW as Mco2preW ; # [doc = "Microcontroller clock output 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco2 { # [doc = "0: System clock (SYSCLK) selected"] Sysclk = 0 , # [doc = "1: PLLI2S clock selected"] Plli2s = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco2 > for u8 { # [inline (always)] fn from (variant : Mco2) -> Self { variant as _ } } impl crate :: FieldSpec for Mco2 { type Ux = u8 ; } impl crate :: IsEnum for Mco2 { } # [doc = "Field `MCO2` reader - Microcontroller clock output 2"] pub type Mco2R = crate :: FieldReader < Mco2 > ; impl Mco2R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco2 { match self . bits { 0 => Mco2 :: Sysclk , 1 => Mco2 :: Plli2s , 2 => Mco2 :: Hse , 3 => Mco2 :: Pll , _ => unreachable ! () , } } # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn is_sysclk (& self) -> bool { * self == Mco2 :: Sysclk } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == Mco2 :: Plli2s } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco2 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco2 :: Pll } } # [doc = "Field `MCO2` writer - Microcontroller clock output 2"] pub type Mco2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco2 , crate :: Safe > ; impl < 'a , REG > Mco2W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn sysclk (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Sysclk) } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Plli2s) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Pll) } } impl R { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& self) -> SwR { SwR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& self) -> SwsR { SwsR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& self) -> HpreR { HpreR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& self) -> Ppre1R { Ppre1R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& self) -> Ppre2R { Ppre2R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& self) -> RtcpreR { RtcpreR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& self) -> Mco1R { Mco1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& self) -> I2ssrcR { I2ssrcR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& self) -> Mco1preR { Mco1preR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& self) -> Mco2preR { Mco2preR :: new (((self . bits >> 27) & 7) as u8) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& self) -> Mco2R { Mco2R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& mut self) -> SwW < CfgrSpec > { SwW :: new (self , 0) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& mut self) -> SwsW < CfgrSpec > { SwsW :: new (self , 2) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& mut self) -> HpreW < CfgrSpec > { HpreW :: new (self , 4) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& mut self) -> Ppre1W < CfgrSpec > { Ppre1W :: new (self , 10) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& mut self) -> Ppre2W < CfgrSpec > { Ppre2W :: new (self , 13) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& mut self) -> RtcpreW <'_, CfgrSpec > { RtcpreW :: new (self , 16) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& mut self) -> Mco1W < CfgrSpec > { Mco1W :: new (self , 21) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& mut self) -> I2ssrcW < CfgrSpec > { I2ssrcW :: new (self , 23) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& mut self) -> Mco1preW < CfgrSpec > { Mco1preW :: new (self , 24) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& mut self) -> Mco2preW < CfgrSpec > { Mco2preW :: new (self , 27) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& mut self) -> Mco2W < CfgrSpec > { Mco2W :: new (self , 30) } } # [doc = "clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgrSpec ; impl crate :: RegisterSpec for CfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr::R`](R) reader structure"] impl crate :: Readable for CfgrSpec { } # [doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"] impl crate :: Writable for CfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CFGR to value 0"] impl crate :: Resettable for CfgrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cfgr.rs:1:21704 [INFO] [stdout] | [INFO] [stdout] 1 | ... # [inline (always)] pub fn mco1 (& mut self) -> Mco1W < CfgrSpec > { Mco1W :: new (self , 21) } # [doc = "Bit 23 - I2S clock selectio... [INFO] [stdout] | ^^^^^^^^^^ ------------------ the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGR` reader"] pub type R = crate :: R < CfgrSpec > ; # [doc = "Register `CFGR` writer"] pub type W = crate :: W < CfgrSpec > ; # [doc = "System clock switch\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Sw { # [doc = "0: HSI selected as system clock"] Hsi = 0 , # [doc = "1: HSE selected as system clock"] Hse = 1 , # [doc = "2: PLL selected as system clock"] Pll = 2 , } impl From < Sw > for u8 { # [inline (always)] fn from (variant : Sw) -> Self { variant as _ } } impl crate :: FieldSpec for Sw { type Ux = u8 ; } impl crate :: IsEnum for Sw { } # [doc = "Field `SW` reader - System clock switch"] pub type SwR = crate :: FieldReader < Sw > ; impl SwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Sw > { match self . bits { 0 => Some (Sw :: Hsi) , 1 => Some (Sw :: Hse) , 2 => Some (Sw :: Pll) , _ => None , } } # [doc = "HSI selected as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Sw :: Hsi } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Sw :: Hse } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Sw :: Pll } } # [doc = "Field `SW` writer - System clock switch"] pub type SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Sw > ; impl < 'a , REG > SwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI selected as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hsi) } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hse) } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Pll) } } # [doc = "System clock switch status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Swsr { # [doc = "0: HSI oscillator used as system clock"] Hsi = 0 , # [doc = "1: HSE oscillator used as system clock"] Hse = 1 , # [doc = "2: PLL used as system clock"] Pll = 2 , } impl From < Swsr > for u8 { # [inline (always)] fn from (variant : Swsr) -> Self { variant as _ } } impl crate :: FieldSpec for Swsr { type Ux = u8 ; } impl crate :: IsEnum for Swsr { } # [doc = "Field `SWS` reader - System clock switch status"] pub type SwsR = crate :: FieldReader < Swsr > ; impl SwsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Swsr > { match self . bits { 0 => Some (Swsr :: Hsi) , 1 => Some (Swsr :: Hse) , 2 => Some (Swsr :: Pll) , _ => None , } } # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Swsr :: Hsi } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Swsr :: Hse } # [doc = "PLL used as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Swsr :: Pll } } # [doc = "Field `SWS` writer - System clock switch status"] pub type SwsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Swsr > ; impl < 'a , REG > SwsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hsi) } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hse) } # [doc = "PLL used as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Pll) } } # [doc = "AHB prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Hpre { # [doc = "8: SYSCLK divided by 2"] Div2 = 8 , # [doc = "9: SYSCLK divided by 4"] Div4 = 9 , # [doc = "10: SYSCLK divided by 8"] Div8 = 10 , # [doc = "11: SYSCLK divided by 16"] Div16 = 11 , # [doc = "12: SYSCLK divided by 64"] Div64 = 12 , # [doc = "13: SYSCLK divided by 128"] Div128 = 13 , # [doc = "14: SYSCLK divided by 256"] Div256 = 14 , # [doc = "15: SYSCLK divided by 512"] Div512 = 15 , # [doc = "0: SYSCLK not divided"] Div1 = 0 , } impl From < Hpre > for u8 { # [inline (always)] fn from (variant : Hpre) -> Self { variant as _ } } impl crate :: FieldSpec for Hpre { type Ux = u8 ; } impl crate :: IsEnum for Hpre { } # [doc = "Field `HPRE` reader - AHB prescaler"] pub type HpreR = crate :: FieldReader < Hpre > ; impl HpreR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hpre { match self . bits { 8 => Hpre :: Div2 , 9 => Hpre :: Div4 , 10 => Hpre :: Div8 , 11 => Hpre :: Div16 , 12 => Hpre :: Div64 , 13 => Hpre :: Div128 , 14 => Hpre :: Div256 , 15 => Hpre :: Div512 , _ => Hpre :: Div1 , } } # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Hpre :: Div2 } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Hpre :: Div4 } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Hpre :: Div8 } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Hpre :: Div16 } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn is_div64 (& self) -> bool { * self == Hpre :: Div64 } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn is_div128 (& self) -> bool { * self == Hpre :: Div128 } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn is_div256 (& self) -> bool { * self == Hpre :: Div256 } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn is_div512 (& self) -> bool { * self == Hpre :: Div512 } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Hpre :: Div1) } } # [doc = "Field `HPRE` writer - AHB prescaler"] pub type HpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , Hpre , crate :: Safe > ; impl < 'a , REG > HpreW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div2) } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div4) } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div8) } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div16) } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn div64 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div64) } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn div128 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div128) } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn div256 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div256) } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn div512 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div512) } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div1) } } # [doc = "APB Low speed prescaler (APB1)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Ppre1 { # [doc = "4: HCLK divided by 2"] Div2 = 4 , # [doc = "5: HCLK divided by 4"] Div4 = 5 , # [doc = "6: HCLK divided by 8"] Div8 = 6 , # [doc = "7: HCLK divided by 16"] Div16 = 7 , # [doc = "0: HCLK not divided"] Div1 = 0 , } impl From < Ppre1 > for u8 { # [inline (always)] fn from (variant : Ppre1) -> Self { variant as _ } } impl crate :: FieldSpec for Ppre1 { type Ux = u8 ; } impl crate :: IsEnum for Ppre1 { } # [doc = "Field `PPRE1` reader - APB Low speed prescaler (APB1)"] pub type Ppre1R = crate :: FieldReader < Ppre1 > ; impl Ppre1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ppre1 { match self . bits { 4 => Ppre1 :: Div2 , 5 => Ppre1 :: Div4 , 6 => Ppre1 :: Div8 , 7 => Ppre1 :: Div16 , _ => Ppre1 :: Div1 , } } # [doc = "HCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Ppre1 :: Div2 } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Ppre1 :: Div4 } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Ppre1 :: Div8 } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Ppre1 :: Div16 } # [doc = "HCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Ppre1 :: Div1) } } # [doc = "Field `PPRE1` writer - APB Low speed prescaler (APB1)"] pub type Ppre1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Ppre1 , crate :: Safe > ; impl < 'a , REG > Ppre1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div2) } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div4) } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div8) } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div16) } # [doc = "HCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div1) } } # [doc = "Field `PPRE2` reader - APB high-speed prescaler (APB2)"] pub use Ppre1R as Ppre2R ; # [doc = "Field `PPRE2` writer - APB high-speed prescaler (APB2)"] pub use Ppre1W as Ppre2W ; # [doc = "Field `RTCPRE` reader - HSE division factor for RTC clock"] pub type RtcpreR = crate :: FieldReader ; # [doc = "Field `RTCPRE` writer - HSE division factor for RTC clock"] pub type RtcpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Microcontroller clock output 1\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1 { # [doc = "0: HSI clock selected"] Hsi = 0 , # [doc = "1: LSE oscillator selected"] Lse = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco1 > for u8 { # [inline (always)] fn from (variant : Mco1) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1 { type Ux = u8 ; } impl crate :: IsEnum for Mco1 { } # [doc = "Field `MCO1` reader - Microcontroller clock output 1"] pub type Mco1R = crate :: FieldReader < Mco1 > ; impl Mco1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1 { match self . bits { 0 => Mco1 :: Hsi , 1 => Mco1 :: Lse , 2 => Mco1 :: Hse , 3 => Mco1 :: Pll , _ => unreachable ! () , } } # [doc = "HSI clock selected"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Mco1 :: Hsi } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn is_lse (& self) -> bool { * self == Mco1 :: Lse } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco1 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco1 :: Pll } } # [doc = "Field `MCO1` writer - Microcontroller clock output 1"] pub type Mco1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco1 , crate :: Safe > ; impl < 'a , REG > Mco1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI clock selected"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hsi) } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn lse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Lse) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Pll) } } # [doc = "I2S clock selection\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum I2ssrc { # [doc = "0: PLLI2S clock used as I2S clock source"] Plli2s = 0 , # [doc = "1: External clock mapped on the I2S_CKIN pin used as I2S clock source"] Ckin = 1 , } impl From < I2ssrc > for bool { # [inline (always)] fn from (variant : I2ssrc) -> Self { variant as u8 != 0 } } # [doc = "Field `I2SSRC` reader - I2S clock selection"] pub type I2ssrcR = crate :: BitReader < I2ssrc > ; impl I2ssrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> I2ssrc { match self . bits { false => I2ssrc :: Plli2s , true => I2ssrc :: Ckin , } } # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == I2ssrc :: Plli2s } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn is_ckin (& self) -> bool { * self == I2ssrc :: Ckin } } # [doc = "Field `I2SSRC` writer - I2S clock selection"] pub type I2ssrcW < 'a , REG > = crate :: BitWriter < 'a , REG , I2ssrc > ; impl < 'a , REG > I2ssrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Plli2s) } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn ckin (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Ckin) } } # [doc = "MCO1 prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1pre { # [doc = "4: Division by 2"] Div2 = 4 , # [doc = "5: Division by 3"] Div3 = 5 , # [doc = "6: Division by 4"] Div4 = 6 , # [doc = "7: Division by 5"] Div5 = 7 , # [doc = "0: No division"] Div1 = 0 , } impl From < Mco1pre > for u8 { # [inline (always)] fn from (variant : Mco1pre) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1pre { type Ux = u8 ; } impl crate :: IsEnum for Mco1pre { } # [doc = "Field `MCO1PRE` reader - MCO1 prescaler"] pub type Mco1preR = crate :: FieldReader < Mco1pre > ; impl Mco1preR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1pre { match self . bits { 4 => Mco1pre :: Div2 , 5 => Mco1pre :: Div3 , 6 => Mco1pre :: Div4 , 7 => Mco1pre :: Div5 , _ => Mco1pre :: Div1 , } } # [doc = "Division by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Mco1pre :: Div2 } # [doc = "Division by 3"] # [inline (always)] pub fn is_div3 (& self) -> bool { * self == Mco1pre :: Div3 } # [doc = "Division by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Mco1pre :: Div4 } # [doc = "Division by 5"] # [inline (always)] pub fn is_div5 (& self) -> bool { * self == Mco1pre :: Div5 } # [doc = "No division"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Mco1pre :: Div1) } } # [doc = "Field `MCO1PRE` writer - MCO1 prescaler"] pub type Mco1preW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Mco1pre , crate :: Safe > ; impl < 'a , REG > Mco1preW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Division by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div2) } # [doc = "Division by 3"] # [inline (always)] pub fn div3 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div3) } # [doc = "Division by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div4) } # [doc = "Division by 5"] # [inline (always)] pub fn div5 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div5) } # [doc = "No division"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div1) } } # [doc = "Field `MCO2PRE` reader - MCO2 prescaler"] pub use Mco1preR as Mco2preR ; # [doc = "Field `MCO2PRE` writer - MCO2 prescaler"] pub use Mco1preW as Mco2preW ; # [doc = "Microcontroller clock output 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco2 { # [doc = "0: System clock (SYSCLK) selected"] Sysclk = 0 , # [doc = "1: PLLI2S clock selected"] Plli2s = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco2 > for u8 { # [inline (always)] fn from (variant : Mco2) -> Self { variant as _ } } impl crate :: FieldSpec for Mco2 { type Ux = u8 ; } impl crate :: IsEnum for Mco2 { } # [doc = "Field `MCO2` reader - Microcontroller clock output 2"] pub type Mco2R = crate :: FieldReader < Mco2 > ; impl Mco2R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco2 { match self . bits { 0 => Mco2 :: Sysclk , 1 => Mco2 :: Plli2s , 2 => Mco2 :: Hse , 3 => Mco2 :: Pll , _ => unreachable ! () , } } # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn is_sysclk (& self) -> bool { * self == Mco2 :: Sysclk } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == Mco2 :: Plli2s } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco2 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco2 :: Pll } } # [doc = "Field `MCO2` writer - Microcontroller clock output 2"] pub type Mco2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco2 , crate :: Safe > ; impl < 'a , REG > Mco2W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn sysclk (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Sysclk) } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Plli2s) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Pll) } } impl R { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& self) -> SwR { SwR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& self) -> SwsR { SwsR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& self) -> HpreR { HpreR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& self) -> Ppre1R { Ppre1R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& self) -> Ppre2R { Ppre2R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& self) -> RtcpreR { RtcpreR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& self) -> Mco1R { Mco1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& self) -> I2ssrcR { I2ssrcR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& self) -> Mco1preR { Mco1preR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& self) -> Mco2preR { Mco2preR :: new (((self . bits >> 27) & 7) as u8) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& self) -> Mco2R { Mco2R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& mut self) -> SwW < CfgrSpec > { SwW :: new (self , 0) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& mut self) -> SwsW < CfgrSpec > { SwsW :: new (self , 2) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& mut self) -> HpreW < CfgrSpec > { HpreW :: new (self , 4) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& mut self) -> Ppre1W < CfgrSpec > { Ppre1W :: new (self , 10) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& mut self) -> Ppre2W < CfgrSpec > { Ppre2W :: new (self , 13) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& mut self) -> RtcpreW < CfgrSpec > { RtcpreW :: new (self , 16) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& mut self) -> Mco1W <'_, CfgrSpec > { Mco1W :: new (self , 21) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& mut self) -> I2ssrcW < CfgrSpec > { I2ssrcW :: new (self , 23) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& mut self) -> Mco1preW < CfgrSpec > { Mco1preW :: new (self , 24) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& mut self) -> Mco2preW < CfgrSpec > { Mco2preW :: new (self , 27) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& mut self) -> Mco2W < CfgrSpec > { Mco2W :: new (self , 30) } } # [doc = "clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgrSpec ; impl crate :: RegisterSpec for CfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr::R`](R) reader structure"] impl crate :: Readable for CfgrSpec { } # [doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"] impl crate :: Writable for CfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CFGR to value 0"] impl crate :: Resettable for CfgrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/rcc/cfgr.rs:1:21843 [INFO] [stdout] | [INFO] [stdout] 1 | ...[inline (always)] pub fn i2ssrc (& mut self) -> I2ssrcW < CfgrSpec > { I2ssrcW :: new (self , 23) } # [doc = "Bits 24:26 - MCO1 presca... [INFO] [stdout] | ^^^^^^^^^^ -------------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [INFO] [stdout] 1 | # [doc = "Register `CFGR` reader"] pub type R = crate :: R < CfgrSpec > ; # [doc = "Register `CFGR` writer"] pub type W = crate :: W < CfgrSpec > ; # [doc = "System clock switch\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Sw { # [doc = "0: HSI selected as system clock"] Hsi = 0 , # [doc = "1: HSE selected as system clock"] Hse = 1 , # [doc = "2: PLL selected as system clock"] Pll = 2 , } impl From < Sw > for u8 { # [inline (always)] fn from (variant : Sw) -> Self { variant as _ } } impl crate :: FieldSpec for Sw { type Ux = u8 ; } impl crate :: IsEnum for Sw { } # [doc = "Field `SW` reader - System clock switch"] pub type SwR = crate :: FieldReader < Sw > ; impl SwR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Sw > { match self . bits { 0 => Some (Sw :: Hsi) , 1 => Some (Sw :: Hse) , 2 => Some (Sw :: Pll) , _ => None , } } # [doc = "HSI selected as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Sw :: Hsi } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Sw :: Hse } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Sw :: Pll } } # [doc = "Field `SW` writer - System clock switch"] pub type SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Sw > ; impl < 'a , REG > SwW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI selected as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hsi) } # [doc = "HSE selected as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Hse) } # [doc = "PLL selected as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Sw :: Pll) } } # [doc = "System clock switch status\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Swsr { # [doc = "0: HSI oscillator used as system clock"] Hsi = 0 , # [doc = "1: HSE oscillator used as system clock"] Hse = 1 , # [doc = "2: PLL used as system clock"] Pll = 2 , } impl From < Swsr > for u8 { # [inline (always)] fn from (variant : Swsr) -> Self { variant as _ } } impl crate :: FieldSpec for Swsr { type Ux = u8 ; } impl crate :: IsEnum for Swsr { } # [doc = "Field `SWS` reader - System clock switch status"] pub type SwsR = crate :: FieldReader < Swsr > ; impl SwsR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Option < Swsr > { match self . bits { 0 => Some (Swsr :: Hsi) , 1 => Some (Swsr :: Hse) , 2 => Some (Swsr :: Pll) , _ => None , } } # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Swsr :: Hsi } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Swsr :: Hse } # [doc = "PLL used as system clock"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Swsr :: Pll } } # [doc = "Field `SWS` writer - System clock switch status"] pub type SwsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Swsr > ; impl < 'a , REG > SwsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI oscillator used as system clock"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hsi) } # [doc = "HSE oscillator used as system clock"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Hse) } # [doc = "PLL used as system clock"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Swsr :: Pll) } } # [doc = "AHB prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Hpre { # [doc = "8: SYSCLK divided by 2"] Div2 = 8 , # [doc = "9: SYSCLK divided by 4"] Div4 = 9 , # [doc = "10: SYSCLK divided by 8"] Div8 = 10 , # [doc = "11: SYSCLK divided by 16"] Div16 = 11 , # [doc = "12: SYSCLK divided by 64"] Div64 = 12 , # [doc = "13: SYSCLK divided by 128"] Div128 = 13 , # [doc = "14: SYSCLK divided by 256"] Div256 = 14 , # [doc = "15: SYSCLK divided by 512"] Div512 = 15 , # [doc = "0: SYSCLK not divided"] Div1 = 0 , } impl From < Hpre > for u8 { # [inline (always)] fn from (variant : Hpre) -> Self { variant as _ } } impl crate :: FieldSpec for Hpre { type Ux = u8 ; } impl crate :: IsEnum for Hpre { } # [doc = "Field `HPRE` reader - AHB prescaler"] pub type HpreR = crate :: FieldReader < Hpre > ; impl HpreR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Hpre { match self . bits { 8 => Hpre :: Div2 , 9 => Hpre :: Div4 , 10 => Hpre :: Div8 , 11 => Hpre :: Div16 , 12 => Hpre :: Div64 , 13 => Hpre :: Div128 , 14 => Hpre :: Div256 , 15 => Hpre :: Div512 , _ => Hpre :: Div1 , } } # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Hpre :: Div2 } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Hpre :: Div4 } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Hpre :: Div8 } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Hpre :: Div16 } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn is_div64 (& self) -> bool { * self == Hpre :: Div64 } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn is_div128 (& self) -> bool { * self == Hpre :: Div128 } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn is_div256 (& self) -> bool { * self == Hpre :: Div256 } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn is_div512 (& self) -> bool { * self == Hpre :: Div512 } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Hpre :: Div1) } } # [doc = "Field `HPRE` writer - AHB prescaler"] pub type HpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , Hpre , crate :: Safe > ; impl < 'a , REG > HpreW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div2) } # [doc = "SYSCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div4) } # [doc = "SYSCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div8) } # [doc = "SYSCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div16) } # [doc = "SYSCLK divided by 64"] # [inline (always)] pub fn div64 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div64) } # [doc = "SYSCLK divided by 128"] # [inline (always)] pub fn div128 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div128) } # [doc = "SYSCLK divided by 256"] # [inline (always)] pub fn div256 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div256) } # [doc = "SYSCLK divided by 512"] # [inline (always)] pub fn div512 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div512) } # [doc = "SYSCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Hpre :: Div1) } } # [doc = "APB Low speed prescaler (APB1)\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Ppre1 { # [doc = "4: HCLK divided by 2"] Div2 = 4 , # [doc = "5: HCLK divided by 4"] Div4 = 5 , # [doc = "6: HCLK divided by 8"] Div8 = 6 , # [doc = "7: HCLK divided by 16"] Div16 = 7 , # [doc = "0: HCLK not divided"] Div1 = 0 , } impl From < Ppre1 > for u8 { # [inline (always)] fn from (variant : Ppre1) -> Self { variant as _ } } impl crate :: FieldSpec for Ppre1 { type Ux = u8 ; } impl crate :: IsEnum for Ppre1 { } # [doc = "Field `PPRE1` reader - APB Low speed prescaler (APB1)"] pub type Ppre1R = crate :: FieldReader < Ppre1 > ; impl Ppre1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Ppre1 { match self . bits { 4 => Ppre1 :: Div2 , 5 => Ppre1 :: Div4 , 6 => Ppre1 :: Div8 , 7 => Ppre1 :: Div16 , _ => Ppre1 :: Div1 , } } # [doc = "HCLK divided by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Ppre1 :: Div2 } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Ppre1 :: Div4 } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn is_div8 (& self) -> bool { * self == Ppre1 :: Div8 } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn is_div16 (& self) -> bool { * self == Ppre1 :: Div16 } # [doc = "HCLK not divided"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Ppre1 :: Div1) } } # [doc = "Field `PPRE1` writer - APB Low speed prescaler (APB1)"] pub type Ppre1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Ppre1 , crate :: Safe > ; impl < 'a , REG > Ppre1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HCLK divided by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div2) } # [doc = "HCLK divided by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div4) } # [doc = "HCLK divided by 8"] # [inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div8) } # [doc = "HCLK divided by 16"] # [inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div16) } # [doc = "HCLK not divided"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Ppre1 :: Div1) } } # [doc = "Field `PPRE2` reader - APB high-speed prescaler (APB2)"] pub use Ppre1R as Ppre2R ; # [doc = "Field `PPRE2` writer - APB high-speed prescaler (APB2)"] pub use Ppre1W as Ppre2W ; # [doc = "Field `RTCPRE` reader - HSE division factor for RTC clock"] pub type RtcpreR = crate :: FieldReader ; # [doc = "Field `RTCPRE` writer - HSE division factor for RTC clock"] pub type RtcpreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 , u8 , crate :: Safe > ; # [doc = "Microcontroller clock output 1\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1 { # [doc = "0: HSI clock selected"] Hsi = 0 , # [doc = "1: LSE oscillator selected"] Lse = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco1 > for u8 { # [inline (always)] fn from (variant : Mco1) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1 { type Ux = u8 ; } impl crate :: IsEnum for Mco1 { } # [doc = "Field `MCO1` reader - Microcontroller clock output 1"] pub type Mco1R = crate :: FieldReader < Mco1 > ; impl Mco1R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1 { match self . bits { 0 => Mco1 :: Hsi , 1 => Mco1 :: Lse , 2 => Mco1 :: Hse , 3 => Mco1 :: Pll , _ => unreachable ! () , } } # [doc = "HSI clock selected"] # [inline (always)] pub fn is_hsi (& self) -> bool { * self == Mco1 :: Hsi } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn is_lse (& self) -> bool { * self == Mco1 :: Lse } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco1 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco1 :: Pll } } # [doc = "Field `MCO1` writer - Microcontroller clock output 1"] pub type Mco1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco1 , crate :: Safe > ; impl < 'a , REG > Mco1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "HSI clock selected"] # [inline (always)] pub fn hsi (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hsi) } # [doc = "LSE oscillator selected"] # [inline (always)] pub fn lse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Lse) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1 :: Pll) } } # [doc = "I2S clock selection\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum I2ssrc { # [doc = "0: PLLI2S clock used as I2S clock source"] Plli2s = 0 , # [doc = "1: External clock mapped on the I2S_CKIN pin used as I2S clock source"] Ckin = 1 , } impl From < I2ssrc > for bool { # [inline (always)] fn from (variant : I2ssrc) -> Self { variant as u8 != 0 } } # [doc = "Field `I2SSRC` reader - I2S clock selection"] pub type I2ssrcR = crate :: BitReader < I2ssrc > ; impl I2ssrcR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> I2ssrc { match self . bits { false => I2ssrc :: Plli2s , true => I2ssrc :: Ckin , } } # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == I2ssrc :: Plli2s } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn is_ckin (& self) -> bool { * self == I2ssrc :: Ckin } } # [doc = "Field `I2SSRC` writer - I2S clock selection"] pub type I2ssrcW < 'a , REG > = crate :: BitWriter < 'a , REG , I2ssrc > ; impl < 'a , REG > I2ssrcW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "PLLI2S clock used as I2S clock source"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Plli2s) } # [doc = "External clock mapped on the I2S_CKIN pin used as I2S clock source"] # [inline (always)] pub fn ckin (self) -> & 'a mut crate :: W < REG > { self . variant (I2ssrc :: Ckin) } } # [doc = "MCO1 prescaler\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco1pre { # [doc = "4: Division by 2"] Div2 = 4 , # [doc = "5: Division by 3"] Div3 = 5 , # [doc = "6: Division by 4"] Div4 = 6 , # [doc = "7: Division by 5"] Div5 = 7 , # [doc = "0: No division"] Div1 = 0 , } impl From < Mco1pre > for u8 { # [inline (always)] fn from (variant : Mco1pre) -> Self { variant as _ } } impl crate :: FieldSpec for Mco1pre { type Ux = u8 ; } impl crate :: IsEnum for Mco1pre { } # [doc = "Field `MCO1PRE` reader - MCO1 prescaler"] pub type Mco1preR = crate :: FieldReader < Mco1pre > ; impl Mco1preR { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco1pre { match self . bits { 4 => Mco1pre :: Div2 , 5 => Mco1pre :: Div3 , 6 => Mco1pre :: Div4 , 7 => Mco1pre :: Div5 , _ => Mco1pre :: Div1 , } } # [doc = "Division by 2"] # [inline (always)] pub fn is_div2 (& self) -> bool { * self == Mco1pre :: Div2 } # [doc = "Division by 3"] # [inline (always)] pub fn is_div3 (& self) -> bool { * self == Mco1pre :: Div3 } # [doc = "Division by 4"] # [inline (always)] pub fn is_div4 (& self) -> bool { * self == Mco1pre :: Div4 } # [doc = "Division by 5"] # [inline (always)] pub fn is_div5 (& self) -> bool { * self == Mco1pre :: Div5 } # [doc = "No division"] # [inline (always)] pub fn is_div1 (& self) -> bool { matches ! (self . variant () , Mco1pre :: Div1) } } # [doc = "Field `MCO1PRE` writer - MCO1 prescaler"] pub type Mco1preW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , Mco1pre , crate :: Safe > ; impl < 'a , REG > Mco1preW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "Division by 2"] # [inline (always)] pub fn div2 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div2) } # [doc = "Division by 3"] # [inline (always)] pub fn div3 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div3) } # [doc = "Division by 4"] # [inline (always)] pub fn div4 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div4) } # [doc = "Division by 5"] # [inline (always)] pub fn div5 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div5) } # [doc = "No division"] # [inline (always)] pub fn div1 (self) -> & 'a mut crate :: W < REG > { self . variant (Mco1pre :: Div1) } } # [doc = "Field `MCO2PRE` reader - MCO2 prescaler"] pub use Mco1preR as Mco2preR ; # [doc = "Field `MCO2PRE` writer - MCO2 prescaler"] pub use Mco1preW as Mco2preW ; # [doc = "Microcontroller clock output 2\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] # [repr (u8)] pub enum Mco2 { # [doc = "0: System clock (SYSCLK) selected"] Sysclk = 0 , # [doc = "1: PLLI2S clock selected"] Plli2s = 1 , # [doc = "2: HSE oscillator clock selected"] Hse = 2 , # [doc = "3: PLL clock selected"] Pll = 3 , } impl From < Mco2 > for u8 { # [inline (always)] fn from (variant : Mco2) -> Self { variant as _ } } impl crate :: FieldSpec for Mco2 { type Ux = u8 ; } impl crate :: IsEnum for Mco2 { } # [doc = "Field `MCO2` reader - Microcontroller clock output 2"] pub type Mco2R = crate :: FieldReader < Mco2 > ; impl Mco2R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> Mco2 { match self . bits { 0 => Mco2 :: Sysclk , 1 => Mco2 :: Plli2s , 2 => Mco2 :: Hse , 3 => Mco2 :: Pll , _ => unreachable ! () , } } # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn is_sysclk (& self) -> bool { * self == Mco2 :: Sysclk } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn is_plli2s (& self) -> bool { * self == Mco2 :: Plli2s } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn is_hse (& self) -> bool { * self == Mco2 :: Hse } # [doc = "PLL clock selected"] # [inline (always)] pub fn is_pll (& self) -> bool { * self == Mco2 :: Pll } } # [doc = "Field `MCO2` writer - Microcontroller clock output 2"] pub type Mco2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mco2 , crate :: Safe > ; impl < 'a , REG > Mco2W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "System clock (SYSCLK) selected"] # [inline (always)] pub fn sysclk (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Sysclk) } # [doc = "PLLI2S clock selected"] # [inline (always)] pub fn plli2s (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Plli2s) } # [doc = "HSE oscillator clock selected"] # [inline (always)] pub fn hse (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Hse) } # [doc = "PLL clock selected"] # [inline (always)] pub fn pll (self) -> & 'a mut crate :: W < REG > { self . variant (Mco2 :: Pll) } } impl R { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& self) -> SwR { SwR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& self) -> SwsR { SwsR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& self) -> HpreR { HpreR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& self) -> Ppre1R { Ppre1R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& self) -> Ppre2R { Ppre2R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& self) -> RtcpreR { RtcpreR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& self) -> Mco1R { Mco1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& self) -> I2ssrcR { I2ssrcR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& self) -> Mco1preR { Mco1preR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& self) -> Mco2preR { Mco2preR :: new (((self . bits >> 27) & 7) as u8) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& self) -> Mco2R { Mco2R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - System clock switch"] # [inline (always)] pub fn sw (& mut self) -> SwW < CfgrSpec > { SwW :: new (self , 0) } # [doc = "Bits 2:3 - System clock switch status"] # [inline (always)] pub fn sws (& mut self) -> SwsW < CfgrSpec > { SwsW :: new (self , 2) } # [doc = "Bits 4:7 - AHB prescaler"] # [inline (always)] pub fn hpre (& mut self) -> HpreW < CfgrSpec > { HpreW :: new (self , 4) } # [doc = "Bits 10:12 - APB Low speed prescaler (APB1)"] # [inline (always)] pub fn ppre1 (& mut self) -> Ppre1W < CfgrSpec > { Ppre1W :: new (self , 10) } # [doc = "Bits 13:15 - APB high-speed prescaler (APB2)"] # [inline (always)] pub fn ppre2 (& mut self) -> Ppre2W < CfgrSpec > { Ppre2W :: new (self , 13) } # [doc = "Bits 16:20 - HSE division factor for RTC clock"] # [inline (always)] pub fn rtcpre (& mut self) -> RtcpreW < CfgrSpec > { RtcpreW :: new (self , 16) } # [doc = "Bits 21:22 - Microcontroller clock output 1"] # [inline (always)] pub fn mco1 (& mut self) -> Mco1W < CfgrSpec > { Mco1W :: new (self , 21) } # [doc = "Bit 23 - I2S clock selection"] # [inline (always)] pub fn i2ssrc (& mut self) -> I2ssrcW <'_, CfgrSpec > { I2ssrcW :: new (self , 23) } # [doc = "Bits 24:26 - MCO1 prescaler"] # [inline (always)] pub fn mco1pre (& mut self) -> Mco1preW < CfgrSpec > { Mco1preW :: new (self , 24) } # [doc = "Bits 27:29 - MCO2 prescaler"] # [inline (always)] pub fn mco2pre (& mut self) -> Mco2preW < CfgrSpec > { Mco2preW :: new (self , 27) } # [doc = "Bits 30:31 - Microcontroller clock output 2"] # [inline (always)] pub fn mco2 (& mut self) -> Mco2W < CfgrSpec > { Mco2W :: new (self , 30) } } # [doc = "clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgrSpec ; impl crate :: RegisterSpec for CfgrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr::R`](R) reader structure"] impl crate :: Readable for CfgrSpec { } # [doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"] impl crate :: Writable for CfgrSpec { type Safety = crate :: Unsafe ; } # [doc = "`reset()` method sets CFGR to value 0"] impl crate :: Resettable for CfgrSpec { } [INFO] [stdout] | +++ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: hiding a lifetime that's elided elsewhere is confusing [INFO] [stdout] --> stm32f4/src/dcmi/cr.rs:1:5274 [INFO] [stdout] | [INFO] [stdout] 1 | ...] # [inline (always)] pub fn fcrc (& mut self) -> FcrcW < CrSpec > { FcrcW :: new (self , 8) } # [doc = "Bits 10:11 - Extended data mo... [INFO] [stdout] | ^^^^^^^^^^ ---------------- the same lifetime is hidden here [INFO] [stdout] | | [INFO] [stdout] | the lifetime is elided here [INFO] [stdout] | [INFO] [stdout] = help: the same lifetime is referred to in inconsistent ways, making the signature confusing [INFO] [stdout] help: use `'_` for type paths [INFO] [stdout] | [WARN] too much data in the log, truncating it