[INFO] cloning repository https://github.com/TinyCoor/riscv-emulator [INFO] running `Command { std: "git" "-c" "credential.helper=" "-c" "credential.helper=/workspace/cargo-home/bin/git-credential-null" "clone" "--bare" "https://github.com/TinyCoor/riscv-emulator" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FTinyCoor%2Friscv-emulator", kill_on_drop: false }` [INFO] [stderr] Cloning into bare repository '/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FTinyCoor%2Friscv-emulator'... [INFO] running `Command { std: "git" "rev-parse" "HEAD", kill_on_drop: false }` [INFO] [stdout] c9f6d41eb63ade8cc812287c5a158ed5c403cb9a [INFO] checking TinyCoor/riscv-emulator against try#9961e55b3687a6d0b2bab4af0e5e81494b09be81 for pr-139087-1 [INFO] running `Command { std: "git" "clone" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FTinyCoor%2Friscv-emulator" "/workspace/builds/worker-6-tc2/source", kill_on_drop: false }` [INFO] [stderr] Cloning into '/workspace/builds/worker-6-tc2/source'... [INFO] [stderr] done. [INFO] started tweaking git repo https://github.com/TinyCoor/riscv-emulator [INFO] finished tweaking git repo https://github.com/TinyCoor/riscv-emulator [INFO] tweaked toml for git repo https://github.com/TinyCoor/riscv-emulator written to /workspace/builds/worker-6-tc2/source/Cargo.toml [INFO] validating manifest of git repo https://github.com/TinyCoor/riscv-emulator on toolchain 9961e55b3687a6d0b2bab4af0e5e81494b09be81 [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+9961e55b3687a6d0b2bab4af0e5e81494b09be81" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }` [INFO] crate git repo https://github.com/TinyCoor/riscv-emulator already has a lockfile, it will not be regenerated [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+9961e55b3687a6d0b2bab4af0e5e81494b09be81" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }` [INFO] [stderr] Blocking waiting for file lock on package cache [INFO] [stderr] Blocking waiting for file lock on package cache [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-6-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-6-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:d429b63d4308055ea97f60fb1d3dfca48854a00942f1bd2ad806beaf015945ec" "/opt/rustwide/cargo-home/bin/cargo" "+9961e55b3687a6d0b2bab4af0e5e81494b09be81" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }` [INFO] [stdout] d90d98741c5920f3be5c45fe9c31f9de23ac60563f9dad1bf76416bc147d2d5c [INFO] running `Command { std: "docker" "start" "-a" "d90d98741c5920f3be5c45fe9c31f9de23ac60563f9dad1bf76416bc147d2d5c", kill_on_drop: false }` [INFO] running `Command { std: "docker" "inspect" "d90d98741c5920f3be5c45fe9c31f9de23ac60563f9dad1bf76416bc147d2d5c", kill_on_drop: false }` [INFO] running `Command { std: "docker" "rm" "-f" "d90d98741c5920f3be5c45fe9c31f9de23ac60563f9dad1bf76416bc147d2d5c", kill_on_drop: false }` [INFO] [stdout] d90d98741c5920f3be5c45fe9c31f9de23ac60563f9dad1bf76416bc147d2d5c [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-6-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-6-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:d429b63d4308055ea97f60fb1d3dfca48854a00942f1bd2ad806beaf015945ec" "/opt/rustwide/cargo-home/bin/cargo" "+9961e55b3687a6d0b2bab4af0e5e81494b09be81" "check" "--frozen" "--all" "--all-targets" "--message-format=json", kill_on_drop: false }` [INFO] [stdout] f36191c1549b53cbf45ce40740ac57d9bd42113dce8177fe0d5bed91be334686 [INFO] running `Command { std: "docker" "start" "-a" "f36191c1549b53cbf45ce40740ac57d9bd42113dce8177fe0d5bed91be334686", kill_on_drop: false }` [INFO] [stderr] Checking rsicv_emulator v0.1.0 (/opt/rustwide/workdir) [INFO] [stdout] warning: enum `Type` is never used [INFO] [stdout] --> src/main.rs:89:6 [INFO] [stdout] | [INFO] [stdout] 89 | enum Type { [INFO] [stdout] | ^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `#[warn(dead_code)]` (part of `#[warn(unused)]`) on by default [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: method `decode` is never used [INFO] [stdout] --> src/main.rs:99:8 [INFO] [stdout] | [INFO] [stdout] 98 | impl Type { [INFO] [stdout] | --------- method in this implementation [INFO] [stdout] 99 | fn decode(&self, inst: u32) -> Instruction { [INFO] [stdout] | ^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: enum `Instruction` is never used [INFO] [stdout] --> src/main.rs:309:6 [INFO] [stdout] | [INFO] [stdout] 309 | enum Instruction { [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: function `decode` is never used [INFO] [stdout] --> src/main.rs:380:4 [INFO] [stdout] | [INFO] [stdout] 380 | fn decode(inst: u32) -> Instruction { [INFO] [stdout] | ^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: constant `OPCODE_TABLE` is never used [INFO] [stdout] --> src/main.rs:389:7 [INFO] [stdout] | [INFO] [stdout] 389 | const OPCODE_TABLE:[Option; 128] = [ [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:312:11 [INFO] [stdout] | [INFO] [stdout] 312 | Addiw{rd: Register, rs1: Register, imm: i32}, [INFO] [stdout] | ----- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] = note: `#[warn(dead_code)]` (part of `#[warn(unused)]`) on by default [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read [INFO] [stdout] --> src/main.rs:313:11 [INFO] [stdout] | [INFO] [stdout] 313 | Slliw{rd: Register, rs1: Register, shamt: u32}, [INFO] [stdout] | ----- ^^ ^^^ ^^^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read [INFO] [stdout] --> src/main.rs:314:11 [INFO] [stdout] | [INFO] [stdout] 314 | Srliw{rd: Register, rs1: Register, shamt: u32}, [INFO] [stdout] | ----- ^^ ^^^ ^^^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read [INFO] [stdout] --> src/main.rs:315:11 [INFO] [stdout] | [INFO] [stdout] 315 | Sraiw{rd: Register, rs1: Register, shamt: u32}, [INFO] [stdout] | ----- ^^ ^^^ ^^^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:317:10 [INFO] [stdout] | [INFO] [stdout] 317 | Addi{rd: Register, rs1: Register, imm: i32}, [INFO] [stdout] | ---- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:318:10 [INFO] [stdout] | [INFO] [stdout] 318 | Slti{rd: Register, rs1: Register, imm: i32}, [INFO] [stdout] | ---- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:319:11 [INFO] [stdout] | [INFO] [stdout] 319 | Sltiu{rd: Register, rs1: Register, imm: i32}, [INFO] [stdout] | ----- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:320:10 [INFO] [stdout] | [INFO] [stdout] 320 | Xori{rd: Register, rs1: Register, imm: i32}, [INFO] [stdout] | ---- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:321:9 [INFO] [stdout] | [INFO] [stdout] 321 | Ori{rd: Register, rs1: Register, imm: i32}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:322:10 [INFO] [stdout] | [INFO] [stdout] 322 | Andi{rd: Register, rs1: Register, imm: i32}, [INFO] [stdout] | ---- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read [INFO] [stdout] --> src/main.rs:324:10 [INFO] [stdout] | [INFO] [stdout] 324 | Slli{rd: Register, rs1: Register, shamt: u32}, [INFO] [stdout] | ---- ^^ ^^^ ^^^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read [INFO] [stdout] --> src/main.rs:325:10 [INFO] [stdout] | [INFO] [stdout] 325 | Srli{rd: Register, rs1: Register, shamt: u32}, [INFO] [stdout] | ---- ^^ ^^^ ^^^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read [INFO] [stdout] --> src/main.rs:326:10 [INFO] [stdout] | [INFO] [stdout] 326 | Srai{rd: Register, rs1: Register, shamt: u32}, [INFO] [stdout] | ---- ^^ ^^^ ^^^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:328:10 [INFO] [stdout] | [INFO] [stdout] 328 | Lb {rd: Register, rs1:Register, imm: i32}, [INFO] [stdout] | -- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:329:10 [INFO] [stdout] | [INFO] [stdout] 329 | Lh {rd: Register, rs1:Register, imm: i32}, [INFO] [stdout] | -- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:330:10 [INFO] [stdout] | [INFO] [stdout] 330 | Lw {rd: Register, rs1:Register, imm: i32}, [INFO] [stdout] | -- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:331:10 [INFO] [stdout] | [INFO] [stdout] 331 | Lbu {rd: Register, rs1:Register, imm: i32}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:332:10 [INFO] [stdout] | [INFO] [stdout] 332 | Lhu {rd: Register, rs1:Register, imm: i32}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:333:10 [INFO] [stdout] | [INFO] [stdout] 333 | Lwu {rd: Register, rs1:Register, imm: i32}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:334:10 [INFO] [stdout] | [INFO] [stdout] 334 | Ld {rd: Register, rs1:Register, imm: i32}, [INFO] [stdout] | -- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:336:12 [INFO] [stdout] | [INFO] [stdout] 336 | Fence {rd :Register, rs1:Register, imm: i32}, [INFO] [stdout] | ----- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:338:11 [INFO] [stdout] | [INFO] [stdout] 338 | Jalr {rd :Register, rs1:Register, imm: i32}, [INFO] [stdout] | ---- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd` and `imm` are never read [INFO] [stdout] --> src/main.rs:340:12 [INFO] [stdout] | [INFO] [stdout] 340 | Auipc {rd: Register, imm: i32}, [INFO] [stdout] | ----- ^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd` and `imm` are never read [INFO] [stdout] --> src/main.rs:341:10 [INFO] [stdout] | [INFO] [stdout] 341 | Lui {rd: Register, imm: i32}, [INFO] [stdout] | --- ^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:343:8 [INFO] [stdout] | [INFO] [stdout] 343 | Sb{rs2: Register, rs1: Register, imm: i32}, [INFO] [stdout] | -- ^^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:344:8 [INFO] [stdout] | [INFO] [stdout] 344 | Sh{rs2: Register, rs1: Register, imm: i32}, [INFO] [stdout] | -- ^^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:345:8 [INFO] [stdout] | [INFO] [stdout] 345 | Sw{rs2: Register, rs1: Register, imm: i32}, [INFO] [stdout] | -- ^^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read [INFO] [stdout] --> src/main.rs:346:8 [INFO] [stdout] | [INFO] [stdout] 346 | Sd{rs2: Register, rs1: Register, imm: i32}, [INFO] [stdout] | -- ^^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:348:9 [INFO] [stdout] | [INFO] [stdout] 348 | Add{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:349:9 [INFO] [stdout] | [INFO] [stdout] 349 | Sub{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stderr] Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.11s [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:350:9 [INFO] [stdout] | [INFO] [stdout] 350 | Sll{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:351:9 [INFO] [stdout] | [INFO] [stdout] 351 | Slt{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:352:10 [INFO] [stdout] | [INFO] [stdout] 352 | Sltu{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | ---- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:353:9 [INFO] [stdout] | [INFO] [stdout] 353 | Xor{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:354:9 [INFO] [stdout] | [INFO] [stdout] 354 | Srl{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:355:9 [INFO] [stdout] | [INFO] [stdout] 355 | Sra{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:356:8 [INFO] [stdout] | [INFO] [stdout] 356 | Or{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | -- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:357:9 [INFO] [stdout] | [INFO] [stdout] 357 | And{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | --- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:360:10 [INFO] [stdout] | [INFO] [stdout] 360 | Addw{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | ---- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:361:10 [INFO] [stdout] | [INFO] [stdout] 361 | Subw{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | ---- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:362:10 [INFO] [stdout] | [INFO] [stdout] 362 | Sllw{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | ---- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:363:10 [INFO] [stdout] | [INFO] [stdout] 363 | Srlw{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | ---- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read [INFO] [stdout] --> src/main.rs:364:10 [INFO] [stdout] | [INFO] [stdout] 364 | Sraw{rd: Register, rs1: Register, rs2: Register}, [INFO] [stdout] | ---- ^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read [INFO] [stdout] --> src/main.rs:366:14 [INFO] [stdout] | [INFO] [stdout] 366 | Beq {rs1: Register,rs2: Register, imm:i32}, [INFO] [stdout] | --- ^^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read [INFO] [stdout] --> src/main.rs:367:14 [INFO] [stdout] | [INFO] [stdout] 367 | Bne {rs1: Register,rs2: Register, imm:i32}, [INFO] [stdout] | --- ^^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read [INFO] [stdout] --> src/main.rs:368:14 [INFO] [stdout] | [INFO] [stdout] 368 | Blt {rs1: Register,rs2: Register, imm:i32}, [INFO] [stdout] | --- ^^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read [INFO] [stdout] --> src/main.rs:369:14 [INFO] [stdout] | [INFO] [stdout] 369 | Bge {rs1: Register,rs2: Register, imm:i32}, [INFO] [stdout] | --- ^^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read [INFO] [stdout] --> src/main.rs:370:14 [INFO] [stdout] | [INFO] [stdout] 370 | Bltu {rs1: Register,rs2: Register, imm:i32}, [INFO] [stdout] | ---- ^^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read [INFO] [stdout] --> src/main.rs:371:14 [INFO] [stdout] | [INFO] [stdout] 371 | Bgeu {rs1: Register,rs2: Register, imm:i32}, [INFO] [stdout] | ---- ^^^ ^^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `rd` and `imm` are never read [INFO] [stdout] --> src/main.rs:373:10 [INFO] [stdout] | [INFO] [stdout] 373 | Jal {rd :Register, imm: i32}, [INFO] [stdout] | --- ^^ ^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] running `Command { std: "docker" "inspect" "f36191c1549b53cbf45ce40740ac57d9bd42113dce8177fe0d5bed91be334686", kill_on_drop: false }` [INFO] running `Command { std: "docker" "rm" "-f" "f36191c1549b53cbf45ce40740ac57d9bd42113dce8177fe0d5bed91be334686", kill_on_drop: false }` [INFO] [stdout] f36191c1549b53cbf45ce40740ac57d9bd42113dce8177fe0d5bed91be334686