[INFO] cloning repository https://github.com/Ubiquitous-Adventure/gameboy-emulator [INFO] running `Command { std: "git" "-c" "credential.helper=" "-c" "credential.helper=/workspace/cargo-home/bin/git-credential-null" "clone" "--bare" "https://github.com/Ubiquitous-Adventure/gameboy-emulator" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FUbiquitous-Adventure%2Fgameboy-emulator", kill_on_drop: false }` [INFO] [stderr] Cloning into bare repository '/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FUbiquitous-Adventure%2Fgameboy-emulator'... [INFO] running `Command { std: "git" "rev-parse" "HEAD", kill_on_drop: false }` [INFO] [stdout] ecdf7c5108dfd20e24d2717c0ec337bad09df9de [INFO] checking Ubiquitous-Adventure/gameboy-emulator/ecdf7c5108dfd20e24d2717c0ec337bad09df9de against master#ab869e094a907cc5d19b4080f22eccaf347f1f95 for pr-129604 [INFO] running `Command { std: "git" "clone" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FUbiquitous-Adventure%2Fgameboy-emulator" "/workspace/builds/worker-2-tc1/source", kill_on_drop: false }` [INFO] [stderr] Cloning into '/workspace/builds/worker-2-tc1/source'... [INFO] [stderr] done. [INFO] validating manifest of git repo https://github.com/Ubiquitous-Adventure/gameboy-emulator on toolchain ab869e094a907cc5d19b4080f22eccaf347f1f95 [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+ab869e094a907cc5d19b4080f22eccaf347f1f95" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }` [INFO] started tweaking git repo https://github.com/Ubiquitous-Adventure/gameboy-emulator [INFO] finished tweaking git repo https://github.com/Ubiquitous-Adventure/gameboy-emulator [INFO] tweaked toml for git repo https://github.com/Ubiquitous-Adventure/gameboy-emulator written to /workspace/builds/worker-2-tc1/source/Cargo.toml [INFO] crate git repo https://github.com/Ubiquitous-Adventure/gameboy-emulator already has a lockfile, it will not be regenerated [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+ab869e094a907cc5d19b4080f22eccaf347f1f95" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }` [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc1/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc1/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:923055f121b5182466d55868a8b05e67af8ba4a3a3f6bad814e953ca3cd3ac2a" "/opt/rustwide/cargo-home/bin/cargo" "+ab869e094a907cc5d19b4080f22eccaf347f1f95" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }` [INFO] [stdout] 7b1b9356fc1f8b27fab0a54779c9a16000e88cd2ad8ea482f80bf342fba2bca4 [INFO] running `Command { std: "docker" "start" "-a" "7b1b9356fc1f8b27fab0a54779c9a16000e88cd2ad8ea482f80bf342fba2bca4", kill_on_drop: false }` [INFO] running `Command { std: "docker" "inspect" "7b1b9356fc1f8b27fab0a54779c9a16000e88cd2ad8ea482f80bf342fba2bca4", kill_on_drop: false }` [INFO] running `Command { std: "docker" "rm" "-f" "7b1b9356fc1f8b27fab0a54779c9a16000e88cd2ad8ea482f80bf342fba2bca4", kill_on_drop: false }` [INFO] [stdout] 7b1b9356fc1f8b27fab0a54779c9a16000e88cd2ad8ea482f80bf342fba2bca4 [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc1/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc1/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:923055f121b5182466d55868a8b05e67af8ba4a3a3f6bad814e953ca3cd3ac2a" "/opt/rustwide/cargo-home/bin/cargo" "+ab869e094a907cc5d19b4080f22eccaf347f1f95" "check" "--frozen" "--all" "--all-targets" "--message-format=json", kill_on_drop: false }` [INFO] [stdout] e14462835885979fb971aa627f589b87153f08d263ef7204fa0047b77775b710 [INFO] running `Command { std: "docker" "start" "-a" "e14462835885979fb971aa627f589b87153f08d263ef7204fa0047b77775b710", kill_on_drop: false }` [INFO] [stderr] Checking utf8parse v0.2.1 [INFO] [stderr] Checking unicode-ident v1.0.12 [INFO] [stderr] Checking is_terminal_polyfill v1.70.0 [INFO] [stderr] Checking anstyle v1.0.7 [INFO] [stderr] Checking colorchoice v1.0.1 [INFO] [stderr] Checking anstyle-query v1.1.0 [INFO] [stderr] Compiling syn v2.0.66 [INFO] [stderr] Checking strsim v0.11.1 [INFO] [stderr] Compiling anstyle-parse v0.2.4 [INFO] [stderr] Checking clap_lex v0.7.0 [INFO] [stderr] Compiling proc-macro2 v1.0.85 [INFO] [stderr] Checking either v1.13.0 [INFO] [stderr] Checking anstream v0.6.14 [INFO] [stderr] Compiling itertools v0.13.0 [INFO] [stderr] Checking clap_builder v4.5.2 [INFO] [stderr] Checking quote v1.0.36 [INFO] [stderr] Compiling clap_derive v4.5.4 [INFO] [stderr] Compiling thiserror-impl v1.0.61 [INFO] [stderr] Checking thiserror v1.0.61 [INFO] [stderr] Checking clap v4.5.4 [INFO] [stderr] Compiling gameboy-emulator v0.1.0 (/opt/rustwide/workdir) [INFO] [stdout] warning: multiple variants are never constructed [INFO] [stdout] --> src/instructions.rs:3:5 [INFO] [stdout] | [INFO] [stdout] 2 | pub enum R8Operand { [INFO] [stdout] | --------- variants in this enum [INFO] [stdout] 3 | AReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 4 | BReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 5 | CReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 6 | DReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 7 | EReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 8 | HReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 9 | LReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 10 | HLAddr, [INFO] [stdout] | ^^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `R8Operand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] = note: `#[warn(dead_code)]` on by default [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: variants `BCReg`, `DEReg`, `HLReg`, and `SP` are never constructed [INFO] [stdout] --> src/instructions.rs:15:5 [INFO] [stdout] | [INFO] [stdout] 14 | pub enum R16Operand { [INFO] [stdout] | ---------- variants in this enum [INFO] [stdout] 15 | BCReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 16 | DEReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 17 | HLReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 18 | SP, [INFO] [stdout] | ^^ [INFO] [stdout] | [INFO] [stdout] = note: `R16Operand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: variants `BCReg`, `DEReg`, `HLReg`, and `AFReg` are never constructed [INFO] [stdout] --> src/instructions.rs:23:5 [INFO] [stdout] | [INFO] [stdout] 22 | pub enum R16StkOperand { [INFO] [stdout] | ------------- variants in this enum [INFO] [stdout] 23 | BCReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 24 | DEReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 25 | HLReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 26 | AFReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `R16StkOperand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: variants `BCReg`, `DEReg`, `HLRegAndInc`, and `HLRegAndDec` are never constructed [INFO] [stdout] --> src/instructions.rs:31:5 [INFO] [stdout] | [INFO] [stdout] 30 | pub enum R16MemOperand { [INFO] [stdout] | ------------- variants in this enum [INFO] [stdout] 31 | BCReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 32 | DEReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 33 | HLRegAndInc, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 34 | HLRegAndDec, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `R16MemOperand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: variants `NZ`, `Z`, `NC`, and `C` are never constructed [INFO] [stdout] --> src/instructions.rs:39:5 [INFO] [stdout] | [INFO] [stdout] 38 | pub enum CondOperand { [INFO] [stdout] | ----------- variants in this enum [INFO] [stdout] 39 | NZ, [INFO] [stdout] | ^^ [INFO] [stdout] 40 | Z, [INFO] [stdout] | ^ [INFO] [stdout] 41 | NC, [INFO] [stdout] | ^^ [INFO] [stdout] 42 | C, [INFO] [stdout] | ^ [INFO] [stdout] | [INFO] [stdout] = note: `CondOperand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: multiple variants are never constructed [INFO] [stdout] --> src/instructions.rs:47:5 [INFO] [stdout] | [INFO] [stdout] 46 | pub enum U3Operand { [INFO] [stdout] | --------- variants in this enum [INFO] [stdout] 47 | Zero = 0, [INFO] [stdout] | ^^^^ [INFO] [stdout] 48 | One = 1, [INFO] [stdout] | ^^^ [INFO] [stdout] 49 | Two = 2, [INFO] [stdout] | ^^^ [INFO] [stdout] 50 | Three = 3, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 51 | Four = 4, [INFO] [stdout] | ^^^^ [INFO] [stdout] 52 | Five = 5, [INFO] [stdout] | ^^^^ [INFO] [stdout] 53 | Six = 6, [INFO] [stdout] | ^^^ [INFO] [stdout] 54 | Seven = 7, [INFO] [stdout] | ^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `U3Operand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: multiple variants are never constructed [INFO] [stdout] --> src/instructions.rs:62:5 [INFO] [stdout] | [INFO] [stdout] 58 | pub enum Instruction { [INFO] [stdout] | ----------- variants in this enum [INFO] [stdout] ... [INFO] [stdout] 62 | LoadImm16 { dst: R16Operand, imm: u16 }, [INFO] [stdout] | ^^^^^^^^^ [INFO] [stdout] 63 | /// ld [r16mem], a - store 8-bit value from A register into byte pointed to by 16-bit register [INFO] [stdout] 64 | StoreARegToMem { dst: R16MemOperand }, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 65 | /// ld a, [r16mem] - load 8-bit value from byte pointed to by 16-bit register into A register [INFO] [stdout] 66 | LoadMemToAReg { dst: R16MemOperand }, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 67 | /// ld [imm16], sp - store 16-bit stack pointer into the two bytes pointed to by immediate [INFO] [stdout] 68 | StoreSPToImmMem { dst: u16 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 69 | /// inc r16 - increment 16-bit register [INFO] [stdout] 70 | IncR16 { reg: R16Operand }, [INFO] [stdout] | ^^^^^^ [INFO] [stdout] 71 | /// dec r16 - decrement 16-bit register [INFO] [stdout] 72 | DecR16 { reg: R16Operand }, [INFO] [stdout] | ^^^^^^ [INFO] [stdout] 73 | /// add hl, r16 - add value from 16-bit register to HL register [INFO] [stdout] 74 | AddToHLReg { reg: R16Operand }, [INFO] [stdout] | ^^^^^^^^^^ [INFO] [stdout] 75 | /// inc r8 - increment 8-bit register [INFO] [stdout] 76 | IncR8 { reg: R8Operand }, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 77 | /// dec r8 - decrement 8-bit register [INFO] [stdout] 78 | DecR8 { reg: R8Operand }, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 79 | /// ld r8, imm8 - load 8-bit immediate into 8-bit register [INFO] [stdout] 80 | LoadImm8 { dst: R8Operand, imm: u8 }, [INFO] [stdout] | ^^^^^^^^ [INFO] [stdout] 81 | /// rlca - rotate A register left [INFO] [stdout] 82 | RotARegLeftSetC, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 83 | /// rrca - rotate A register left [INFO] [stdout] 84 | RotARegRightSetC, [INFO] [stdout] | ^^^^^^^^^^^^^^^^ [INFO] [stdout] 85 | /// rla - rotate A register left through the carry floag [INFO] [stdout] 86 | RotARegLeftThroughC, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 87 | /// rra - rotate A register right through the carry floag [INFO] [stdout] 88 | RotARegRightThroughC, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 89 | /// daa - decimal adjust accumulator to get correct BCD representation [INFO] [stdout] 90 | DecAdjAccum, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 91 | /// cpl - invert A register [INFO] [stdout] 92 | InvA, [INFO] [stdout] | ^^^^ [INFO] [stdout] 93 | /// scf - set carry flag [INFO] [stdout] 94 | SetC, [INFO] [stdout] | ^^^^ [INFO] [stdout] 95 | /// ccf - invert carry flag [INFO] [stdout] 96 | InvC, [INFO] [stdout] | ^^^^ [INFO] [stdout] 97 | /// jr imm16 - jump to address with signed 16-bit immediate offset [INFO] [stdout] 98 | JumpRelativeImm { imm: i8 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 99 | /// jr cond, imm16 - jump to address with signed 16-bit immediate offset if condition is met [INFO] [stdout] 100 | JumpRelativeImmUnderCond { imm: i8 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 101 | /// stop - do nothing but is (often) considered a two-byte instruction [INFO] [stdout] 102 | Stop, [INFO] [stdout] | ^^^^ [INFO] [stdout] 103 | /// ld r8dst, r8src - load value from 8-bit register into another 8-bit register [INFO] [stdout] 104 | LoadR8ToR8 { dst: R8Operand, src: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^ [INFO] [stdout] 105 | /// halt - enter CPU low-power mode until interrupt occurs [INFO] [stdout] 106 | Halt, [INFO] [stdout] | ^^^^ [INFO] [stdout] 107 | /// add a, r8 - add value from 8-bit register to the A register [INFO] [stdout] 108 | AddRegToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 109 | /// adc a, r8 - add value from 8-bit register plus the carry flag to the A register [INFO] [stdout] 110 | AddRegCToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 111 | /// sub a, r8 - subtract 8-bit register from the A register [INFO] [stdout] 112 | SubRegFromAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 113 | /// sbc a, r8 - subtract 8-bit register and the carry flag from the A register [INFO] [stdout] 114 | SubRegCFromAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 115 | /// and a, r8 - bitwise and between 8-bit register and the A register [INFO] [stdout] 116 | AndRegToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 117 | /// xor a, r8 - bitwise xor between 8-bit register and the A register [INFO] [stdout] 118 | XorRegToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 119 | /// or a, r8 - bitwise or between 8-bit register and the A register [INFO] [stdout] 120 | OrRegToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 121 | /// cp a, r8 - compare 8-bit register and A register by substracting and setting flags [INFO] [stdout] 122 | CmpRegToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 123 | /// add a, imm8 - add 8-bit immediate to the A register [INFO] [stdout] 124 | AddImmToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 125 | /// adc a, imm8 - add 8-bit immediate plus the carry flag to the A register [INFO] [stdout] 126 | AddImmCToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 127 | /// sub a, imm8 - subtract 8-bit immediate from the A register [INFO] [stdout] 128 | SubImmFromAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 129 | /// sbc a, imm8 - subtract 8-bit immediate and the carry flag from the A register [INFO] [stdout] 130 | SubImmCFromAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 131 | /// and a, imm8 - bitwise and between 8-bit register and the A register [INFO] [stdout] 132 | AndImmToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 133 | /// xor a, imm8 - bitwise xor between 8-bit register and the A register [INFO] [stdout] 134 | XorImmToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 135 | /// or a, imm8 - bitwise or between 8-bit register and the A register [INFO] [stdout] 136 | OrImmToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 137 | /// cp a, imm8 - compare 8-bit register and 8-bit immediate by substracting and setting flags [INFO] [stdout] 138 | CmpImmToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 139 | /// ret cond - return from subroutine if condition is met [INFO] [stdout] 140 | RetUnderCond, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 141 | /// ret - return from subroutine (Pop PC) [INFO] [stdout] 142 | Ret, [INFO] [stdout] | ^^^ [INFO] [stdout] 143 | /// reti - return from subroutine and enable interrupts [INFO] [stdout] 144 | RetInterrupts, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 145 | /// jp cond, imm16 - jump to 16-bit immediate address if condition is met [INFO] [stdout] 146 | JumpImmUnderCond, [INFO] [stdout] | ^^^^^^^^^^^^^^^^ [INFO] [stdout] 147 | /// jp imm16 - jump to 16-bit immediate address [INFO] [stdout] 148 | JumpImm, [INFO] [stdout] | ^^^^^^^ [INFO] [stdout] 149 | /// jp hl - jump to 16-bit address stored in HL register [INFO] [stdout] 150 | JumpHL, [INFO] [stdout] | ^^^^^^ [INFO] [stdout] 151 | /// call cond, imm16 - call 16-bit immediate if condition is met [INFO] [stdout] 152 | CallImmUnderCond { cond: CondOperand, imm: u16 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^ [INFO] [stdout] 153 | /// call imm16 - call 16-bit immediate address [INFO] [stdout] 154 | CallImm { imm: u16 }, [INFO] [stdout] | ^^^^^^^ [INFO] [stdout] 155 | /// rst tgt3 - call address tgt3 * 8 [INFO] [stdout] 156 | CallRst { target: U3Operand }, [INFO] [stdout] | ^^^^^^^ [INFO] [stdout] 157 | /// pop r16stk - pop 16-bit register from the stack [INFO] [stdout] 158 | Pop { reg: R16Operand }, [INFO] [stdout] | ^^^ [INFO] [stdout] 159 | /// push r16stk - push 16-bit register to the stack [INFO] [stdout] 160 | Push { reg: R16Operand }, [INFO] [stdout] | ^^^^ [INFO] [stdout] 161 | /// ldh [c], a - store 8-bit value from A register to memory at 0xFF00 + C [INFO] [stdout] 162 | StoreARegToCMem, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 163 | /// ldh [imm8], a - store 8-bit value from A register to memory at 0xFF00 + 8-bit immediate [INFO] [stdout] 164 | StoreARegToImm8Mem { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 165 | /// ld [imm16], a - store 8-bit value from A register to memory pointed to by 16-bit immediate [INFO] [stdout] 166 | StoreARegToImm16Mem { imm: u16 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 167 | /// ldh a, [c] - load 8-bit value from 0xFF00 + C into A register [INFO] [stdout] 168 | LoadCMemToAReg, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 169 | /// ldh a, [imm8] - load 8-bit value from 0xFF00 + 8-bit immediate into A register [INFO] [stdout] 170 | LoadImm8MemToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^ [INFO] [stdout] 171 | /// ld a, [imm16] - load 8-bit value from memory at 16-bit immediate address into A register [INFO] [stdout] 172 | LoadImm16MemToAReg { imm: u16 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 173 | /// add sp, imm8 - add a signed 8-bit immediate to the stack pointer [INFO] [stdout] 174 | AddImmToSP { imm: i8 }, [INFO] [stdout] | ^^^^^^^^^^ [INFO] [stdout] 175 | /// ld hl, sp + imm8 - add signed 8-bit immediate to the stack pointer and save in HL [INFO] [stdout] 176 | LoadSPWithImmToHLReg { imm: i8 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 177 | /// ld sp, hl - load 16-bit register from HL register into stack pointer [INFO] [stdout] 178 | LoadHLRegToSP, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 179 | /// di - disable interrupts by clearing the IME flag [INFO] [stdout] 180 | DisableInterrupts, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^ [INFO] [stdout] 181 | /// ei - enable interrupts by setting the IME flag [INFO] [stdout] 182 | EnableInterrupts, [INFO] [stdout] | ^^^^^^^^^^^^^^^^ [INFO] [stdout] 183 | /// rlc r8 - rotate 8-bit register left [INFO] [stdout] 184 | RotR8LeftSetC, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 185 | /// rrc r8 - rotate 8-bit register right [INFO] [stdout] 186 | RotR8RightSetC, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 187 | /// rl r8 - rotate 8-bit register left through the carry flag [INFO] [stdout] 188 | RotR8LeftThroughC, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^ [INFO] [stdout] 189 | /// rr r8 - rotate 8-bit register right through the carry flag [INFO] [stdout] 190 | RotR8RightThroughC, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 191 | /// sla r8 - arithmetically shift left 8-bit register [INFO] [stdout] 192 | ShiftLeftArith { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 193 | /// sra r8 - arithmetically shift right 8-bit register [INFO] [stdout] 194 | ShiftRightArith { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 195 | /// swap r8 - swap the upper 4 bits in 8-bit register with the lower 4 bits [INFO] [stdout] 196 | SwapHighLowR8 { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 197 | /// srl r8 - logically shift right 8-bit register [INFO] [stdout] 198 | ShiftLeftLogic { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 199 | /// bit b3, r8 - test b3-th bit in 8-bit register [INFO] [stdout] 200 | TestBit { bit_num: U3Operand, reg: R8Operand }, [INFO] [stdout] | ^^^^^^^ [INFO] [stdout] 201 | /// res b3, r8 - set b3-th bit in 8-bit register to zero [INFO] [stdout] 202 | SetBitZero { bit_num: U3Operand, reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^ [INFO] [stdout] 203 | /// set b3, r8 - set b3-th bit in 8-bit register to one [INFO] [stdout] 204 | SetBitOne { bit_num: U3Operand, reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: enum `FlagKind` is never used [INFO] [stdout] --> src/registers.rs:2:6 [INFO] [stdout] | [INFO] [stdout] 2 | enum FlagKind { [INFO] [stdout] | ^^^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: enum `R8Kind` is never used [INFO] [stdout] --> src/registers.rs:10:6 [INFO] [stdout] | [INFO] [stdout] 10 | enum R8Kind { [INFO] [stdout] | ^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: enum `R16Kind` is never used [INFO] [stdout] --> src/registers.rs:21:6 [INFO] [stdout] | [INFO] [stdout] 21 | enum R16Kind { [INFO] [stdout] | ^^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: constant `MOST_SIGNIFICANT_BYTE` is never used [INFO] [stdout] --> src/registers.rs:30:7 [INFO] [stdout] | [INFO] [stdout] 30 | const MOST_SIGNIFICANT_BYTE: usize = 1; [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: constant `LEAST_SIGNIFICANT_BYTE` is never used [INFO] [stdout] --> src/registers.rs:31:7 [INFO] [stdout] | [INFO] [stdout] 31 | const LEAST_SIGNIFICANT_BYTE: usize = 0; [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: struct `Registers` is never constructed [INFO] [stdout] --> src/registers.rs:34:8 [INFO] [stdout] | [INFO] [stdout] 34 | struct Registers { [INFO] [stdout] | ^^^^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: multiple associated items are never used [INFO] [stdout] --> src/registers.rs:49:12 [INFO] [stdout] | [INFO] [stdout] 48 | impl Registers { [INFO] [stdout] | -------------- associated items in this implementation [INFO] [stdout] 49 | pub fn new() -> Self { [INFO] [stdout] | ^^^ [INFO] [stdout] ... [INFO] [stdout] 59 | pub fn get_flag(&self, flag_kind: FlagKind) -> bool { [INFO] [stdout] | ^^^^^^^^ [INFO] [stdout] ... [INFO] [stdout] 70 | pub fn set_flag(&mut self, flag_kind: FlagKind, value: bool) { [INFO] [stdout] | ^^^^^^^^ [INFO] [stdout] ... [INFO] [stdout] 85 | pub fn get_r8(&self, r8kind: R8Kind) -> u8 { [INFO] [stdout] | ^^^^^^ [INFO] [stdout] ... [INFO] [stdout] 97 | pub fn get_mut_r8(&mut self, r8kind: R8Kind) -> &mut u8 { [INFO] [stdout] | ^^^^^^^^^^ [INFO] [stdout] ... [INFO] [stdout] 109 | pub fn get_r16(&self, r16kind: R16Kind) -> u16 { [INFO] [stdout] | ^^^^^^^ [INFO] [stdout] ... [INFO] [stdout] 124 | pub fn get_mut_r16(&mut self, r16kind: R16Kind) -> &mut u16 { [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: 14 warnings emitted [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: multiple variants are never constructed [INFO] [stdout] --> src/instructions.rs:3:5 [INFO] [stdout] | [INFO] [stdout] 2 | pub enum R8Operand { [INFO] [stdout] | --------- variants in this enum [INFO] [stdout] 3 | AReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 4 | BReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 5 | CReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 6 | DReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 7 | EReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 8 | HReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 9 | LReg, [INFO] [stdout] | ^^^^ [INFO] [stdout] 10 | HLAddr, [INFO] [stdout] | ^^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `R8Operand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] = note: `#[warn(dead_code)]` on by default [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: variants `BCReg`, `DEReg`, `HLReg`, and `SP` are never constructed [INFO] [stdout] --> src/instructions.rs:15:5 [INFO] [stdout] | [INFO] [stdout] 14 | pub enum R16Operand { [INFO] [stdout] | ---------- variants in this enum [INFO] [stdout] 15 | BCReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 16 | DEReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 17 | HLReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 18 | SP, [INFO] [stdout] | ^^ [INFO] [stdout] | [INFO] [stdout] = note: `R16Operand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: variants `BCReg`, `DEReg`, `HLReg`, and `AFReg` are never constructed [INFO] [stdout] --> src/instructions.rs:23:5 [INFO] [stdout] | [INFO] [stdout] 22 | pub enum R16StkOperand { [INFO] [stdout] | ------------- variants in this enum [INFO] [stdout] 23 | BCReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 24 | DEReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 25 | HLReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 26 | AFReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `R16StkOperand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: variants `BCReg`, `DEReg`, `HLRegAndInc`, and `HLRegAndDec` are never constructed [INFO] [stdout] --> src/instructions.rs:31:5 [INFO] [stdout] | [INFO] [stdout] 30 | pub enum R16MemOperand { [INFO] [stdout] | ------------- variants in this enum [INFO] [stdout] 31 | BCReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 32 | DEReg, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 33 | HLRegAndInc, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 34 | HLRegAndDec, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `R16MemOperand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: variants `NZ`, `Z`, `NC`, and `C` are never constructed [INFO] [stdout] --> src/instructions.rs:39:5 [INFO] [stdout] | [INFO] [stdout] 38 | pub enum CondOperand { [INFO] [stdout] | ----------- variants in this enum [INFO] [stdout] 39 | NZ, [INFO] [stdout] | ^^ [INFO] [stdout] 40 | Z, [INFO] [stdout] | ^ [INFO] [stdout] 41 | NC, [INFO] [stdout] | ^^ [INFO] [stdout] 42 | C, [INFO] [stdout] | ^ [INFO] [stdout] | [INFO] [stdout] = note: `CondOperand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: multiple variants are never constructed [INFO] [stdout] --> src/instructions.rs:47:5 [INFO] [stdout] | [INFO] [stdout] 46 | pub enum U3Operand { [INFO] [stdout] | --------- variants in this enum [INFO] [stdout] 47 | Zero = 0, [INFO] [stdout] | ^^^^ [INFO] [stdout] 48 | One = 1, [INFO] [stdout] | ^^^ [INFO] [stdout] 49 | Two = 2, [INFO] [stdout] | ^^^ [INFO] [stdout] 50 | Three = 3, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 51 | Four = 4, [INFO] [stdout] | ^^^^ [INFO] [stdout] 52 | Five = 5, [INFO] [stdout] | ^^^^ [INFO] [stdout] 53 | Six = 6, [INFO] [stdout] | ^^^ [INFO] [stdout] 54 | Seven = 7, [INFO] [stdout] | ^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `U3Operand` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: multiple variants are never constructed [INFO] [stdout] --> src/instructions.rs:62:5 [INFO] [stdout] | [INFO] [stdout] 58 | pub enum Instruction { [INFO] [stdout] | ----------- variants in this enum [INFO] [stdout] ... [INFO] [stdout] 62 | LoadImm16 { dst: R16Operand, imm: u16 }, [INFO] [stdout] | ^^^^^^^^^ [INFO] [stdout] 63 | /// ld [r16mem], a - store 8-bit value from A register into byte pointed to by 16-bit register [INFO] [stdout] 64 | StoreARegToMem { dst: R16MemOperand }, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 65 | /// ld a, [r16mem] - load 8-bit value from byte pointed to by 16-bit register into A register [INFO] [stdout] 66 | LoadMemToAReg { dst: R16MemOperand }, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 67 | /// ld [imm16], sp - store 16-bit stack pointer into the two bytes pointed to by immediate [INFO] [stdout] 68 | StoreSPToImmMem { dst: u16 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 69 | /// inc r16 - increment 16-bit register [INFO] [stdout] 70 | IncR16 { reg: R16Operand }, [INFO] [stdout] | ^^^^^^ [INFO] [stdout] 71 | /// dec r16 - decrement 16-bit register [INFO] [stdout] 72 | DecR16 { reg: R16Operand }, [INFO] [stdout] | ^^^^^^ [INFO] [stdout] 73 | /// add hl, r16 - add value from 16-bit register to HL register [INFO] [stdout] 74 | AddToHLReg { reg: R16Operand }, [INFO] [stdout] | ^^^^^^^^^^ [INFO] [stdout] 75 | /// inc r8 - increment 8-bit register [INFO] [stdout] 76 | IncR8 { reg: R8Operand }, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 77 | /// dec r8 - decrement 8-bit register [INFO] [stdout] 78 | DecR8 { reg: R8Operand }, [INFO] [stdout] | ^^^^^ [INFO] [stdout] 79 | /// ld r8, imm8 - load 8-bit immediate into 8-bit register [INFO] [stdout] 80 | LoadImm8 { dst: R8Operand, imm: u8 }, [INFO] [stdout] | ^^^^^^^^ [INFO] [stdout] 81 | /// rlca - rotate A register left [INFO] [stdout] 82 | RotARegLeftSetC, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 83 | /// rrca - rotate A register left [INFO] [stdout] 84 | RotARegRightSetC, [INFO] [stdout] | ^^^^^^^^^^^^^^^^ [INFO] [stdout] 85 | /// rla - rotate A register left through the carry floag [INFO] [stdout] 86 | RotARegLeftThroughC, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 87 | /// rra - rotate A register right through the carry floag [INFO] [stdout] 88 | RotARegRightThroughC, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 89 | /// daa - decimal adjust accumulator to get correct BCD representation [INFO] [stdout] 90 | DecAdjAccum, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 91 | /// cpl - invert A register [INFO] [stdout] 92 | InvA, [INFO] [stdout] | ^^^^ [INFO] [stdout] 93 | /// scf - set carry flag [INFO] [stdout] 94 | SetC, [INFO] [stdout] | ^^^^ [INFO] [stdout] 95 | /// ccf - invert carry flag [INFO] [stdout] 96 | InvC, [INFO] [stdout] | ^^^^ [INFO] [stdout] 97 | /// jr imm16 - jump to address with signed 16-bit immediate offset [INFO] [stdout] 98 | JumpRelativeImm { imm: i8 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 99 | /// jr cond, imm16 - jump to address with signed 16-bit immediate offset if condition is met [INFO] [stdout] 100 | JumpRelativeImmUnderCond { imm: i8 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 101 | /// stop - do nothing but is (often) considered a two-byte instruction [INFO] [stdout] 102 | Stop, [INFO] [stdout] | ^^^^ [INFO] [stdout] 103 | /// ld r8dst, r8src - load value from 8-bit register into another 8-bit register [INFO] [stdout] 104 | LoadR8ToR8 { dst: R8Operand, src: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^ [INFO] [stdout] 105 | /// halt - enter CPU low-power mode until interrupt occurs [INFO] [stdout] 106 | Halt, [INFO] [stdout] | ^^^^ [INFO] [stdout] 107 | /// add a, r8 - add value from 8-bit register to the A register [INFO] [stdout] 108 | AddRegToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 109 | /// adc a, r8 - add value from 8-bit register plus the carry flag to the A register [INFO] [stdout] 110 | AddRegCToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 111 | /// sub a, r8 - subtract 8-bit register from the A register [INFO] [stdout] 112 | SubRegFromAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 113 | /// sbc a, r8 - subtract 8-bit register and the carry flag from the A register [INFO] [stdout] 114 | SubRegCFromAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 115 | /// and a, r8 - bitwise and between 8-bit register and the A register [INFO] [stdout] 116 | AndRegToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 117 | /// xor a, r8 - bitwise xor between 8-bit register and the A register [INFO] [stdout] 118 | XorRegToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 119 | /// or a, r8 - bitwise or between 8-bit register and the A register [INFO] [stdout] 120 | OrRegToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 121 | /// cp a, r8 - compare 8-bit register and A register by substracting and setting flags [INFO] [stdout] 122 | CmpRegToAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 123 | /// add a, imm8 - add 8-bit immediate to the A register [INFO] [stdout] 124 | AddImmToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 125 | /// adc a, imm8 - add 8-bit immediate plus the carry flag to the A register [INFO] [stdout] 126 | AddImmCToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 127 | /// sub a, imm8 - subtract 8-bit immediate from the A register [INFO] [stdout] 128 | SubImmFromAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 129 | /// sbc a, imm8 - subtract 8-bit immediate and the carry flag from the A register [INFO] [stdout] 130 | SubImmCFromAReg { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 131 | /// and a, imm8 - bitwise and between 8-bit register and the A register [INFO] [stdout] 132 | AndImmToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 133 | /// xor a, imm8 - bitwise xor between 8-bit register and the A register [INFO] [stdout] 134 | XorImmToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 135 | /// or a, imm8 - bitwise or between 8-bit register and the A register [INFO] [stdout] 136 | OrImmToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 137 | /// cp a, imm8 - compare 8-bit register and 8-bit immediate by substracting and setting flags [INFO] [stdout] 138 | CmpImmToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 139 | /// ret cond - return from subroutine if condition is met [INFO] [stdout] 140 | RetUnderCond, [INFO] [stdout] | ^^^^^^^^^^^^ [INFO] [stdout] 141 | /// ret - return from subroutine (Pop PC) [INFO] [stdout] 142 | Ret, [INFO] [stdout] | ^^^ [INFO] [stdout] 143 | /// reti - return from subroutine and enable interrupts [INFO] [stdout] 144 | RetInterrupts, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 145 | /// jp cond, imm16 - jump to 16-bit immediate address if condition is met [INFO] [stdout] 146 | JumpImmUnderCond, [INFO] [stdout] | ^^^^^^^^^^^^^^^^ [INFO] [stdout] 147 | /// jp imm16 - jump to 16-bit immediate address [INFO] [stdout] 148 | JumpImm, [INFO] [stdout] | ^^^^^^^ [INFO] [stdout] 149 | /// jp hl - jump to 16-bit address stored in HL register [INFO] [stdout] 150 | JumpHL, [INFO] [stdout] | ^^^^^^ [INFO] [stdout] 151 | /// call cond, imm16 - call 16-bit immediate if condition is met [INFO] [stdout] 152 | CallImmUnderCond { cond: CondOperand, imm: u16 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^ [INFO] [stdout] 153 | /// call imm16 - call 16-bit immediate address [INFO] [stdout] 154 | CallImm { imm: u16 }, [INFO] [stdout] | ^^^^^^^ [INFO] [stdout] 155 | /// rst tgt3 - call address tgt3 * 8 [INFO] [stdout] 156 | CallRst { target: U3Operand }, [INFO] [stdout] | ^^^^^^^ [INFO] [stdout] 157 | /// pop r16stk - pop 16-bit register from the stack [INFO] [stdout] 158 | Pop { reg: R16Operand }, [INFO] [stdout] | ^^^ [INFO] [stdout] 159 | /// push r16stk - push 16-bit register to the stack [INFO] [stdout] 160 | Push { reg: R16Operand }, [INFO] [stdout] | ^^^^ [INFO] [stdout] 161 | /// ldh [c], a - store 8-bit value from A register to memory at 0xFF00 + C [INFO] [stdout] 162 | StoreARegToCMem, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 163 | /// ldh [imm8], a - store 8-bit value from A register to memory at 0xFF00 + 8-bit immediate [INFO] [stdout] 164 | StoreARegToImm8Mem { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 165 | /// ld [imm16], a - store 8-bit value from A register to memory pointed to by 16-bit immediate [INFO] [stdout] 166 | StoreARegToImm16Mem { imm: u16 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 167 | /// ldh a, [c] - load 8-bit value from 0xFF00 + C into A register [INFO] [stdout] 168 | LoadCMemToAReg, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 169 | /// ldh a, [imm8] - load 8-bit value from 0xFF00 + 8-bit immediate into A register [INFO] [stdout] 170 | LoadImm8MemToAReg { imm: u8 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^ [INFO] [stdout] 171 | /// ld a, [imm16] - load 8-bit value from memory at 16-bit immediate address into A register [INFO] [stdout] 172 | LoadImm16MemToAReg { imm: u16 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 173 | /// add sp, imm8 - add a signed 8-bit immediate to the stack pointer [INFO] [stdout] 174 | AddImmToSP { imm: i8 }, [INFO] [stdout] | ^^^^^^^^^^ [INFO] [stdout] 175 | /// ld hl, sp + imm8 - add signed 8-bit immediate to the stack pointer and save in HL [INFO] [stdout] 176 | LoadSPWithImmToHLReg { imm: i8 }, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 177 | /// ld sp, hl - load 16-bit register from HL register into stack pointer [INFO] [stdout] 178 | LoadHLRegToSP, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 179 | /// di - disable interrupts by clearing the IME flag [INFO] [stdout] 180 | DisableInterrupts, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^ [INFO] [stdout] 181 | /// ei - enable interrupts by setting the IME flag [INFO] [stdout] 182 | EnableInterrupts, [INFO] [stdout] | ^^^^^^^^^^^^^^^^ [INFO] [stdout] 183 | /// rlc r8 - rotate 8-bit register left [INFO] [stdout] 184 | RotR8LeftSetC, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 185 | /// rrc r8 - rotate 8-bit register right [INFO] [stdout] 186 | RotR8RightSetC, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 187 | /// rl r8 - rotate 8-bit register left through the carry flag [INFO] [stdout] 188 | RotR8LeftThroughC, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^ [INFO] [stdout] 189 | /// rr r8 - rotate 8-bit register right through the carry flag [INFO] [stdout] 190 | RotR8RightThroughC, [INFO] [stdout] | ^^^^^^^^^^^^^^^^^^ [INFO] [stdout] 191 | /// sla r8 - arithmetically shift left 8-bit register [INFO] [stdout] 192 | ShiftLeftArith { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 193 | /// sra r8 - arithmetically shift right 8-bit register [INFO] [stdout] 194 | ShiftRightArith { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^^ [INFO] [stdout] 195 | /// swap r8 - swap the upper 4 bits in 8-bit register with the lower 4 bits [INFO] [stdout] 196 | SwapHighLowR8 { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^ [INFO] [stdout] 197 | /// srl r8 - logically shift right 8-bit register [INFO] [stdout] 198 | ShiftLeftLogic { reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^^^^^ [INFO] [stdout] 199 | /// bit b3, r8 - test b3-th bit in 8-bit register [INFO] [stdout] 200 | TestBit { bit_num: U3Operand, reg: R8Operand }, [INFO] [stdout] | ^^^^^^^ [INFO] [stdout] 201 | /// res b3, r8 - set b3-th bit in 8-bit register to zero [INFO] [stdout] 202 | SetBitZero { bit_num: U3Operand, reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^^ [INFO] [stdout] 203 | /// set b3, r8 - set b3-th bit in 8-bit register to one [INFO] [stdout] 204 | SetBitOne { bit_num: U3Operand, reg: R8Operand }, [INFO] [stdout] | ^^^^^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `Instruction` has derived impls for the traits `Clone` and `Debug`, but these are intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: method `set_flag` is never used [INFO] [stdout] --> src/registers.rs:70:12 [INFO] [stdout] | [INFO] [stdout] 48 | impl Registers { [INFO] [stdout] | -------------- method in this implementation [INFO] [stdout] ... [INFO] [stdout] 70 | pub fn set_flag(&mut self, flag_kind: FlagKind, value: bool) { [INFO] [stdout] | ^^^^^^^^ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: 8 warnings emitted [INFO] [stdout] [INFO] [stdout] [INFO] [stderr] Finished `dev` profile [unoptimized + debuginfo] target(s) in 21.30s [INFO] running `Command { std: "docker" "inspect" "e14462835885979fb971aa627f589b87153f08d263ef7204fa0047b77775b710", kill_on_drop: false }` [INFO] running `Command { std: "docker" "rm" "-f" "e14462835885979fb971aa627f589b87153f08d263ef7204fa0047b77775b710", kill_on_drop: false }` [INFO] [stdout] e14462835885979fb971aa627f589b87153f08d263ef7204fa0047b77775b710