[INFO] cloning repository https://github.com/MelomanCool/chip-8-emulator-rust [INFO] running `Command { std: "git" "-c" "credential.helper=" "-c" "credential.helper=/workspace/cargo-home/bin/git-credential-null" "clone" "--bare" "https://github.com/MelomanCool/chip-8-emulator-rust" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FMelomanCool%2Fchip-8-emulator-rust", kill_on_drop: false }` [INFO] [stderr] Cloning into bare repository '/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FMelomanCool%2Fchip-8-emulator-rust'... [INFO] running `Command { std: "git" "rev-parse" "HEAD", kill_on_drop: false }` [INFO] [stdout] d9b2b91f82929e8f86ee093bb97a815f7bdc71fb [INFO] building MelomanCool/chip-8-emulator-rust against master#70591dc15db32941fe3595fdbf98e58d6975f95e for pr-127731 [INFO] running `Command { std: "git" "clone" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FMelomanCool%2Fchip-8-emulator-rust" "/workspace/builds/worker-5-tc1/source", kill_on_drop: false }` [INFO] [stderr] Cloning into '/workspace/builds/worker-5-tc1/source'... [INFO] [stderr] done. [INFO] validating manifest of git repo https://github.com/MelomanCool/chip-8-emulator-rust on toolchain 70591dc15db32941fe3595fdbf98e58d6975f95e [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+70591dc15db32941fe3595fdbf98e58d6975f95e" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }` [INFO] started tweaking git repo https://github.com/MelomanCool/chip-8-emulator-rust [INFO] finished tweaking git repo https://github.com/MelomanCool/chip-8-emulator-rust [INFO] tweaked toml for git repo https://github.com/MelomanCool/chip-8-emulator-rust written to /workspace/builds/worker-5-tc1/source/Cargo.toml [INFO] crate git repo https://github.com/MelomanCool/chip-8-emulator-rust already has a lockfile, it will not be regenerated [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+70591dc15db32941fe3595fdbf98e58d6975f95e" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }` [INFO] [stderr] Blocking waiting for file lock on package cache [ERROR] error running command: no output for 300 seconds [ERROR] this task or one of its parent failed! [ERROR] no output for 300 seconds [ERROR] note: run with `RUST_BACKTRACE=1` to display a backtrace. [INFO] building MelomanCool/chip-8-emulator-rust against try#7587ff3622fbec0abf6ac551eab5226f22f5d958 for pr-127731 [INFO] running `Command { std: "git" "clone" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FMelomanCool%2Fchip-8-emulator-rust" "/workspace/builds/worker-5-tc2/source", kill_on_drop: false }` [INFO] [stderr] Cloning into '/workspace/builds/worker-5-tc2/source'... [INFO] [stderr] done. [INFO] validating manifest of git repo https://github.com/MelomanCool/chip-8-emulator-rust on toolchain 7587ff3622fbec0abf6ac551eab5226f22f5d958 [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+7587ff3622fbec0abf6ac551eab5226f22f5d958" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }` [INFO] started tweaking git repo https://github.com/MelomanCool/chip-8-emulator-rust [INFO] finished tweaking git repo https://github.com/MelomanCool/chip-8-emulator-rust [INFO] tweaked toml for git repo https://github.com/MelomanCool/chip-8-emulator-rust written to /workspace/builds/worker-5-tc2/source/Cargo.toml [INFO] crate git repo https://github.com/MelomanCool/chip-8-emulator-rust already has a lockfile, it will not be regenerated [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+7587ff3622fbec0abf6ac551eab5226f22f5d958" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }` [INFO] [stderr] Blocking waiting for file lock on package cache [INFO] [stderr] Blocking waiting for file lock on package cache [ERROR] error running command: no output for 300 seconds [INFO] building MelomanCool/chip-8-emulator-rust against try#7587ff3622fbec0abf6ac551eab5226f22f5d958 for pr-127731 [INFO] running `Command { std: "git" "clone" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FMelomanCool%2Fchip-8-emulator-rust" "/workspace/builds/worker-5-tc2/source", kill_on_drop: false }` [INFO] [stderr] Cloning into '/workspace/builds/worker-5-tc2/source'... [INFO] [stderr] done. [INFO] validating manifest of git repo https://github.com/MelomanCool/chip-8-emulator-rust on toolchain 7587ff3622fbec0abf6ac551eab5226f22f5d958 [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+7587ff3622fbec0abf6ac551eab5226f22f5d958" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }` [INFO] started tweaking git repo https://github.com/MelomanCool/chip-8-emulator-rust [INFO] finished tweaking git repo https://github.com/MelomanCool/chip-8-emulator-rust [INFO] tweaked toml for git repo https://github.com/MelomanCool/chip-8-emulator-rust written to /workspace/builds/worker-5-tc2/source/Cargo.toml [INFO] crate git repo https://github.com/MelomanCool/chip-8-emulator-rust already has a lockfile, it will not be regenerated [INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+7587ff3622fbec0abf6ac551eab5226f22f5d958" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }` [INFO] [stderr] Blocking waiting for file lock on package cache [INFO] [stderr] Blocking waiting for file lock on package cache [INFO] [stderr] Downloading crates ... [INFO] [stderr] Downloaded rand_pcg v0.2.0 [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-5-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-5-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:923055f121b5182466d55868a8b05e67af8ba4a3a3f6bad814e953ca3cd3ac2a" "/opt/rustwide/cargo-home/bin/cargo" "+7587ff3622fbec0abf6ac551eab5226f22f5d958" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }` [INFO] [stdout] c6a2168a5efc5d8f86b3775048210712a75a8502bb2869f3e2e94481244e7050 [INFO] running `Command { std: "docker" "start" "-a" "c6a2168a5efc5d8f86b3775048210712a75a8502bb2869f3e2e94481244e7050", kill_on_drop: false }` [INFO] running `Command { std: "docker" "inspect" "c6a2168a5efc5d8f86b3775048210712a75a8502bb2869f3e2e94481244e7050", kill_on_drop: false }` [INFO] running `Command { std: "docker" "rm" "-f" "c6a2168a5efc5d8f86b3775048210712a75a8502bb2869f3e2e94481244e7050", kill_on_drop: false }` [INFO] [stdout] c6a2168a5efc5d8f86b3775048210712a75a8502bb2869f3e2e94481244e7050 [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-5-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-5-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:923055f121b5182466d55868a8b05e67af8ba4a3a3f6bad814e953ca3cd3ac2a" "/opt/rustwide/cargo-home/bin/cargo" "+7587ff3622fbec0abf6ac551eab5226f22f5d958" "build" "--frozen" "--message-format=json", kill_on_drop: false }` [INFO] [stdout] d8790784f10aba6abc84cc9f147c0925b932a168c4e8deb35eb074a2ea4278e0 [INFO] running `Command { std: "docker" "start" "-a" "d8790784f10aba6abc84cc9f147c0925b932a168c4e8deb35eb074a2ea4278e0", kill_on_drop: false }` [INFO] [stderr] Compiling libc v0.2.62 [INFO] [stderr] Compiling getrandom v0.1.11 [INFO] [stderr] Compiling cfg-if v0.1.9 [INFO] [stderr] Compiling ppv-lite86 v0.2.5 [INFO] [stderr] Compiling c2-chacha v0.2.2 [INFO] [stderr] Compiling rand_core v0.5.1 [INFO] [stderr] Compiling rand_pcg v0.2.0 [INFO] [stderr] Compiling rand_chacha v0.2.1 [INFO] [stderr] Compiling rand v0.7.0 [INFO] [stderr] Compiling chip8_emulator v0.1.0 (/opt/rustwide/workdir) [INFO] [stdout] warning: fields `delay_timer`, `sound_timer`, and `keyboard` are never read [INFO] [stdout] --> src/main.rs:16:5 [INFO] [stdout] | [INFO] [stdout] 7 | struct Chip8 { [INFO] [stdout] | ----- fields in this struct [INFO] [stdout] ... [INFO] [stdout] 16 | delay_timer: u8, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 17 | sound_timer: u8, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 18 | [INFO] [stdout] 19 | keyboard: Vec, [INFO] [stdout] | ^^^^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `#[warn(dead_code)]` on by default [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `0` is never read [INFO] [stdout] --> src/main.rs:44:13 [INFO] [stdout] | [INFO] [stdout] 44 | Unknown(u16), [INFO] [stdout] | ------- ^^^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `MetaOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] help: consider changing the field to be of unit type to suppress this warning while preserving the field numbering, or remove the field [INFO] [stdout] | [INFO] [stdout] 44 | Unknown(()), [INFO] [stdout] | ~~ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `value` are never read [INFO] [stdout] --> src/main.rs:61:28 [INFO] [stdout] | [INFO] [stdout] 61 | SkipIfRegValNotEqual { x: u8, value: u8 }, [INFO] [stdout] | -------------------- ^ ^^^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:62:25 [INFO] [stdout] | [INFO] [stdout] 62 | SkipIfRegRegEqual { x: u8, y: u8 }, [INFO] [stdout] | ----------------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:63:28 [INFO] [stdout] | [INFO] [stdout] 63 | SkipIfRegRegNotEqual { x: u8, y: u8 }, [INFO] [stdout] | -------------------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:64:24 [INFO] [stdout] | [INFO] [stdout] 64 | SkipIfKeyPressed { x: u8 }, [INFO] [stdout] | ---------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:65:27 [INFO] [stdout] | [INFO] [stdout] 65 | SkipIfKeyNotPressed { x: u8 }, [INFO] [stdout] | ------------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:68:20 [INFO] [stdout] | [INFO] [stdout] 68 | LoadRegToReg { x: u8, y: u8 }, [INFO] [stdout] | ------------ ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:69:27 [INFO] [stdout] | [INFO] [stdout] 69 | LoadDelayTimerToReg { x: u8 }, [INFO] [stdout] | ------------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:70:20 [INFO] [stdout] | [INFO] [stdout] 70 | LoadKeyToReg { x: u8 }, [INFO] [stdout] | ------------ ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:71:27 [INFO] [stdout] | [INFO] [stdout] 71 | LoadRegToDelayTimer { x: u8 }, [INFO] [stdout] | ------------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:72:27 [INFO] [stdout] | [INFO] [stdout] 72 | LoadRegToSoundTimer { x: u8 }, [INFO] [stdout] | ------------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:74:29 [INFO] [stdout] | [INFO] [stdout] 74 | LoadSpriteLocationToI { x: u8 }, [INFO] [stdout] | --------------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:75:23 [INFO] [stdout] | [INFO] [stdout] 75 | LoadRegBcdToMem { x: u8 }, [INFO] [stdout] | --------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `n` is never read [INFO] [stdout] --> src/main.rs:76:21 [INFO] [stdout] | [INFO] [stdout] 76 | LoadRegsToMem { n: u8 }, [INFO] [stdout] | ------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `n` is never read [INFO] [stdout] --> src/main.rs:77:21 [INFO] [stdout] | [INFO] [stdout] 77 | LoadMemToRegs { n: u8 }, [INFO] [stdout] | ------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:80:21 [INFO] [stdout] | [INFO] [stdout] 80 | SubRegFromReg { x: u8, y: u8 }, [INFO] [stdout] | ------------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:81:22 [INFO] [stdout] | [INFO] [stdout] 81 | SubnRegFromReg { x: u8, y: u8 }, [INFO] [stdout] | -------------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:83:17 [INFO] [stdout] | [INFO] [stdout] 83 | AddRegToI { x: u8 }, [INFO] [stdout] | --------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:84:16 [INFO] [stdout] | [INFO] [stdout] 84 | OrRegReg { x: u8, y: u8 }, [INFO] [stdout] | -------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:85:17 [INFO] [stdout] | [INFO] [stdout] 85 | AndRegReg { x: u8, y: u8 }, [INFO] [stdout] | --------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:86:17 [INFO] [stdout] | [INFO] [stdout] 86 | XorRegReg { x: u8, y: u8 }, [INFO] [stdout] | --------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:87:19 [INFO] [stdout] | [INFO] [stdout] 87 | AddRegToReg { x: u8, y: u8 }, [INFO] [stdout] | ----------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:88:21 [INFO] [stdout] | [INFO] [stdout] 88 | ShiftRightReg { x: u8 }, [INFO] [stdout] | ------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:89:20 [INFO] [stdout] | [INFO] [stdout] 89 | ShiftLeftReg { x: u8 }, [INFO] [stdout] | ------------ ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: 25 warnings emitted [INFO] [stdout] [INFO] [stdout] [INFO] [stderr] Finished `dev` profile [unoptimized + debuginfo] target(s) in 2.50s [INFO] running `Command { std: "docker" "inspect" "d8790784f10aba6abc84cc9f147c0925b932a168c4e8deb35eb074a2ea4278e0", kill_on_drop: false }` [INFO] running `Command { std: "docker" "rm" "-f" "d8790784f10aba6abc84cc9f147c0925b932a168c4e8deb35eb074a2ea4278e0", kill_on_drop: false }` [INFO] [stdout] d8790784f10aba6abc84cc9f147c0925b932a168c4e8deb35eb074a2ea4278e0 [INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-5-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-5-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:923055f121b5182466d55868a8b05e67af8ba4a3a3f6bad814e953ca3cd3ac2a" "/opt/rustwide/cargo-home/bin/cargo" "+7587ff3622fbec0abf6ac551eab5226f22f5d958" "test" "--frozen" "--no-run" "--message-format=json", kill_on_drop: false }` [INFO] [stdout] dad3ade8ee36eba8725e5c152a68e4ecd5eac790314ba980f4afc7b39f9d5f88 [INFO] running `Command { std: "docker" "start" "-a" "dad3ade8ee36eba8725e5c152a68e4ecd5eac790314ba980f4afc7b39f9d5f88", kill_on_drop: false }` [INFO] [stderr] Compiling chip8_emulator v0.1.0 (/opt/rustwide/workdir) [INFO] [stdout] warning: fields `delay_timer`, `sound_timer`, and `keyboard` are never read [INFO] [stdout] --> src/main.rs:16:5 [INFO] [stdout] | [INFO] [stdout] 7 | struct Chip8 { [INFO] [stdout] | ----- fields in this struct [INFO] [stdout] ... [INFO] [stdout] 16 | delay_timer: u8, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 17 | sound_timer: u8, [INFO] [stdout] | ^^^^^^^^^^^ [INFO] [stdout] 18 | [INFO] [stdout] 19 | keyboard: Vec, [INFO] [stdout] | ^^^^^^^^ [INFO] [stdout] | [INFO] [stdout] = note: `#[warn(dead_code)]` on by default [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `0` is never read [INFO] [stdout] --> src/main.rs:44:13 [INFO] [stdout] | [INFO] [stdout] 44 | Unknown(u16), [INFO] [stdout] | ------- ^^^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `MetaOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] help: consider changing the field to be of unit type to suppress this warning while preserving the field numbering, or remove the field [INFO] [stdout] | [INFO] [stdout] 44 | Unknown(()), [INFO] [stdout] | ~~ [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `value` are never read [INFO] [stdout] --> src/main.rs:61:28 [INFO] [stdout] | [INFO] [stdout] 61 | SkipIfRegValNotEqual { x: u8, value: u8 }, [INFO] [stdout] | -------------------- ^ ^^^^^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:62:25 [INFO] [stdout] | [INFO] [stdout] 62 | SkipIfRegRegEqual { x: u8, y: u8 }, [INFO] [stdout] | ----------------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:63:28 [INFO] [stdout] | [INFO] [stdout] 63 | SkipIfRegRegNotEqual { x: u8, y: u8 }, [INFO] [stdout] | -------------------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:64:24 [INFO] [stdout] | [INFO] [stdout] 64 | SkipIfKeyPressed { x: u8 }, [INFO] [stdout] | ---------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:65:27 [INFO] [stdout] | [INFO] [stdout] 65 | SkipIfKeyNotPressed { x: u8 }, [INFO] [stdout] | ------------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:68:20 [INFO] [stdout] | [INFO] [stdout] 68 | LoadRegToReg { x: u8, y: u8 }, [INFO] [stdout] | ------------ ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:69:27 [INFO] [stdout] | [INFO] [stdout] 69 | LoadDelayTimerToReg { x: u8 }, [INFO] [stdout] | ------------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:70:20 [INFO] [stdout] | [INFO] [stdout] 70 | LoadKeyToReg { x: u8 }, [INFO] [stdout] | ------------ ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:71:27 [INFO] [stdout] | [INFO] [stdout] 71 | LoadRegToDelayTimer { x: u8 }, [INFO] [stdout] | ------------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:72:27 [INFO] [stdout] | [INFO] [stdout] 72 | LoadRegToSoundTimer { x: u8 }, [INFO] [stdout] | ------------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:74:29 [INFO] [stdout] | [INFO] [stdout] 74 | LoadSpriteLocationToI { x: u8 }, [INFO] [stdout] | --------------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:75:23 [INFO] [stdout] | [INFO] [stdout] 75 | LoadRegBcdToMem { x: u8 }, [INFO] [stdout] | --------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `n` is never read [INFO] [stdout] --> src/main.rs:76:21 [INFO] [stdout] | [INFO] [stdout] 76 | LoadRegsToMem { n: u8 }, [INFO] [stdout] | ------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `n` is never read [INFO] [stdout] --> src/main.rs:77:21 [INFO] [stdout] | [INFO] [stdout] 77 | LoadMemToRegs { n: u8 }, [INFO] [stdout] | ------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:80:21 [INFO] [stdout] | [INFO] [stdout] 80 | SubRegFromReg { x: u8, y: u8 }, [INFO] [stdout] | ------------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:81:22 [INFO] [stdout] | [INFO] [stdout] 81 | SubnRegFromReg { x: u8, y: u8 }, [INFO] [stdout] | -------------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:83:17 [INFO] [stdout] | [INFO] [stdout] 83 | AddRegToI { x: u8 }, [INFO] [stdout] | --------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:84:16 [INFO] [stdout] | [INFO] [stdout] 84 | OrRegReg { x: u8, y: u8 }, [INFO] [stdout] | -------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:85:17 [INFO] [stdout] | [INFO] [stdout] 85 | AndRegReg { x: u8, y: u8 }, [INFO] [stdout] | --------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:86:17 [INFO] [stdout] | [INFO] [stdout] 86 | XorRegReg { x: u8, y: u8 }, [INFO] [stdout] | --------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: fields `x` and `y` are never read [INFO] [stdout] --> src/main.rs:87:19 [INFO] [stdout] | [INFO] [stdout] 87 | AddRegToReg { x: u8, y: u8 }, [INFO] [stdout] | ----------- ^ ^ [INFO] [stdout] | | [INFO] [stdout] | fields in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:88:21 [INFO] [stdout] | [INFO] [stdout] 88 | ShiftRightReg { x: u8 }, [INFO] [stdout] | ------------- ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: field `x` is never read [INFO] [stdout] --> src/main.rs:89:20 [INFO] [stdout] | [INFO] [stdout] 89 | ShiftLeftReg { x: u8 }, [INFO] [stdout] | ------------ ^ [INFO] [stdout] | | [INFO] [stdout] | field in this variant [INFO] [stdout] | [INFO] [stdout] = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis [INFO] [stdout] [INFO] [stdout] [INFO] [stdout] warning: 25 warnings emitted [INFO] [stdout] [INFO] [stdout] [INFO] [stderr] Finished `test` profile [unoptimized + debuginfo] target(s) in 0.45s [INFO] running `Command { std: "docker" "inspect" "dad3ade8ee36eba8725e5c152a68e4ecd5eac790314ba980f4afc7b39f9d5f88", kill_on_drop: false }` [INFO] running `Command { std: "docker" "rm" "-f" "dad3ade8ee36eba8725e5c152a68e4ecd5eac790314ba980f4afc7b39f9d5f88", kill_on_drop: false }` [INFO] [stdout] dad3ade8ee36eba8725e5c152a68e4ecd5eac790314ba980f4afc7b39f9d5f88