[INFO] cloning repository https://github.com/MelomanCool/chip-8-emulator-rust
[INFO] running `Command { std: "git" "-c" "credential.helper=" "-c" "credential.helper=/workspace/cargo-home/bin/git-credential-null" "clone" "--bare" "https://github.com/MelomanCool/chip-8-emulator-rust" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FMelomanCool%2Fchip-8-emulator-rust", kill_on_drop: false }`
[INFO] [stderr] Cloning into bare repository '/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FMelomanCool%2Fchip-8-emulator-rust'...
[INFO] running `Command { std: "git" "rev-parse" "HEAD", kill_on_drop: false }`
[INFO] [stdout] d9b2b91f82929e8f86ee093bb97a815f7bdc71fb
[INFO] testing MelomanCool/chip-8-emulator-rust against try#8de4c7234dd9b97c9d76b58671343fdbbc9a433e+target=x86_64-unknown-linux-musl for musl_upgrade_1_2_5_in_2025-retry-1
[INFO] running `Command { std: "git" "clone" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FMelomanCool%2Fchip-8-emulator-rust" "/workspace/builds/worker-7-tc1/source", kill_on_drop: false }`
[INFO] [stderr] Cloning into '/workspace/builds/worker-7-tc1/source'...
[INFO] [stderr] done.
[INFO] started tweaking git repo https://github.com/MelomanCool/chip-8-emulator-rust
[INFO] finished tweaking git repo https://github.com/MelomanCool/chip-8-emulator-rust
[INFO] tweaked toml for git repo https://github.com/MelomanCool/chip-8-emulator-rust written to /workspace/builds/worker-7-tc1/source/Cargo.toml
[INFO] validating manifest of git repo https://github.com/MelomanCool/chip-8-emulator-rust on toolchain 8de4c7234dd9b97c9d76b58671343fdbbc9a433e
[INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+8de4c7234dd9b97c9d76b58671343fdbbc9a433e" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }`
[INFO] crate git repo https://github.com/MelomanCool/chip-8-emulator-rust already has a lockfile, it will not be regenerated
[INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+8de4c7234dd9b97c9d76b58671343fdbbc9a433e" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }`
[INFO] [stderr]  Downloading crates ...
[INFO] [stderr]   Downloaded getrandom v0.1.11
[INFO] [stderr]   Downloaded rand_pcg v0.2.0
[INFO] [stderr]   Downloaded wasi v0.5.0
[INFO] [stderr]   Downloaded rand v0.7.0
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc1/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc1/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:90999bfc7ae267e83380e433d8e61a7c072ca6729e92edbae886d3423b3a6f4c" "/opt/rustwide/cargo-home/bin/cargo" "+8de4c7234dd9b97c9d76b58671343fdbbc9a433e" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }`
[INFO] [stdout] cab720280541416eb20f83e5ed7eec555536872f6aed74fc9a7e066241eba37e
[INFO] running `Command { std: "docker" "start" "-a" "cab720280541416eb20f83e5ed7eec555536872f6aed74fc9a7e066241eba37e", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "inspect" "cab720280541416eb20f83e5ed7eec555536872f6aed74fc9a7e066241eba37e", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "cab720280541416eb20f83e5ed7eec555536872f6aed74fc9a7e066241eba37e", kill_on_drop: false }`
[INFO] [stdout] cab720280541416eb20f83e5ed7eec555536872f6aed74fc9a7e066241eba37e
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc1/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc1/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:90999bfc7ae267e83380e433d8e61a7c072ca6729e92edbae886d3423b3a6f4c" "/opt/rustwide/cargo-home/bin/cargo" "+8de4c7234dd9b97c9d76b58671343fdbbc9a433e" "build" "--frozen" "--message-format=json" "--target" "x86_64-unknown-linux-musl", kill_on_drop: false }`
[INFO] [stdout] 640c28301393f32aed5f6b6721fb865c66a731a27d85f74d409a7e093d2c38f2
[INFO] running `Command { std: "docker" "start" "-a" "640c28301393f32aed5f6b6721fb865c66a731a27d85f74d409a7e093d2c38f2", kill_on_drop: false }`
[INFO] [stderr]    Compiling libc v0.2.62
[INFO] [stderr]    Compiling getrandom v0.1.11
[INFO] [stderr]    Compiling cfg-if v0.1.9
[INFO] [stderr]    Compiling ppv-lite86 v0.2.5
[INFO] [stderr]    Compiling c2-chacha v0.2.2
[INFO] [stderr]    Compiling rand_core v0.5.1
[INFO] [stderr]    Compiling rand_chacha v0.2.1
[INFO] [stderr]    Compiling rand_pcg v0.2.0
[INFO] [stderr]    Compiling rand v0.7.0
[INFO] [stderr]    Compiling chip8_emulator v0.1.0 (/opt/rustwide/workdir)
[INFO] [stdout] warning: fields `delay_timer`, `sound_timer`, and `keyboard` are never read
[INFO] [stdout]   --> src/main.rs:16:5
[INFO] [stdout]    |
[INFO] [stdout] 7  | struct Chip8 {
[INFO] [stdout]    |        ----- fields in this struct
[INFO] [stdout] ...
[INFO] [stdout] 16 |     delay_timer: u8,
[INFO] [stdout]    |     ^^^^^^^^^^^
[INFO] [stdout] 17 |     sound_timer: u8,
[INFO] [stdout]    |     ^^^^^^^^^^^
[INFO] [stdout] 18 |
[INFO] [stdout] 19 |     keyboard: Vec<bool>,
[INFO] [stdout]    |     ^^^^^^^^
[INFO] [stdout]    |
[INFO] [stdout]    = note: `#[warn(dead_code)]` on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `0` is never read
[INFO] [stdout]   --> src/main.rs:44:13
[INFO] [stdout]    |
[INFO] [stdout] 44 |     Unknown(u16),
[INFO] [stdout]    |     ------- ^^^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `MetaOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] help: consider changing the field to be of unit type to suppress this warning while preserving the field numbering, or remove the field
[INFO] [stdout]    |
[INFO] [stdout] 44 -     Unknown(u16),
[INFO] [stdout] 44 +     Unknown(()),
[INFO] [stdout]    |
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `value` are never read
[INFO] [stdout]   --> src/main.rs:61:28
[INFO] [stdout]    |
[INFO] [stdout] 61 |     SkipIfRegValNotEqual { x: u8, value: u8 },
[INFO] [stdout]    |     --------------------   ^      ^^^^^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:62:25
[INFO] [stdout]    |
[INFO] [stdout] 62 |     SkipIfRegRegEqual { x: u8, y: u8 },
[INFO] [stdout]    |     -----------------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:63:28
[INFO] [stdout]    |
[INFO] [stdout] 63 |     SkipIfRegRegNotEqual { x: u8, y: u8 },
[INFO] [stdout]    |     --------------------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:64:24
[INFO] [stdout]    |
[INFO] [stdout] 64 |     SkipIfKeyPressed { x: u8 },
[INFO] [stdout]    |     ----------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:65:27
[INFO] [stdout]    |
[INFO] [stdout] 65 |     SkipIfKeyNotPressed { x: u8 },
[INFO] [stdout]    |     -------------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:68:20
[INFO] [stdout]    |
[INFO] [stdout] 68 |     LoadRegToReg { x: u8, y: u8 }, 
[INFO] [stdout]    |     ------------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:69:27
[INFO] [stdout]    |
[INFO] [stdout] 69 |     LoadDelayTimerToReg { x: u8 },
[INFO] [stdout]    |     -------------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:70:20
[INFO] [stdout]    |
[INFO] [stdout] 70 |     LoadKeyToReg { x: u8 },
[INFO] [stdout]    |     ------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:71:27
[INFO] [stdout]    |
[INFO] [stdout] 71 |     LoadRegToDelayTimer { x: u8 },
[INFO] [stdout]    |     -------------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:72:27
[INFO] [stdout]    |
[INFO] [stdout] 72 |     LoadRegToSoundTimer { x: u8 },
[INFO] [stdout]    |     -------------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:74:29
[INFO] [stdout]    |
[INFO] [stdout] 74 |     LoadSpriteLocationToI { x: u8 }, 
[INFO] [stdout]    |     ---------------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:75:23
[INFO] [stdout]    |
[INFO] [stdout] 75 |     LoadRegBcdToMem { x: u8 },
[INFO] [stdout]    |     ---------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `n` is never read
[INFO] [stdout]   --> src/main.rs:76:21
[INFO] [stdout]    |
[INFO] [stdout] 76 |     LoadRegsToMem { n: u8 },
[INFO] [stdout]    |     -------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `n` is never read
[INFO] [stdout]   --> src/main.rs:77:21
[INFO] [stdout]    |
[INFO] [stdout] 77 |     LoadMemToRegs { n: u8 },
[INFO] [stdout]    |     -------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:80:21
[INFO] [stdout]    |
[INFO] [stdout] 80 |     SubRegFromReg { x: u8, y: u8 }, 
[INFO] [stdout]    |     -------------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:81:22
[INFO] [stdout]    |
[INFO] [stdout] 81 |     SubnRegFromReg { x: u8, y: u8 }, 
[INFO] [stdout]    |     --------------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:83:17
[INFO] [stdout]    |
[INFO] [stdout] 83 |     AddRegToI { x: u8 },
[INFO] [stdout]    |     ---------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:84:16
[INFO] [stdout]    |
[INFO] [stdout] 84 |     OrRegReg { x: u8, y: u8 },
[INFO] [stdout]    |     --------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:85:17
[INFO] [stdout]    |
[INFO] [stdout] 85 |     AndRegReg { x: u8, y: u8 },
[INFO] [stdout]    |     ---------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:86:17
[INFO] [stdout]    |
[INFO] [stdout] 86 |     XorRegReg { x: u8, y: u8 },
[INFO] [stdout]    |     ---------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:87:19
[INFO] [stdout]    |
[INFO] [stdout] 87 |     AddRegToReg { x: u8, y: u8 },
[INFO] [stdout]    |     -----------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:88:21
[INFO] [stdout]    |
[INFO] [stdout] 88 |     ShiftRightReg { x: u8 },
[INFO] [stdout]    |     -------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:89:20
[INFO] [stdout]    |
[INFO] [stdout] 89 |     ShiftLeftReg { x: u8 }, 
[INFO] [stdout]    |     ------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stderr]     Finished `dev` profile [unoptimized + debuginfo] target(s) in 3.24s
[INFO] running `Command { std: "docker" "inspect" "640c28301393f32aed5f6b6721fb865c66a731a27d85f74d409a7e093d2c38f2", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "640c28301393f32aed5f6b6721fb865c66a731a27d85f74d409a7e093d2c38f2", kill_on_drop: false }`
[INFO] [stdout] 640c28301393f32aed5f6b6721fb865c66a731a27d85f74d409a7e093d2c38f2
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc1/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc1/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:90999bfc7ae267e83380e433d8e61a7c072ca6729e92edbae886d3423b3a6f4c" "/opt/rustwide/cargo-home/bin/cargo" "+8de4c7234dd9b97c9d76b58671343fdbbc9a433e" "test" "--frozen" "--no-run" "--message-format=json" "--target" "x86_64-unknown-linux-musl", kill_on_drop: false }`
[INFO] [stdout] f87a975bd81edd503071898c4ed23967cc99992cc0538e558ea4ab4590e65b89
[INFO] running `Command { std: "docker" "start" "-a" "f87a975bd81edd503071898c4ed23967cc99992cc0538e558ea4ab4590e65b89", kill_on_drop: false }`
[INFO] [stderr]    Compiling chip8_emulator v0.1.0 (/opt/rustwide/workdir)
[INFO] [stdout] warning: fields `delay_timer`, `sound_timer`, and `keyboard` are never read
[INFO] [stdout]   --> src/main.rs:16:5
[INFO] [stdout]    |
[INFO] [stdout] 7  | struct Chip8 {
[INFO] [stdout]    |        ----- fields in this struct
[INFO] [stdout] ...
[INFO] [stdout] 16 |     delay_timer: u8,
[INFO] [stdout]    |     ^^^^^^^^^^^
[INFO] [stdout] 17 |     sound_timer: u8,
[INFO] [stdout]    |     ^^^^^^^^^^^
[INFO] [stdout] 18 |
[INFO] [stdout] 19 |     keyboard: Vec<bool>,
[INFO] [stdout]    |     ^^^^^^^^
[INFO] [stdout]    |
[INFO] [stdout]    = note: `#[warn(dead_code)]` on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `0` is never read
[INFO] [stdout]   --> src/main.rs:44:13
[INFO] [stdout]    |
[INFO] [stdout] 44 |     Unknown(u16),
[INFO] [stdout]    |     ------- ^^^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `MetaOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] help: consider changing the field to be of unit type to suppress this warning while preserving the field numbering, or remove the field
[INFO] [stdout]    |
[INFO] [stdout] 44 -     Unknown(u16),
[INFO] [stdout] 44 +     Unknown(()),
[INFO] [stdout]    |
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `value` are never read
[INFO] [stdout]   --> src/main.rs:61:28
[INFO] [stdout]    |
[INFO] [stdout] 61 |     SkipIfRegValNotEqual { x: u8, value: u8 },
[INFO] [stdout]    |     --------------------   ^      ^^^^^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:62:25
[INFO] [stdout]    |
[INFO] [stdout] 62 |     SkipIfRegRegEqual { x: u8, y: u8 },
[INFO] [stdout]    |     -----------------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:63:28
[INFO] [stdout]    |
[INFO] [stdout] 63 |     SkipIfRegRegNotEqual { x: u8, y: u8 },
[INFO] [stdout]    |     --------------------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:64:24
[INFO] [stdout]    |
[INFO] [stdout] 64 |     SkipIfKeyPressed { x: u8 },
[INFO] [stdout]    |     ----------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:65:27
[INFO] [stdout]    |
[INFO] [stdout] 65 |     SkipIfKeyNotPressed { x: u8 },
[INFO] [stdout]    |     -------------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:68:20
[INFO] [stdout]    |
[INFO] [stdout] 68 |     LoadRegToReg { x: u8, y: u8 }, 
[INFO] [stdout]    |     ------------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:69:27
[INFO] [stdout]    |
[INFO] [stdout] 69 |     LoadDelayTimerToReg { x: u8 },
[INFO] [stdout]    |     -------------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:70:20
[INFO] [stdout]    |
[INFO] [stdout] 70 |     LoadKeyToReg { x: u8 },
[INFO] [stdout]    |     ------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:71:27
[INFO] [stdout]    |
[INFO] [stdout] 71 |     LoadRegToDelayTimer { x: u8 },
[INFO] [stdout]    |     -------------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:72:27
[INFO] [stdout]    |
[INFO] [stdout] 72 |     LoadRegToSoundTimer { x: u8 },
[INFO] [stdout]    |     -------------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:74:29
[INFO] [stdout]    |
[INFO] [stdout] 74 |     LoadSpriteLocationToI { x: u8 }, 
[INFO] [stdout]    |     ---------------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:75:23
[INFO] [stdout]    |
[INFO] [stdout] 75 |     LoadRegBcdToMem { x: u8 },
[INFO] [stdout]    |     ---------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `n` is never read
[INFO] [stdout]   --> src/main.rs:76:21
[INFO] [stdout]    |
[INFO] [stdout] 76 |     LoadRegsToMem { n: u8 },
[INFO] [stdout]    |     -------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `n` is never read
[INFO] [stdout]   --> src/main.rs:77:21
[INFO] [stdout]    |
[INFO] [stdout] 77 |     LoadMemToRegs { n: u8 },
[INFO] [stdout]    |     -------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:80:21
[INFO] [stdout]    |
[INFO] [stdout] 80 |     SubRegFromReg { x: u8, y: u8 }, 
[INFO] [stdout]    |     -------------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:81:22
[INFO] [stdout]    |
[INFO] [stdout] 81 |     SubnRegFromReg { x: u8, y: u8 }, 
[INFO] [stdout]    |     --------------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:83:17
[INFO] [stdout]    |
[INFO] [stdout] 83 |     AddRegToI { x: u8 },
[INFO] [stdout]    |     ---------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:84:16
[INFO] [stdout]    |
[INFO] [stdout] 84 |     OrRegReg { x: u8, y: u8 },
[INFO] [stdout]    |     --------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:85:17
[INFO] [stdout]    |
[INFO] [stdout] 85 |     AndRegReg { x: u8, y: u8 },
[INFO] [stdout]    |     ---------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:86:17
[INFO] [stdout]    |
[INFO] [stdout] 86 |     XorRegReg { x: u8, y: u8 },
[INFO] [stdout]    |     ---------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `x` and `y` are never read
[INFO] [stdout]   --> src/main.rs:87:19
[INFO] [stdout]    |
[INFO] [stdout] 87 |     AddRegToReg { x: u8, y: u8 },
[INFO] [stdout]    |     -----------   ^      ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     fields in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:88:21
[INFO] [stdout]    |
[INFO] [stdout] 88 |     ShiftRightReg { x: u8 },
[INFO] [stdout]    |     -------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: field `x` is never read
[INFO] [stdout]   --> src/main.rs:89:20
[INFO] [stdout]    |
[INFO] [stdout] 89 |     ShiftLeftReg { x: u8 }, 
[INFO] [stdout]    |     ------------   ^
[INFO] [stdout]    |     |
[INFO] [stdout]    |     field in this variant
[INFO] [stdout]    |
[INFO] [stdout]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stderr]     Finished `test` profile [unoptimized + debuginfo] target(s) in 0.53s
[INFO] running `Command { std: "docker" "inspect" "f87a975bd81edd503071898c4ed23967cc99992cc0538e558ea4ab4590e65b89", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "f87a975bd81edd503071898c4ed23967cc99992cc0538e558ea4ab4590e65b89", kill_on_drop: false }`
[INFO] [stdout] f87a975bd81edd503071898c4ed23967cc99992cc0538e558ea4ab4590e65b89
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc1/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc1/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:90999bfc7ae267e83380e433d8e61a7c072ca6729e92edbae886d3423b3a6f4c" "/opt/rustwide/cargo-home/bin/cargo" "+8de4c7234dd9b97c9d76b58671343fdbbc9a433e" "test" "--frozen" "--target" "x86_64-unknown-linux-musl", kill_on_drop: false }`
[INFO] [stdout] 996db19bd00f1949fec0fe7992d1e799c45547a59d28a9f4eea125e5ba70591f
[INFO] running `Command { std: "docker" "start" "-a" "996db19bd00f1949fec0fe7992d1e799c45547a59d28a9f4eea125e5ba70591f", kill_on_drop: false }`
[INFO] [stderr] warning: fields `delay_timer`, `sound_timer`, and `keyboard` are never read
[INFO] [stderr]   --> src/main.rs:16:5
[INFO] [stderr]    |
[INFO] [stderr] 7  | struct Chip8 {
[INFO] [stderr]    |        ----- fields in this struct
[INFO] [stderr] ...
[INFO] [stderr] 16 |     delay_timer: u8,
[INFO] [stderr]    |     ^^^^^^^^^^^
[INFO] [stderr] 17 |     sound_timer: u8,
[INFO] [stderr]    |     ^^^^^^^^^^^
[INFO] [stderr] 18 |
[INFO] [stderr] 19 |     keyboard: Vec<bool>,
[INFO] [stderr]    |     ^^^^^^^^
[INFO] [stderr]    |
[INFO] [stderr]    = note: `#[warn(dead_code)]` on by default
[INFO] [stderr] 
[INFO] [stderr] warning: field `0` is never read
[INFO] [stderr]   --> src/main.rs:44:13
[INFO] [stderr]    |
[INFO] [stderr] 44 |     Unknown(u16),
[INFO] [stderr]    |     ------- ^^^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `MetaOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] help: consider changing the field to be of unit type to suppress this warning while preserving the field numbering, or remove the field
[INFO] [stderr]    |
[INFO] [stderr] 44 -     Unknown(u16),
[INFO] [stderr] 44 +     Unknown(()),
[INFO] [stderr]    |
[INFO] [stderr] 
[INFO] [stderr] warning: fields `x` and `value` are never read
[INFO] [stderr]   --> src/main.rs:61:28
[INFO] [stderr]    |
[INFO] [stderr] 61 |     SkipIfRegValNotEqual { x: u8, value: u8 },
[INFO] [stderr]    |     --------------------   ^      ^^^^^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     fields in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `x` and `y` are never read
[INFO] [stderr]   --> src/main.rs:62:25
[INFO] [stderr]    |
[INFO] [stderr] 62 |     SkipIfRegRegEqual { x: u8, y: u8 },
[INFO] [stderr]    |     -----------------   ^      ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     fields in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `x` and `y` are never read
[INFO] [stderr]   --> src/main.rs:63:28
[INFO] [stderr]    |
[INFO] [stderr] 63 |     SkipIfRegRegNotEqual { x: u8, y: u8 },
[INFO] [stderr]    |     --------------------   ^      ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     fields in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `x` is never read
[INFO] [stderr]   --> src/main.rs:64:24
[INFO] [stderr]    |
[INFO] [stderr] 64 |     SkipIfKeyPressed { x: u8 },
[INFO] [stderr]    |     ----------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `x` is never read
[INFO] [stderr]   --> src/main.rs:65:27
[INFO] [stderr]    |
[INFO] [stderr] 65 |     SkipIfKeyNotPressed { x: u8 },
[INFO] [stderr]    |     -------------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `x` and `y` are never read
[INFO] [stderr]   --> src/main.rs:68:20
[INFO] [stderr]    |
[INFO] [stderr] 68 |     LoadRegToReg { x: u8, y: u8 }, 
[INFO] [stderr]    |     ------------   ^      ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     fields in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `x` is never read
[INFO] [stderr]   --> src/main.rs:69:27
[INFO] [stderr]    |
[INFO] [stderr] 69 |     LoadDelayTimerToReg { x: u8 },
[INFO] [stderr]    |     -------------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `x` is never read
[INFO] [stderr]   --> src/main.rs:70:20
[INFO] [stderr]    |
[INFO] [stderr] 70 |     LoadKeyToReg { x: u8 },
[INFO] [stderr]    |     ------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `x` is never read
[INFO] [stderr]   --> src/main.rs:71:27
[INFO] [stderr]    |
[INFO] [stderr] 71 |     LoadRegToDelayTimer { x: u8 },
[INFO] [stderr]    |     -------------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `x` is never read
[INFO] [stderr]   --> src/main.rs:72:27
[INFO] [stderr]    |
[INFO] [stderr] 72 |     LoadRegToSoundTimer { x: u8 },
[INFO] [stderr]    |     -------------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `x` is never read
[INFO] [stderr]   --> src/main.rs:74:29
[INFO] [stderr]    |
[INFO] [stderr] 74 |     LoadSpriteLocationToI { x: u8 }, 
[INFO] [stderr]    |     ---------------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `x` is never read
[INFO] [stderr]   --> src/main.rs:75:23
[INFO] [stderr]    |
[INFO] [stderr] 75 |     LoadRegBcdToMem { x: u8 },
[INFO] [stderr]    |     ---------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `n` is never read
[INFO] [stderr]   --> src/main.rs:76:21
[INFO] [stderr]    |
[INFO] [stderr] 76 |     LoadRegsToMem { n: u8 },
[INFO] [stderr]    |     -------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `n` is never read
[INFO] [stderr]   --> src/main.rs:77:21
[INFO] [stderr]    |
[INFO] [stderr] 77 |     LoadMemToRegs { n: u8 },
[INFO] [stderr]    |     -------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `x` and `y` are never read
[INFO] [stderr]   --> src/main.rs:80:21
[INFO] [stderr]    |
[INFO] [stderr] 80 |     SubRegFromReg { x: u8, y: u8 }, 
[INFO] [stderr]    |     -------------   ^      ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     fields in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `x` and `y` are never read
[INFO] [stderr]   --> src/main.rs:81:22
[INFO] [stderr]    |
[INFO] [stderr] 81 |     SubnRegFromReg { x: u8, y: u8 }, 
[INFO] [stderr]    |     --------------   ^      ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     fields in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `x` is never read
[INFO] [stderr]   --> src/main.rs:83:17
[INFO] [stderr]    |
[INFO] [stderr] 83 |     AddRegToI { x: u8 },
[INFO] [stderr]    |     ---------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `x` and `y` are never read
[INFO] [stderr]   --> src/main.rs:84:16
[INFO] [stderr]    |
[INFO] [stderr] 84 |     OrRegReg { x: u8, y: u8 },
[INFO] [stderr]    |     --------   ^      ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     fields in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `x` and `y` are never read
[INFO] [stderr]   --> src/main.rs:85:17
[INFO] [stderr]    |
[INFO] [stderr] 85 |     AndRegReg { x: u8, y: u8 },
[INFO] [stderr]    |     ---------   ^      ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     fields in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `x` and `y` are never read
[INFO] [stderr]   --> src/main.rs:86:17
[INFO] [stderr]    |
[INFO] [stderr] 86 |     XorRegReg { x: u8, y: u8 },
[INFO] [stderr]    |     ---------   ^      ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     fields in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `x` and `y` are never read
[INFO] [stderr]   --> src/main.rs:87:19
[INFO] [stderr]    |
[INFO] [stderr] 87 |     AddRegToReg { x: u8, y: u8 },
[INFO] [stderr]    |     -----------   ^      ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     fields in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `x` is never read
[INFO] [stderr]   --> src/main.rs:88:21
[INFO] [stderr]    |
[INFO] [stderr] 88 |     ShiftRightReg { x: u8 },
[INFO] [stderr]    |     -------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: field `x` is never read
[INFO] [stderr]   --> src/main.rs:89:20
[INFO] [stderr]    |
[INFO] [stderr] 89 |     ShiftLeftReg { x: u8 }, 
[INFO] [stderr]    |     ------------   ^
[INFO] [stderr]    |     |
[INFO] [stderr]    |     field in this variant
[INFO] [stderr]    |
[INFO] [stderr]    = note: `RegularOpcode` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: `chip8_emulator` (bin "chip8_emulator" test) generated 25 warnings
[INFO] [stderr]     Finished `test` profile [unoptimized + debuginfo] target(s) in 0.03s
[INFO] [stderr]      Running unittests src/main.rs (/opt/rustwide/target/x86_64-unknown-linux-musl/debug/deps/chip8_emulator-974a8f76984356ac)
[INFO] [stdout] 
[INFO] [stdout] running 0 tests
[INFO] [stdout] 
[INFO] [stdout] test result: ok. 0 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.00s
[INFO] [stdout] 
[INFO] running `Command { std: "docker" "inspect" "996db19bd00f1949fec0fe7992d1e799c45547a59d28a9f4eea125e5ba70591f", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "996db19bd00f1949fec0fe7992d1e799c45547a59d28a9f4eea125e5ba70591f", kill_on_drop: false }`
[INFO] [stdout] 996db19bd00f1949fec0fe7992d1e799c45547a59d28a9f4eea125e5ba70591f