[INFO] cloning repository https://github.com/TinyCoor/riscv-emulator
[INFO] running `Command { std: "git" "-c" "credential.helper=" "-c" "credential.helper=/workspace/cargo-home/bin/git-credential-null" "clone" "--bare" "https://github.com/TinyCoor/riscv-emulator" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FTinyCoor%2Friscv-emulator", kill_on_drop: false }`
[INFO] [stderr] Cloning into bare repository '/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FTinyCoor%2Friscv-emulator'...
[INFO] running `Command { std: "git" "rev-parse" "HEAD", kill_on_drop: false }`
[INFO] [stdout] c9f6d41eb63ade8cc812287c5a158ed5c403cb9a
[INFO] testing TinyCoor/riscv-emulator against beta-2026-03-05 for beta-1.95-1
[INFO] running `Command { std: "git" "clone" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FTinyCoor%2Friscv-emulator" "/workspace/builds/worker-7-tc2/source", kill_on_drop: false }`
[INFO] [stderr] Cloning into '/workspace/builds/worker-7-tc2/source'...
[INFO] [stderr] done.
[INFO] started tweaking git repo https://github.com/TinyCoor/riscv-emulator
[INFO] finished tweaking git repo https://github.com/TinyCoor/riscv-emulator
[INFO] tweaked toml for git repo https://github.com/TinyCoor/riscv-emulator written to /workspace/builds/worker-7-tc2/source/Cargo.toml
[INFO] validating manifest of git repo https://github.com/TinyCoor/riscv-emulator on toolchain beta-2026-03-05
[INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+beta-2026-03-05" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }`
[INFO] crate git repo https://github.com/TinyCoor/riscv-emulator already has a lockfile, it will not be regenerated
[INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+beta-2026-03-05" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:d429b63d4308055ea97f60fb1d3dfca48854a00942f1bd2ad806beaf015945ec" "/opt/rustwide/cargo-home/bin/cargo" "+beta-2026-03-05" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }`
[INFO] [stdout] 8f8db8727ffafe5b8203abdd063ffbcd34a932ece8dca9c4203fde87746cefee
[INFO] running `Command { std: "docker" "start" "-a" "8f8db8727ffafe5b8203abdd063ffbcd34a932ece8dca9c4203fde87746cefee", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "inspect" "8f8db8727ffafe5b8203abdd063ffbcd34a932ece8dca9c4203fde87746cefee", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "8f8db8727ffafe5b8203abdd063ffbcd34a932ece8dca9c4203fde87746cefee", kill_on_drop: false }`
[INFO] [stdout] 8f8db8727ffafe5b8203abdd063ffbcd34a932ece8dca9c4203fde87746cefee
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=warn" "-e" "RUSTDOCFLAGS=--cap-lints=warn" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:d429b63d4308055ea97f60fb1d3dfca48854a00942f1bd2ad806beaf015945ec" "/opt/rustwide/cargo-home/bin/cargo" "+beta-2026-03-05" "build" "--frozen" "--message-format=json", kill_on_drop: false }`
[INFO] [stdout] 1dd806c7075e0a93dd9a6cda4fe1293513a37e49e2a041b6ab29b7432c6c586a
[INFO] running `Command { std: "docker" "start" "-a" "1dd806c7075e0a93dd9a6cda4fe1293513a37e49e2a041b6ab29b7432c6c586a", kill_on_drop: false }`
[INFO] [stderr]    Compiling rsicv_emulator v0.1.0 (/opt/rustwide/workdir)
[INFO] [stdout] warning: enum `Type` is never used
[INFO] [stdout]   --> src/main.rs:89:6
[INFO] [stdout]    |
[INFO] [stdout] 89 | enum Type {
[INFO] [stdout]    |      ^^^^
[INFO] [stdout]    |
[INFO] [stdout]    = note: `#[warn(dead_code)]` (part of `#[warn(unused)]`) on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: method `decode` is never used
[INFO] [stdout]   --> src/main.rs:99:8
[INFO] [stdout]    |
[INFO] [stdout] 98 | impl Type {
[INFO] [stdout]    | --------- method in this implementation
[INFO] [stdout] 99 |     fn decode(&self, inst: u32) -> Instruction {
[INFO] [stdout]    |        ^^^^^^
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: enum `Instruction` is never used
[INFO] [stdout]    --> src/main.rs:309:6
[INFO] [stdout]     |
[INFO] [stdout] 309 | enum Instruction {
[INFO] [stdout]     |      ^^^^^^^^^^^
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: function `decode` is never used
[INFO] [stdout]    --> src/main.rs:380:4
[INFO] [stdout]     |
[INFO] [stdout] 380 | fn decode(inst: u32) -> Instruction {
[INFO] [stdout]     |    ^^^^^^
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: constant `OPCODE_TABLE` is never used
[INFO] [stdout]    --> src/main.rs:389:7
[INFO] [stdout]     |
[INFO] [stdout] 389 | const OPCODE_TABLE:[Option<Type>; 128] = [
[INFO] [stdout]     |       ^^^^^^^^^^^^
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stderr]     Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.36s
[INFO] running `Command { std: "docker" "inspect" "1dd806c7075e0a93dd9a6cda4fe1293513a37e49e2a041b6ab29b7432c6c586a", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "1dd806c7075e0a93dd9a6cda4fe1293513a37e49e2a041b6ab29b7432c6c586a", kill_on_drop: false }`
[INFO] [stdout] 1dd806c7075e0a93dd9a6cda4fe1293513a37e49e2a041b6ab29b7432c6c586a
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=warn" "-e" "RUSTDOCFLAGS=--cap-lints=warn" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:d429b63d4308055ea97f60fb1d3dfca48854a00942f1bd2ad806beaf015945ec" "/opt/rustwide/cargo-home/bin/cargo" "+beta-2026-03-05" "test" "--frozen" "--no-run" "--message-format=json", kill_on_drop: false }`
[INFO] [stdout] cfd07a3036f544bebed450852b9e74379593e74d17711e58ebc268886923e2f8
[INFO] running `Command { std: "docker" "start" "-a" "cfd07a3036f544bebed450852b9e74379593e74d17711e58ebc268886923e2f8", kill_on_drop: false }`
[INFO] [stderr]    Compiling rsicv_emulator v0.1.0 (/opt/rustwide/workdir)
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:312:11
[INFO] [stdout]     |
[INFO] [stdout] 312 |     Addiw{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ----- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout]     = note: `#[warn(dead_code)]` (part of `#[warn(unused)]`) on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:313:11
[INFO] [stdout]     |
[INFO] [stdout] 313 |     Slliw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:314:11
[INFO] [stdout]     |
[INFO] [stdout] 314 |     Srliw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:315:11
[INFO] [stdout]     |
[INFO] [stdout] 315 |     Sraiw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:317:10
[INFO] [stdout]     |
[INFO] [stdout] 317 |     Addi{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:318:10
[INFO] [stdout]     |
[INFO] [stdout] 318 |     Slti{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:319:11
[INFO] [stdout]     |
[INFO] [stdout] 319 |     Sltiu{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ----- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:320:10
[INFO] [stdout]     |
[INFO] [stdout] 320 |     Xori{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:321:9
[INFO] [stdout]     |
[INFO] [stdout] 321 |     Ori{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:322:10
[INFO] [stdout]     |
[INFO] [stdout] 322 |     Andi{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:324:10
[INFO] [stdout]     |
[INFO] [stdout] 324 |     Slli{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:325:10
[INFO] [stdout]     |
[INFO] [stdout] 325 |     Srli{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:326:10
[INFO] [stdout]     |
[INFO] [stdout] 326 |     Srai{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:328:10
[INFO] [stdout]     |
[INFO] [stdout] 328 |     Lb  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     --   ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:329:10
[INFO] [stdout]     |
[INFO] [stdout] 329 |     Lh  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     --   ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:330:10
[INFO] [stdout]     |
[INFO] [stdout] 330 |     Lw  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     --   ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:331:10
[INFO] [stdout]     |
[INFO] [stdout] 331 |     Lbu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     ---  ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:332:10
[INFO] [stdout]     |
[INFO] [stdout] 332 |     Lhu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     ---  ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:333:10
[INFO] [stdout]     |
[INFO] [stdout] 333 |     Lwu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     ---  ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:334:10
[INFO] [stdout]     |
[INFO] [stdout] 334 |     Ld  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     --   ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:336:12
[INFO] [stdout]     |
[INFO] [stdout] 336 |     Fence {rd :Register, rs1:Register,  imm: i32},
[INFO] [stdout]     |     -----  ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:338:11
[INFO] [stdout]     |
[INFO] [stdout] 338 |     Jalr {rd :Register, rs1:Register,  imm: i32},
[INFO] [stdout]     |     ----  ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd` and `imm` are never read
[INFO] [stdout]    --> src/main.rs:340:12
[INFO] [stdout]     |
[INFO] [stdout] 340 |     Auipc {rd: Register, imm: i32},
[INFO] [stdout]     |     -----  ^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd` and `imm` are never read
[INFO] [stdout]    --> src/main.rs:341:10
[INFO] [stdout]     |
[INFO] [stdout] 341 |     Lui {rd: Register, imm: i32},
[INFO] [stdout]     |     ---  ^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:343:8
[INFO] [stdout]     |
[INFO] [stdout] 343 |     Sb{rs2: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     -- ^^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:344:8
[INFO] [stdout]     |
[INFO] [stdout] 344 |     Sh{rs2: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     -- ^^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:345:8
[INFO] [stdout]     |
[INFO] [stdout] 345 |     Sw{rs2: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     -- ^^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:346:8
[INFO] [stdout]     |
[INFO] [stdout] 346 |     Sd{rs2: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     -- ^^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:348:9
[INFO] [stdout]     |
[INFO] [stdout] 348 |     Add{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:349:9
[INFO] [stdout]     |
[INFO] [stdout] 349 |     Sub{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:350:9
[INFO] [stdout]     |
[INFO] [stdout] 350 |     Sll{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:351:9
[INFO] [stdout]     |
[INFO] [stdout] 351 |     Slt{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:352:10
[INFO] [stdout]     |
[INFO] [stdout] 352 |     Sltu{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:353:9
[INFO] [stdout]     |
[INFO] [stdout] 353 |     Xor{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:354:9
[INFO] [stdout]     |
[INFO] [stdout] 354 |     Srl{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:355:9
[INFO] [stdout]     |
[INFO] [stdout] 355 |     Sra{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:356:8
[INFO] [stdout]     |
[INFO] [stdout] 356 |     Or{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     -- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:357:9
[INFO] [stdout]     |
[INFO] [stdout] 357 |     And{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:360:10
[INFO] [stdout]     |
[INFO] [stdout] 360 |     Addw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:361:10
[INFO] [stdout]     |
[INFO] [stdout] 361 |     Subw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:362:10
[INFO] [stdout]     |
[INFO] [stdout] 362 |     Sllw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:363:10
[INFO] [stdout]     |
[INFO] [stdout] 363 |     Srlw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:364:10
[INFO] [stdout]     |
[INFO] [stdout] 364 |     Sraw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:366:14
[INFO] [stdout]     |
[INFO] [stdout] 366 |     Beq     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ---      ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:367:14
[INFO] [stdout]     |
[INFO] [stdout] 367 |     Bne     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ---      ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:368:14
[INFO] [stdout]     |
[INFO] [stdout] 368 |     Blt     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ---      ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:369:14
[INFO] [stdout]     |
[INFO] [stdout] 369 |     Bge     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ---      ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:370:14
[INFO] [stdout]     |
[INFO] [stdout] 370 |     Bltu    {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ----     ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:371:14
[INFO] [stdout]     |
[INFO] [stdout] 371 |     Bgeu    {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ----     ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd` and `imm` are never read
[INFO] [stdout]    --> src/main.rs:373:10
[INFO] [stdout]     |
[INFO] [stdout] 373 |     Jal {rd :Register, imm: i32},
[INFO] [stdout]     |     ---  ^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stderr]     Finished `test` profile [unoptimized + debuginfo] target(s) in 0.64s
[INFO] running `Command { std: "docker" "inspect" "cfd07a3036f544bebed450852b9e74379593e74d17711e58ebc268886923e2f8", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "cfd07a3036f544bebed450852b9e74379593e74d17711e58ebc268886923e2f8", kill_on_drop: false }`
[INFO] [stdout] cfd07a3036f544bebed450852b9e74379593e74d17711e58ebc268886923e2f8
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-7-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=warn" "-e" "RUSTDOCFLAGS=--cap-lints=warn" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:d429b63d4308055ea97f60fb1d3dfca48854a00942f1bd2ad806beaf015945ec" "/opt/rustwide/cargo-home/bin/cargo" "+beta-2026-03-05" "test" "--frozen", kill_on_drop: false }`
[INFO] [stdout] fac38896e1eea49479b9c7a3ddd5cc3983a12223796f5d7dcc0ed9ab61b33907
[INFO] running `Command { std: "docker" "start" "-a" "fac38896e1eea49479b9c7a3ddd5cc3983a12223796f5d7dcc0ed9ab61b33907", kill_on_drop: false }`
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:312:11
[INFO] [stderr]     |
[INFO] [stderr] 312 |     Addiw{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ----- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr]     = note: `#[warn(dead_code)]` (part of `#[warn(unused)]`) on by default
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:313:11
[INFO] [stderr]     |
[INFO] [stderr] 313 |     Slliw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:314:11
[INFO] [stderr]     |
[INFO] [stderr] 314 |     Srliw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:315:11
[INFO] [stderr]     |
[INFO] [stderr] 315 |     Sraiw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:317:10
[INFO] [stderr]     |
[INFO] [stderr] 317 |     Addi{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:318:10
[INFO] [stderr]     |
[INFO] [stderr] 318 |     Slti{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:319:11
[INFO] [stderr]     |
[INFO] [stderr] 319 |     Sltiu{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ----- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:320:10
[INFO] [stderr]     |
[INFO] [stderr] 320 |     Xori{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:321:9
[INFO] [stderr]     |
[INFO] [stderr] 321 |     Ori{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:322:10
[INFO] [stderr]     |
[INFO] [stderr] 322 |     Andi{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:324:10
[INFO] [stderr]     |
[INFO] [stderr] 324 |     Slli{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:325:10
[INFO] [stderr]     |
[INFO] [stderr] 325 |     Srli{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:326:10
[INFO] [stderr]     |
[INFO] [stderr] 326 |     Srai{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:328:10
[INFO] [stderr]     |
[INFO] [stderr] 328 |     Lb  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     --   ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:329:10
[INFO] [stderr]     |
[INFO] [stderr] 329 |     Lh  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     --   ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:330:10
[INFO] [stderr]     |
[INFO] [stderr] 330 |     Lw  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     --   ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:331:10
[INFO] [stderr]     |
[INFO] [stderr] 331 |     Lbu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     ---  ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:332:10
[INFO] [stderr]     |
[INFO] [stderr] 332 |     Lhu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     ---  ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:333:10
[INFO] [stderr]     |
[INFO] [stderr] 333 |     Lwu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     ---  ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:334:10
[INFO] [stderr]     |
[INFO] [stderr] 334 |     Ld  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     --   ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:336:12
[INFO] [stderr]     |
[INFO] [stderr] 336 |     Fence {rd :Register, rs1:Register,  imm: i32},
[INFO] [stderr]     |     -----  ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:338:11
[INFO] [stderr]     |
[INFO] [stderr] 338 |     Jalr {rd :Register, rs1:Register,  imm: i32},
[INFO] [stderr]     |     ----  ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd` and `imm` are never read
[INFO] [stderr]    --> src/main.rs:340:12
[INFO] [stderr]     |
[INFO] [stderr] 340 |     Auipc {rd: Register, imm: i32},
[INFO] [stderr]     |     -----  ^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd` and `imm` are never read
[INFO] [stderr]    --> src/main.rs:341:10
[INFO] [stderr]     |
[INFO] [stderr] 341 |     Lui {rd: Register, imm: i32},
[INFO] [stderr]     |     ---  ^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:343:8
[INFO] [stderr]     |
[INFO] [stderr] 343 |     Sb{rs2: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     -- ^^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:344:8
[INFO] [stderr]     |
[INFO] [stderr] 344 |     Sh{rs2: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     -- ^^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:345:8
[INFO] [stderr]     |
[INFO] [stderr] 345 |     Sw{rs2: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     -- ^^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:346:8
[INFO] [stderr]     |
[INFO] [stderr] 346 |     Sd{rs2: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     -- ^^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:348:9
[INFO] [stderr]     |
[INFO] [stderr] 348 |     Add{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:349:9
[INFO] [stderr]     |
[INFO] [stderr] 349 |     Sub{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:350:9
[INFO] [stderr]     |
[INFO] [stderr] 350 |     Sll{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:351:9
[INFO] [stderr]     |
[INFO] [stderr] 351 |     Slt{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:352:10
[INFO] [stderr]     |
[INFO] [stderr] 352 |     Sltu{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:353:9
[INFO] [stderr]     |
[INFO] [stderr] 353 |     Xor{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:354:9
[INFO] [stderr]     |
[INFO] [stderr] 354 |     Srl{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:355:9
[INFO] [stderr]     |
[INFO] [stderr] 355 |     Sra{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:356:8
[INFO] [stderr]     |
[INFO] [stderr] 356 |     Or{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     -- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:357:9
[INFO] [stderr]     |
[INFO] [stderr] 357 |     And{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:360:10
[INFO] [stderr]     |
[INFO] [stderr] 360 |     Addw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:361:10
[INFO] [stderr]     |
[INFO] [stderr] 361 |     Subw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:362:10
[INFO] [stderr]     |
[INFO] [stderr] 362 |     Sllw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:363:10
[INFO] [stderr]     |
[INFO] [stderr] 363 |     Srlw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:364:10
[INFO] [stderr]     |
[INFO] [stderr] 364 |     Sraw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:366:14
[INFO] [stderr]     |
[INFO] [stderr] 366 |     Beq     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ---      ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:367:14
[INFO] [stderr]     |
[INFO] [stderr] 367 |     Bne     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ---      ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:368:14
[INFO] [stderr]     |
[INFO] [stderr] 368 |     Blt     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ---      ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:369:14
[INFO] [stderr]     |
[INFO] [stderr] 369 |     Bge     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ---      ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:370:14
[INFO] [stderr]     |
[INFO] [stderr] 370 |     Bltu    {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ----     ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:371:14
[INFO] [stderr]     |
[INFO] [stderr] 371 |     Bgeu    {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ----     ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd` and `imm` are never read
[INFO] [stderr]    --> src/main.rs:373:10
[INFO] [stderr]     |
[INFO] [stderr] 373 |     Jal {rd :Register, imm: i32},
[INFO] [stderr]     |     ---  ^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: `rsicv_emulator` (bin "rsicv_emulator" test) generated 50 warnings
[INFO] [stderr]     Finished `test` profile [unoptimized + debuginfo] target(s) in 0.02s
[INFO] [stderr]      Running unittests src/main.rs (/opt/rustwide/target/debug/deps/rsicv_emulator-36e4cce0cb167c4a)
[INFO] [stdout] 
[INFO] [stdout] running 1 test
[INFO] [stdout] test test ... FAILED
[INFO] [stdout] 
[INFO] [stdout] failures:
[INFO] [stdout] 
[INFO] [stdout] ---- test stdout ----
[INFO] [stdout] 
[INFO] [stdout] thread 'test' (25) panicked at src/main.rs:304:5:
[INFO] [stdout] Failed
[INFO] [stdout] 
[INFO] [stdout] stack backtrace:
[INFO] [stdout]    0:     0x62941ef37bda - std[b80a194dd3c418bb]::backtrace_rs::backtrace::libunwind::trace
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/../../backtrace/src/backtrace/libunwind.rs:117:9
[INFO] [stdout]    1:     0x62941ef37bda - std[b80a194dd3c418bb]::backtrace_rs::backtrace::trace_unsynchronized::<std[b80a194dd3c418bb]::sys::backtrace::_print_fmt::{closure#1}>
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/../../backtrace/src/backtrace/mod.rs:66:14
[INFO] [stdout]    2:     0x62941ef37bda - std[b80a194dd3c418bb]::sys::backtrace::_print_fmt
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/sys/backtrace.rs:74:9
[INFO] [stdout]    3:     0x62941ef37bda - <<std[b80a194dd3c418bb]::sys::backtrace::BacktraceLock>::print::DisplayBacktrace as core[10b6fa85044e1869]::fmt::Display>::fmt
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/sys/backtrace.rs:44:26
[INFO] [stdout]    4:     0x62941ef4b84a - <core[10b6fa85044e1869]::fmt::rt::Argument>::fmt
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/core/src/fmt/rt.rs:152:76
[INFO] [stdout]    5:     0x62941ef4b84a - core[10b6fa85044e1869]::fmt::write
[INFO] [stdout]    6:     0x62941ef3c462 - std[b80a194dd3c418bb]::io::default_write_fmt::<alloc[dd269455e567d8e9]::vec::Vec<u8>>
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/io/mod.rs:639:11
[INFO] [stdout]    7:     0x62941ef3c462 - <alloc[dd269455e567d8e9]::vec::Vec<u8> as std[b80a194dd3c418bb]::io::Write>::write_fmt
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/io/mod.rs:1994:13
[INFO] [stdout]    8:     0x62941ef16def - <std[b80a194dd3c418bb]::sys::backtrace::BacktraceLock>::print
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/sys/backtrace.rs:47:9
[INFO] [stdout]    9:     0x62941ef16def - std[b80a194dd3c418bb]::panicking::default_hook::{closure#0}
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/panicking.rs:292:27
[INFO] [stdout]   10:     0x62941ef30149 - std[b80a194dd3c418bb]::panicking::default_hook
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/panicking.rs:316:9
[INFO] [stdout]   11:     0x62941eecd1ac - <alloc[dd269455e567d8e9]::boxed::Box<dyn for<'a, 'b> core[10b6fa85044e1869]::ops::function::Fn<(&'a std[b80a194dd3c418bb]::panic::PanicHookInfo<'b>,), Output = ()> + core[10b6fa85044e1869]::marker::Sync + core[10b6fa85044e1869]::marker::Send> as core[10b6fa85044e1869]::ops::function::Fn<(&std[b80a194dd3c418bb]::panic::PanicHookInfo,)>>::call
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/alloc/src/boxed.rs:2254:9
[INFO] [stdout]   12:     0x62941eecd1ac - test[826cbc6ef54ab466]::test_main_with_exit_callback::<test[826cbc6ef54ab466]::test_main::{closure#0}>::{closure#0}
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/test/src/lib.rs:145:21
[INFO] [stdout]   13:     0x62941ef30302 - <alloc[dd269455e567d8e9]::boxed::Box<dyn for<'a, 'b> core[10b6fa85044e1869]::ops::function::Fn<(&'a std[b80a194dd3c418bb]::panic::PanicHookInfo<'b>,), Output = ()> + core[10b6fa85044e1869]::marker::Sync + core[10b6fa85044e1869]::marker::Send> as core[10b6fa85044e1869]::ops::function::Fn<(&std[b80a194dd3c418bb]::panic::PanicHookInfo,)>>::call
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/alloc/src/boxed.rs:2254:9
[INFO] [stdout]   14:     0x62941ef30302 - std[b80a194dd3c418bb]::panicking::panic_with_hook
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/panicking.rs:833:13
[INFO] [stdout]   15:     0x62941ef16eda - std[b80a194dd3c418bb]::panicking::panic_handler::{closure#0}
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/panicking.rs:691:13
[INFO] [stdout]   16:     0x62941ef0e849 - std[b80a194dd3c418bb]::sys::backtrace::__rust_end_short_backtrace::<std[b80a194dd3c418bb]::panicking::panic_handler::{closure#0}, !>
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/sys/backtrace.rs:182:18
[INFO] [stdout]   17:     0x62941ef17bbd - __rustc[9698a3e60dd14283]::rust_begin_unwind
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/panicking.rs:689:5
[INFO] [stdout]   18:     0x62941ef4c05c - core[10b6fa85044e1869]::panicking::panic_fmt
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/core/src/panicking.rs:80:14
[INFO] [stdout]   19:     0x62941eec03f1 - rsicv_emulator::test::h8544f85723393541
[INFO] [stdout]                                at /opt/rustwide/workdir/src/main.rs:304:5
[INFO] [stdout]   20:     0x62941eec0417 - rsicv_emulator::test::{{closure}}::hbfc07a8f760b9772
[INFO] [stdout]                                at /opt/rustwide/workdir/src/main.rs:301:10
[INFO] [stdout]   21:     0x62941eec05f6 - core::ops::function::FnOnce::call_once::h86bb5f1064ffecc3
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/core/src/ops/function.rs:250:5
[INFO] [stdout]   22:     0x62941eec128b - <fn() -> core[10b6fa85044e1869]::result::Result<(), alloc[dd269455e567d8e9]::string::String> as core[10b6fa85044e1869]::ops::function::FnOnce<()>>::call_once
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/core/src/ops/function.rs:250:5
[INFO] [stdout]   23:     0x62941eec128b - test[826cbc6ef54ab466]::__rust_begin_short_backtrace::<core[10b6fa85044e1869]::result::Result<(), alloc[dd269455e567d8e9]::string::String>, fn() -> core[10b6fa85044e1869]::result::Result<(), alloc[dd269455e567d8e9]::string::String>>
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/test/src/lib.rs:663:18
[INFO] [stdout]   24:     0x62941eecdc7b - test[826cbc6ef54ab466]::run_test_in_process::{closure#0}
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/test/src/lib.rs:686:74
[INFO] [stdout]   25:     0x62941eecdc7b - <core[10b6fa85044e1869]::panic::unwind_safe::AssertUnwindSafe<test[826cbc6ef54ab466]::run_test_in_process::{closure#0}> as core[10b6fa85044e1869]::ops::function::FnOnce<()>>::call_once
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/core/src/panic/unwind_safe.rs:274:9
[INFO] [stdout]   26:     0x62941eecdc7b - std[b80a194dd3c418bb]::panicking::catch_unwind::do_call::<core[10b6fa85044e1869]::panic::unwind_safe::AssertUnwindSafe<test[826cbc6ef54ab466]::run_test_in_process::{closure#0}>, core[10b6fa85044e1869]::result::Result<(), alloc[dd269455e567d8e9]::string::String>>
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/panicking.rs:581:40
[INFO] [stdout]   27:     0x62941eecdc7b - std[b80a194dd3c418bb]::panicking::catch_unwind::<core[10b6fa85044e1869]::result::Result<(), alloc[dd269455e567d8e9]::string::String>, core[10b6fa85044e1869]::panic::unwind_safe::AssertUnwindSafe<test[826cbc6ef54ab466]::run_test_in_process::{closure#0}>>
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/panicking.rs:544:19
[INFO] [stdout]   28:     0x62941eecdc7b - std[b80a194dd3c418bb]::panic::catch_unwind::<core[10b6fa85044e1869]::panic::unwind_safe::AssertUnwindSafe<test[826cbc6ef54ab466]::run_test_in_process::{closure#0}>, core[10b6fa85044e1869]::result::Result<(), alloc[dd269455e567d8e9]::string::String>>
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/panic.rs:359:14
[INFO] [stdout]   29:     0x62941eecdc7b - test[826cbc6ef54ab466]::run_test_in_process
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/test/src/lib.rs:686:27
[INFO] [stdout]   30:     0x62941eecdc7b - test[826cbc6ef54ab466]::run_test::{closure#0}
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/test/src/lib.rs:607:43
[INFO] [stdout]   31:     0x62941eec9394 - test[826cbc6ef54ab466]::run_test::{closure#1}
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/test/src/lib.rs:637:41
[INFO] [stdout]   32:     0x62941eec9394 - std[b80a194dd3c418bb]::sys::backtrace::__rust_begin_short_backtrace::<test[826cbc6ef54ab466]::run_test::{closure#1}, ()>
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/sys/backtrace.rs:166:18
[INFO] [stdout]   33:     0x62941eed0882 - std[b80a194dd3c418bb]::thread::lifecycle::spawn_unchecked::<test[826cbc6ef54ab466]::run_test::{closure#1}, ()>::{closure#1}::{closure#0}
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/thread/lifecycle.rs:91:13
[INFO] [stdout]   34:     0x62941eed0882 - <core[10b6fa85044e1869]::panic::unwind_safe::AssertUnwindSafe<std[b80a194dd3c418bb]::thread::lifecycle::spawn_unchecked<test[826cbc6ef54ab466]::run_test::{closure#1}, ()>::{closure#1}::{closure#0}> as core[10b6fa85044e1869]::ops::function::FnOnce<()>>::call_once
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/core/src/panic/unwind_safe.rs:274:9
[INFO] [stdout]   35:     0x62941eed0882 - std[b80a194dd3c418bb]::panicking::catch_unwind::do_call::<core[10b6fa85044e1869]::panic::unwind_safe::AssertUnwindSafe<std[b80a194dd3c418bb]::thread::lifecycle::spawn_unchecked<test[826cbc6ef54ab466]::run_test::{closure#1}, ()>::{closure#1}::{closure#0}>, ()>
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/panicking.rs:581:40
[INFO] [stdout]   36:     0x62941eed0882 - std[b80a194dd3c418bb]::panicking::catch_unwind::<(), core[10b6fa85044e1869]::panic::unwind_safe::AssertUnwindSafe<std[b80a194dd3c418bb]::thread::lifecycle::spawn_unchecked<test[826cbc6ef54ab466]::run_test::{closure#1}, ()>::{closure#1}::{closure#0}>>
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/panicking.rs:544:19
[INFO] [stdout]   37:     0x62941eed0882 - std[b80a194dd3c418bb]::panic::catch_unwind::<core[10b6fa85044e1869]::panic::unwind_safe::AssertUnwindSafe<std[b80a194dd3c418bb]::thread::lifecycle::spawn_unchecked<test[826cbc6ef54ab466]::run_test::{closure#1}, ()>::{closure#1}::{closure#0}>, ()>
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/panic.rs:359:14
[INFO] [stdout]   38:     0x62941eed0882 - std[b80a194dd3c418bb]::thread::lifecycle::spawn_unchecked::<test[826cbc6ef54ab466]::run_test::{closure#1}, ()>::{closure#1}
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/thread/lifecycle.rs:89:26
[INFO] [stdout]   39:     0x62941eed0882 - <std[b80a194dd3c418bb]::thread::lifecycle::spawn_unchecked<test[826cbc6ef54ab466]::run_test::{closure#1}, ()>::{closure#1} as core[10b6fa85044e1869]::ops::function::FnOnce<()>>::call_once::{shim:vtable#0}
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/core/src/ops/function.rs:250:5
[INFO] [stdout]   40:     0x62941ef374ef - <alloc[dd269455e567d8e9]::boxed::Box<dyn core[10b6fa85044e1869]::ops::function::FnOnce<(), Output = ()> + core[10b6fa85044e1869]::marker::Send> as core[10b6fa85044e1869]::ops::function::FnOnce<()>>::call_once
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/alloc/src/boxed.rs:2240:9
[INFO] [stdout]   41:     0x62941ef374ef - <std[b80a194dd3c418bb]::sys::thread::unix::Thread>::new::thread_start
[INFO] [stdout]                                at /rustc/ad726b5063362ec9897ef3d67452fc5606ee70fa/library/std/src/sys/thread/unix.rs:118:17
[INFO] [stdout]   42:     0x7b0c43de7aa4 - <unknown>
[INFO] [stdout]   43:     0x7b0c43e74a64 - clone
[INFO] [stdout]   44:                0x0 - <unknown>
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] failures:
[INFO] [stdout]     test
[INFO] [stdout] 
[INFO] [stdout] test result: FAILED. 0 passed; 1 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.03s
[INFO] [stdout] 
[INFO] [stderr] error: test failed, to rerun pass `--bin rsicv_emulator`
[INFO] running `Command { std: "docker" "inspect" "fac38896e1eea49479b9c7a3ddd5cc3983a12223796f5d7dcc0ed9ab61b33907", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "fac38896e1eea49479b9c7a3ddd5cc3983a12223796f5d7dcc0ed9ab61b33907", kill_on_drop: false }`
[INFO] [stdout] fac38896e1eea49479b9c7a3ddd5cc3983a12223796f5d7dcc0ed9ab61b33907
