[INFO] cloning repository https://github.com/TinyCoor/riscv-emulator
[INFO] running `Command { std: "git" "-c" "credential.helper=" "-c" "credential.helper=/workspace/cargo-home/bin/git-credential-null" "clone" "--bare" "https://github.com/TinyCoor/riscv-emulator" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FTinyCoor%2Friscv-emulator", kill_on_drop: false }`
[INFO] [stderr] Cloning into bare repository '/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FTinyCoor%2Friscv-emulator'...
[INFO] running `Command { std: "git" "rev-parse" "HEAD", kill_on_drop: false }`
[INFO] [stdout] c9f6d41eb63ade8cc812287c5a158ed5c403cb9a
[INFO] testing TinyCoor/riscv-emulator against beta-2026-01-20 for beta-1.94-1
[INFO] running `Command { std: "git" "clone" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FTinyCoor%2Friscv-emulator" "/workspace/builds/worker-2-tc2/source", kill_on_drop: false }`
[INFO] [stderr] Cloning into '/workspace/builds/worker-2-tc2/source'...
[INFO] [stderr] done.
[INFO] started tweaking git repo https://github.com/TinyCoor/riscv-emulator
[INFO] finished tweaking git repo https://github.com/TinyCoor/riscv-emulator
[INFO] tweaked toml for git repo https://github.com/TinyCoor/riscv-emulator written to /workspace/builds/worker-2-tc2/source/Cargo.toml
[INFO] validating manifest of git repo https://github.com/TinyCoor/riscv-emulator on toolchain beta-2026-01-20
[INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+beta-2026-01-20" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }`
[INFO] crate git repo https://github.com/TinyCoor/riscv-emulator already has a lockfile, it will not be regenerated
[INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+beta-2026-01-20" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:98afbf2d16093dec2546ff8915fddc74e65664aa03fc460b3712b1c2c54a33e4" "/opt/rustwide/cargo-home/bin/cargo" "+beta-2026-01-20" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }`
[INFO] [stdout] a08b05d768958a5a97aa639a021214674e41b05a9c5730764bd1c5901f2ce084
[INFO] running `Command { std: "docker" "start" "-a" "a08b05d768958a5a97aa639a021214674e41b05a9c5730764bd1c5901f2ce084", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "inspect" "a08b05d768958a5a97aa639a021214674e41b05a9c5730764bd1c5901f2ce084", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "a08b05d768958a5a97aa639a021214674e41b05a9c5730764bd1c5901f2ce084", kill_on_drop: false }`
[INFO] [stdout] a08b05d768958a5a97aa639a021214674e41b05a9c5730764bd1c5901f2ce084
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=warn" "-e" "RUSTDOCFLAGS=--cap-lints=warn" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:98afbf2d16093dec2546ff8915fddc74e65664aa03fc460b3712b1c2c54a33e4" "/opt/rustwide/cargo-home/bin/cargo" "+beta-2026-01-20" "build" "--frozen" "--message-format=json", kill_on_drop: false }`
[INFO] [stdout] ea6d2749effa3905e436210a37c4c07f38112c32c8f5d9b75eec2558f2d56d45
[INFO] running `Command { std: "docker" "start" "-a" "ea6d2749effa3905e436210a37c4c07f38112c32c8f5d9b75eec2558f2d56d45", kill_on_drop: false }`
[INFO] [stderr]    Compiling rsicv_emulator v0.1.0 (/opt/rustwide/workdir)
[INFO] [stdout] warning: enum `Type` is never used
[INFO] [stdout]   --> src/main.rs:89:6
[INFO] [stdout]    |
[INFO] [stdout] 89 | enum Type {
[INFO] [stdout]    |      ^^^^
[INFO] [stdout]    |
[INFO] [stdout]    = note: `#[warn(dead_code)]` (part of `#[warn(unused)]`) on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: method `decode` is never used
[INFO] [stdout]   --> src/main.rs:99:8
[INFO] [stdout]    |
[INFO] [stdout] 98 | impl Type {
[INFO] [stdout]    | --------- method in this implementation
[INFO] [stdout] 99 |     fn decode(&self, inst: u32) -> Instruction {
[INFO] [stdout]    |        ^^^^^^
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: enum `Instruction` is never used
[INFO] [stdout]    --> src/main.rs:309:6
[INFO] [stdout]     |
[INFO] [stdout] 309 | enum Instruction {
[INFO] [stdout]     |      ^^^^^^^^^^^
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: function `decode` is never used
[INFO] [stdout]    --> src/main.rs:380:4
[INFO] [stdout]     |
[INFO] [stdout] 380 | fn decode(inst: u32) -> Instruction {
[INFO] [stdout]     |    ^^^^^^
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: constant `OPCODE_TABLE` is never used
[INFO] [stdout]    --> src/main.rs:389:7
[INFO] [stdout]     |
[INFO] [stdout] 389 | const OPCODE_TABLE:[Option<Type>; 128] = [
[INFO] [stdout]     |       ^^^^^^^^^^^^
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stderr]     Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.32s
[INFO] running `Command { std: "docker" "inspect" "ea6d2749effa3905e436210a37c4c07f38112c32c8f5d9b75eec2558f2d56d45", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "ea6d2749effa3905e436210a37c4c07f38112c32c8f5d9b75eec2558f2d56d45", kill_on_drop: false }`
[INFO] [stdout] ea6d2749effa3905e436210a37c4c07f38112c32c8f5d9b75eec2558f2d56d45
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=warn" "-e" "RUSTDOCFLAGS=--cap-lints=warn" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:98afbf2d16093dec2546ff8915fddc74e65664aa03fc460b3712b1c2c54a33e4" "/opt/rustwide/cargo-home/bin/cargo" "+beta-2026-01-20" "test" "--frozen" "--no-run" "--message-format=json", kill_on_drop: false }`
[INFO] [stdout] d9f7212bbd6bdbe158d2d375305e081e9b4a2c495b7c7d6bcea378875f1cff76
[INFO] running `Command { std: "docker" "start" "-a" "d9f7212bbd6bdbe158d2d375305e081e9b4a2c495b7c7d6bcea378875f1cff76", kill_on_drop: false }`
[INFO] [stderr]    Compiling rsicv_emulator v0.1.0 (/opt/rustwide/workdir)
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:312:11
[INFO] [stdout]     |
[INFO] [stdout] 312 |     Addiw{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ----- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout]     = note: `#[warn(dead_code)]` (part of `#[warn(unused)]`) on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:313:11
[INFO] [stdout]     |
[INFO] [stdout] 313 |     Slliw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:314:11
[INFO] [stdout]     |
[INFO] [stdout] 314 |     Srliw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:315:11
[INFO] [stdout]     |
[INFO] [stdout] 315 |     Sraiw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:317:10
[INFO] [stdout]     |
[INFO] [stdout] 317 |     Addi{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:318:10
[INFO] [stdout]     |
[INFO] [stdout] 318 |     Slti{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:319:11
[INFO] [stdout]     |
[INFO] [stdout] 319 |     Sltiu{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ----- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:320:10
[INFO] [stdout]     |
[INFO] [stdout] 320 |     Xori{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:321:9
[INFO] [stdout]     |
[INFO] [stdout] 321 |     Ori{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:322:10
[INFO] [stdout]     |
[INFO] [stdout] 322 |     Andi{rd: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:324:10
[INFO] [stdout]     |
[INFO] [stdout] 324 |     Slli{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:325:10
[INFO] [stdout]     |
[INFO] [stdout] 325 |     Srli{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stdout]    --> src/main.rs:326:10
[INFO] [stdout]     |
[INFO] [stdout] 326 |     Srai{rd: Register, rs1: Register, shamt: u32},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:328:10
[INFO] [stdout]     |
[INFO] [stdout] 328 |     Lb  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     --   ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:329:10
[INFO] [stdout]     |
[INFO] [stdout] 329 |     Lh  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     --   ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:330:10
[INFO] [stdout]     |
[INFO] [stdout] 330 |     Lw  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     --   ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:331:10
[INFO] [stdout]     |
[INFO] [stdout] 331 |     Lbu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     ---  ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:332:10
[INFO] [stdout]     |
[INFO] [stdout] 332 |     Lhu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     ---  ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:333:10
[INFO] [stdout]     |
[INFO] [stdout] 333 |     Lwu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     ---  ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:334:10
[INFO] [stdout]     |
[INFO] [stdout] 334 |     Ld  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stdout]     |     --   ^^             ^^^           ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:336:12
[INFO] [stdout]     |
[INFO] [stdout] 336 |     Fence {rd :Register, rs1:Register,  imm: i32},
[INFO] [stdout]     |     -----  ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:338:11
[INFO] [stdout]     |
[INFO] [stdout] 338 |     Jalr {rd :Register, rs1:Register,  imm: i32},
[INFO] [stdout]     |     ----  ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd` and `imm` are never read
[INFO] [stdout]    --> src/main.rs:340:12
[INFO] [stdout]     |
[INFO] [stdout] 340 |     Auipc {rd: Register, imm: i32},
[INFO] [stdout]     |     -----  ^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd` and `imm` are never read
[INFO] [stdout]    --> src/main.rs:341:10
[INFO] [stdout]     |
[INFO] [stdout] 341 |     Lui {rd: Register, imm: i32},
[INFO] [stdout]     |     ---  ^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:343:8
[INFO] [stdout]     |
[INFO] [stdout] 343 |     Sb{rs2: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     -- ^^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:344:8
[INFO] [stdout]     |
[INFO] [stdout] 344 |     Sh{rs2: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     -- ^^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:345:8
[INFO] [stdout]     |
[INFO] [stdout] 345 |     Sw{rs2: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     -- ^^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:346:8
[INFO] [stdout]     |
[INFO] [stdout] 346 |     Sd{rs2: Register, rs1: Register, imm: i32},
[INFO] [stdout]     |     -- ^^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:348:9
[INFO] [stdout]     |
[INFO] [stdout] 348 |     Add{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:349:9
[INFO] [stdout]     |
[INFO] [stdout] 349 |     Sub{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:350:9
[INFO] [stdout]     |
[INFO] [stdout] 350 |     Sll{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:351:9
[INFO] [stdout]     |
[INFO] [stdout] 351 |     Slt{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:352:10
[INFO] [stdout]     |
[INFO] [stdout] 352 |     Sltu{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:353:9
[INFO] [stdout]     |
[INFO] [stdout] 353 |     Xor{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:354:9
[INFO] [stdout]     |
[INFO] [stdout] 354 |     Srl{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:355:9
[INFO] [stdout]     |
[INFO] [stdout] 355 |     Sra{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:356:8
[INFO] [stdout]     |
[INFO] [stdout] 356 |     Or{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     -- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:357:9
[INFO] [stdout]     |
[INFO] [stdout] 357 |     And{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     --- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:360:10
[INFO] [stdout]     |
[INFO] [stdout] 360 |     Addw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:361:10
[INFO] [stdout]     |
[INFO] [stdout] 361 |     Subw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:362:10
[INFO] [stdout]     |
[INFO] [stdout] 362 |     Sllw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:363:10
[INFO] [stdout]     |
[INFO] [stdout] 363 |     Srlw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stdout]    --> src/main.rs:364:10
[INFO] [stdout]     |
[INFO] [stdout] 364 |     Sraw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stdout]     |     ---- ^^            ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:366:14
[INFO] [stdout]     |
[INFO] [stdout] 366 |     Beq     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ---      ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:367:14
[INFO] [stdout]     |
[INFO] [stdout] 367 |     Bne     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ---      ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:368:14
[INFO] [stdout]     |
[INFO] [stdout] 368 |     Blt     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ---      ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:369:14
[INFO] [stdout]     |
[INFO] [stdout] 369 |     Bge     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ---      ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:370:14
[INFO] [stdout]     |
[INFO] [stdout] 370 |     Bltu    {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ----     ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stdout]    --> src/main.rs:371:14
[INFO] [stdout]     |
[INFO] [stdout] 371 |     Bgeu    {rs1: Register,rs2: Register, imm:i32},
[INFO] [stdout]     |     ----     ^^^           ^^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: fields `rd` and `imm` are never read
[INFO] [stdout]    --> src/main.rs:373:10
[INFO] [stdout]     |
[INFO] [stdout] 373 |     Jal {rd :Register, imm: i32},
[INFO] [stdout]     |     ---  ^^            ^^^
[INFO] [stdout]     |     |
[INFO] [stdout]     |     fields in this variant
[INFO] [stdout]     |
[INFO] [stdout]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stderr]     Finished `test` profile [unoptimized + debuginfo] target(s) in 0.40s
[INFO] running `Command { std: "docker" "inspect" "d9f7212bbd6bdbe158d2d375305e081e9b4a2c495b7c7d6bcea378875f1cff76", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "d9f7212bbd6bdbe158d2d375305e081e9b4a2c495b7c7d6bcea378875f1cff76", kill_on_drop: false }`
[INFO] [stdout] d9f7212bbd6bdbe158d2d375305e081e9b4a2c495b7c7d6bcea378875f1cff76
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-2-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=warn" "-e" "RUSTDOCFLAGS=--cap-lints=warn" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:98afbf2d16093dec2546ff8915fddc74e65664aa03fc460b3712b1c2c54a33e4" "/opt/rustwide/cargo-home/bin/cargo" "+beta-2026-01-20" "test" "--frozen", kill_on_drop: false }`
[INFO] [stdout] af5dc64da9c1f35a6bfece2d21a1f199377a28be98eb6b0873b7e32204cfb113
[INFO] running `Command { std: "docker" "start" "-a" "af5dc64da9c1f35a6bfece2d21a1f199377a28be98eb6b0873b7e32204cfb113", kill_on_drop: false }`
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:312:11
[INFO] [stderr]     |
[INFO] [stderr] 312 |     Addiw{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ----- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr]     = note: `#[warn(dead_code)]` (part of `#[warn(unused)]`) on by default
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:313:11
[INFO] [stderr]     |
[INFO] [stderr] 313 |     Slliw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:314:11
[INFO] [stderr]     |
[INFO] [stderr] 314 |     Srliw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:315:11
[INFO] [stderr]     |
[INFO] [stderr] 315 |     Sraiw{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ----- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:317:10
[INFO] [stderr]     |
[INFO] [stderr] 317 |     Addi{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:318:10
[INFO] [stderr]     |
[INFO] [stderr] 318 |     Slti{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:319:11
[INFO] [stderr]     |
[INFO] [stderr] 319 |     Sltiu{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ----- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:320:10
[INFO] [stderr]     |
[INFO] [stderr] 320 |     Xori{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:321:9
[INFO] [stderr]     |
[INFO] [stderr] 321 |     Ori{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:322:10
[INFO] [stderr]     |
[INFO] [stderr] 322 |     Andi{rd: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:324:10
[INFO] [stderr]     |
[INFO] [stderr] 324 |     Slli{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:325:10
[INFO] [stderr]     |
[INFO] [stderr] 325 |     Srli{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `shamt` are never read
[INFO] [stderr]    --> src/main.rs:326:10
[INFO] [stderr]     |
[INFO] [stderr] 326 |     Srai{rd: Register, rs1: Register, shamt: u32},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:328:10
[INFO] [stderr]     |
[INFO] [stderr] 328 |     Lb  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     --   ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:329:10
[INFO] [stderr]     |
[INFO] [stderr] 329 |     Lh  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     --   ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:330:10
[INFO] [stderr]     |
[INFO] [stderr] 330 |     Lw  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     --   ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:331:10
[INFO] [stderr]     |
[INFO] [stderr] 331 |     Lbu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     ---  ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:332:10
[INFO] [stderr]     |
[INFO] [stderr] 332 |     Lhu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     ---  ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:333:10
[INFO] [stderr]     |
[INFO] [stderr] 333 |     Lwu {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     ---  ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:334:10
[INFO] [stderr]     |
[INFO] [stderr] 334 |     Ld  {rd: Register,  rs1:Register, imm: i32},
[INFO] [stderr]     |     --   ^^             ^^^           ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:336:12
[INFO] [stderr]     |
[INFO] [stderr] 336 |     Fence {rd :Register, rs1:Register,  imm: i32},
[INFO] [stderr]     |     -----  ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:338:11
[INFO] [stderr]     |
[INFO] [stderr] 338 |     Jalr {rd :Register, rs1:Register,  imm: i32},
[INFO] [stderr]     |     ----  ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd` and `imm` are never read
[INFO] [stderr]    --> src/main.rs:340:12
[INFO] [stderr]     |
[INFO] [stderr] 340 |     Auipc {rd: Register, imm: i32},
[INFO] [stderr]     |     -----  ^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd` and `imm` are never read
[INFO] [stderr]    --> src/main.rs:341:10
[INFO] [stderr]     |
[INFO] [stderr] 341 |     Lui {rd: Register, imm: i32},
[INFO] [stderr]     |     ---  ^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:343:8
[INFO] [stderr]     |
[INFO] [stderr] 343 |     Sb{rs2: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     -- ^^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:344:8
[INFO] [stderr]     |
[INFO] [stderr] 344 |     Sh{rs2: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     -- ^^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:345:8
[INFO] [stderr]     |
[INFO] [stderr] 345 |     Sw{rs2: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     -- ^^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs2`, `rs1`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:346:8
[INFO] [stderr]     |
[INFO] [stderr] 346 |     Sd{rs2: Register, rs1: Register, imm: i32},
[INFO] [stderr]     |     -- ^^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:348:9
[INFO] [stderr]     |
[INFO] [stderr] 348 |     Add{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:349:9
[INFO] [stderr]     |
[INFO] [stderr] 349 |     Sub{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:350:9
[INFO] [stderr]     |
[INFO] [stderr] 350 |     Sll{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:351:9
[INFO] [stderr]     |
[INFO] [stderr] 351 |     Slt{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:352:10
[INFO] [stderr]     |
[INFO] [stderr] 352 |     Sltu{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:353:9
[INFO] [stderr]     |
[INFO] [stderr] 353 |     Xor{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:354:9
[INFO] [stderr]     |
[INFO] [stderr] 354 |     Srl{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:355:9
[INFO] [stderr]     |
[INFO] [stderr] 355 |     Sra{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:356:8
[INFO] [stderr]     |
[INFO] [stderr] 356 |     Or{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     -- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:357:9
[INFO] [stderr]     |
[INFO] [stderr] 357 |     And{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     --- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:360:10
[INFO] [stderr]     |
[INFO] [stderr] 360 |     Addw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:361:10
[INFO] [stderr]     |
[INFO] [stderr] 361 |     Subw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:362:10
[INFO] [stderr]     |
[INFO] [stderr] 362 |     Sllw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:363:10
[INFO] [stderr]     |
[INFO] [stderr] 363 |     Srlw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd`, `rs1`, and `rs2` are never read
[INFO] [stderr]    --> src/main.rs:364:10
[INFO] [stderr]     |
[INFO] [stderr] 364 |     Sraw{rd: Register, rs1: Register, rs2: Register},
[INFO] [stderr]     |     ---- ^^            ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:366:14
[INFO] [stderr]     |
[INFO] [stderr] 366 |     Beq     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ---      ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:367:14
[INFO] [stderr]     |
[INFO] [stderr] 367 |     Bne     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ---      ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:368:14
[INFO] [stderr]     |
[INFO] [stderr] 368 |     Blt     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ---      ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:369:14
[INFO] [stderr]     |
[INFO] [stderr] 369 |     Bge     {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ---      ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:370:14
[INFO] [stderr]     |
[INFO] [stderr] 370 |     Bltu    {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ----     ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rs1`, `rs2`, and `imm` are never read
[INFO] [stderr]    --> src/main.rs:371:14
[INFO] [stderr]     |
[INFO] [stderr] 371 |     Bgeu    {rs1: Register,rs2: Register, imm:i32},
[INFO] [stderr]     |     ----     ^^^           ^^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: fields `rd` and `imm` are never read
[INFO] [stderr]    --> src/main.rs:373:10
[INFO] [stderr]     |
[INFO] [stderr] 373 |     Jal {rd :Register, imm: i32},
[INFO] [stderr]     |     ---  ^^            ^^^
[INFO] [stderr]     |     |
[INFO] [stderr]     |     fields in this variant
[INFO] [stderr]     |
[INFO] [stderr]     = note: `Instruction` has a derived impl for the trait `Debug`, but this is intentionally ignored during dead code analysis
[INFO] [stderr] 
[INFO] [stderr] warning: `rsicv_emulator` (bin "rsicv_emulator" test) generated 50 warnings
[INFO] [stderr]     Finished `test` profile [unoptimized + debuginfo] target(s) in 0.09s
[INFO] [stderr]      Running unittests src/main.rs (/opt/rustwide/target/debug/deps/rsicv_emulator-36e4cce0cb167c4a)
[INFO] [stdout] 
[INFO] [stdout] running 1 test
[INFO] [stdout] test test ... FAILED
[INFO] [stdout] 
[INFO] [stdout] failures:
[INFO] [stdout] 
[INFO] [stdout] ---- test stdout ----
[INFO] [stdout] 
[INFO] [stdout] thread 'test' (25) panicked at src/main.rs:304:5:
[INFO] [stdout] Failed
[INFO] [stdout] 
[INFO] [stdout] stack backtrace:
[INFO] [stdout]    0:     0x556caa681cf2 - std::backtrace_rs::backtrace::libunwind::trace::hf0bd46b30bc61685
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/../../backtrace/src/backtrace/libunwind.rs:117:9
[INFO] [stdout]    1:     0x556caa681cf2 - std::backtrace_rs::backtrace::trace_unsynchronized::h1d1fbb72ad89d7b7
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/../../backtrace/src/backtrace/mod.rs:66:14
[INFO] [stdout]    2:     0x556caa681cf2 - std::sys::backtrace::_print_fmt::he38b6f68ca847f47
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/sys/backtrace.rs:74:9
[INFO] [stdout]    3:     0x556caa681cf2 - <std::sys::backtrace::BacktraceLock::print::DisplayBacktrace as core::fmt::Display>::fmt::hb7e843cde1bc81a3
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/sys/backtrace.rs:44:26
[INFO] [stdout]    4:     0x556caa691d4a - core::fmt::rt::Argument::fmt::hc1dd77ac64f2688c
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/core/src/fmt/rt.rs:152:76
[INFO] [stdout]    5:     0x556caa691d4a - core::fmt::write::h952c506e2dbe9cff
[INFO] [stdout]    6:     0x556caa650c76 - std::io::default_write_fmt::hd23bd8145c03a23a
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/io/mod.rs:639:11
[INFO] [stdout]    7:     0x556caa650c76 - std::io::Write::write_fmt::hdd3314a2bd8a34bd
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/io/mod.rs:1994:13
[INFO] [stdout]    8:     0x556caa6611d9 - std::sys::backtrace::BacktraceLock::print::h1079b82381c2c252
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/sys/backtrace.rs:47:9
[INFO] [stdout]    9:     0x556caa6611d9 - std::panicking::default_hook::{{closure}}::h85cb76b8462c00f2
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/panicking.rs:292:27
[INFO] [stdout]   10:     0x556caa661071 - std::panicking::default_hook::h0134d220cc034c02
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/panicking.rs:316:9
[INFO] [stdout]   11:     0x556caa62571e - <alloc::boxed::Box<F,A> as core::ops::function::Fn<Args>>::call::hb2e68dca3970e3ca
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/alloc/src/boxed.rs:2220:9
[INFO] [stdout]   12:     0x556caa62571e - test::test_main_with_exit_callback::{{closure}}::ha7ec2063a2565ec3
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/test/src/lib.rs:145:21
[INFO] [stdout]   13:     0x556caa661452 - <alloc::boxed::Box<F,A> as core::ops::function::Fn<Args>>::call::haebee478d0f56cf4
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/alloc/src/boxed.rs:2220:9
[INFO] [stdout]   14:     0x556caa661452 - std::panicking::panic_with_hook::h8119b6db1fef734f
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/panicking.rs:833:13
[INFO] [stdout]   15:     0x556caa6612ca - std::panicking::panic_handler::{{closure}}::h24f5360b91482c0e
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/panicking.rs:691:13
[INFO] [stdout]   16:     0x556caa65c829 - std::sys::backtrace::__rust_end_short_backtrace::h4e60c5cbd1bd0108
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/sys/backtrace.rs:182:18
[INFO] [stdout]   17:     0x556caa64586d - __rustc[e4c6931bd8050421]::rust_begin_unwind
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/panicking.rs:689:5
[INFO] [stdout]   18:     0x556caa69903c - core::panicking::panic_fmt::hb1614a3ff6840071
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/core/src/panicking.rs:80:14
[INFO] [stdout]   19:     0x556caa605b61 - rsicv_emulator::test::h77588f1a36c1d761
[INFO] [stdout]                                at /opt/rustwide/workdir/src/main.rs:304:5
[INFO] [stdout]   20:     0x556caa605b87 - rsicv_emulator::test::{{closure}}::h9f9f1c348748f174
[INFO] [stdout]                                at /opt/rustwide/workdir/src/main.rs:301:10
[INFO] [stdout]   21:     0x556caa605d26 - core::ops::function::FnOnce::call_once::h51d76a96bd531a56
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/core/src/ops/function.rs:250:5
[INFO] [stdout]   22:     0x556caa62551b - core::ops::function::FnOnce::call_once::hefaf63600cd43d2a
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/core/src/ops/function.rs:250:5
[INFO] [stdout]   23:     0x556caa62551b - test::__rust_begin_short_backtrace::he30322a73a0e9ea6
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/test/src/lib.rs:663:18
[INFO] [stdout]   24:     0x556caa638eea - test::run_test_in_process::{{closure}}::hdea3ab8d0243ef36
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/test/src/lib.rs:686:74
[INFO] [stdout]   25:     0x556caa638eea - <core::panic::unwind_safe::AssertUnwindSafe<F> as core::ops::function::FnOnce<()>>::call_once::h66d192f42498ffce
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/core/src/panic/unwind_safe.rs:274:9
[INFO] [stdout]   26:     0x556caa638eea - std::panicking::catch_unwind::do_call::h822e18e8d3a6bb65
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/panicking.rs:581:40
[INFO] [stdout]   27:     0x556caa638eea - std::panicking::catch_unwind::h54b1de7ceab578bf
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/panicking.rs:544:19
[INFO] [stdout]   28:     0x556caa638eea - std::panic::catch_unwind::h60c29b7a9d0246b1
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/panic.rs:359:14
[INFO] [stdout]   29:     0x556caa638eea - test::run_test_in_process::h6099b5f871379b13
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/test/src/lib.rs:686:27
[INFO] [stdout]   30:     0x556caa638eea - test::run_test::{{closure}}::h926ce0a38281a4c8
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/test/src/lib.rs:607:43
[INFO] [stdout]   31:     0x556caa613344 - test::run_test::{{closure}}::h508de21a9afc7140
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/test/src/lib.rs:637:41
[INFO] [stdout]   32:     0x556caa613344 - std::sys::backtrace::__rust_begin_short_backtrace::h6e2f5c39ca00735a
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/sys/backtrace.rs:166:18
[INFO] [stdout]   33:     0x556caa616c02 - std::thread::lifecycle::spawn_unchecked::{{closure}}::{{closure}}::h133e44f0e5802c14
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/thread/lifecycle.rs:91:13
[INFO] [stdout]   34:     0x556caa616c02 - <core::panic::unwind_safe::AssertUnwindSafe<F> as core::ops::function::FnOnce<()>>::call_once::h4718c1285283955c
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/core/src/panic/unwind_safe.rs:274:9
[INFO] [stdout]   35:     0x556caa616c02 - std::panicking::catch_unwind::do_call::h0bba3937b4892238
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/panicking.rs:581:40
[INFO] [stdout]   36:     0x556caa616c02 - std::panicking::catch_unwind::h5b31cab5fb8c5d7f
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/panicking.rs:544:19
[INFO] [stdout]   37:     0x556caa616c02 - std::panic::catch_unwind::hb2fa05d52ed0124e
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/panic.rs:359:14
[INFO] [stdout]   38:     0x556caa616c02 - std::thread::lifecycle::spawn_unchecked::{{closure}}::hf401cf5ff501bd29
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/thread/lifecycle.rs:89:26
[INFO] [stdout]   39:     0x556caa616c02 - core::ops::function::FnOnce::call_once{{vtable.shim}}::h160022e94ce3b0bb
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/core/src/ops/function.rs:250:5
[INFO] [stdout]   40:     0x556caa657abf - <alloc::boxed::Box<F,A> as core::ops::function::FnOnce<Args>>::call_once::hf234e0d1d1d272ba
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/alloc/src/boxed.rs:2206:9
[INFO] [stdout]   41:     0x556caa657abf - std::sys::thread::unix::Thread::new::thread_start::h106a295241840d3b
[INFO] [stdout]                                at /rustc/9b1f8ff42d110b0ca138116745be921df5dc97e7/library/std/src/sys/thread/unix.rs:127:17
[INFO] [stdout]   42:     0x79f13f9b7aa4 - <unknown>
[INFO] [stdout]   43:     0x79f13fa44a64 - clone
[INFO] [stdout]   44:                0x0 - <unknown>
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] failures:
[INFO] [stdout]     test
[INFO] [stdout] 
[INFO] [stdout] test result: FAILED. 0 passed; 1 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.02s
[INFO] [stdout] 
[INFO] [stderr] error: test failed, to rerun pass `--bin rsicv_emulator`
[INFO] running `Command { std: "docker" "inspect" "af5dc64da9c1f35a6bfece2d21a1f199377a28be98eb6b0873b7e32204cfb113", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "af5dc64da9c1f35a6bfece2d21a1f199377a28be98eb6b0873b7e32204cfb113", kill_on_drop: false }`
[INFO] [stdout] af5dc64da9c1f35a6bfece2d21a1f199377a28be98eb6b0873b7e32204cfb113
