[INFO] cloning repository https://github.com/HOddyPropsting/Gameboy-Emulator
[INFO] running `Command { std: "git" "-c" "credential.helper=" "-c" "credential.helper=/workspace/cargo-home/bin/git-credential-null" "clone" "--bare" "https://github.com/HOddyPropsting/Gameboy-Emulator" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FHOddyPropsting%2FGameboy-Emulator", kill_on_drop: false }`
[INFO] [stderr] Cloning into bare repository '/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FHOddyPropsting%2FGameboy-Emulator'...
[INFO] running `Command { std: "git" "rev-parse" "HEAD", kill_on_drop: false }`
[INFO] [stdout] 2a4212e1d2baf148900aa804c3752e261eadad81
[INFO] documenting HOddyPropsting/Gameboy-Emulator against beta-2020-08-29 for beta-1.47-rustdoc-1
[INFO] running `Command { std: "git" "clone" "/workspace/cache/git-repos/https%3A%2F%2Fgithub.com%2FHOddyPropsting%2FGameboy-Emulator" "/workspace/builds/worker-5/source", kill_on_drop: false }`
[INFO] [stderr] Cloning into '/workspace/builds/worker-5/source'...
[INFO] [stderr] done.
[INFO] validating manifest of git repo https://github.com/HOddyPropsting/Gameboy-Emulator on toolchain beta-2020-08-29
[INFO] running `Command { std: "/workspace/cargo-home/bin/cargo" "+beta-2020-08-29" "read-manifest" "--manifest-path" "Cargo.toml", kill_on_drop: false }`
[INFO] started tweaking git repo https://github.com/HOddyPropsting/Gameboy-Emulator
[INFO] finished tweaking git repo https://github.com/HOddyPropsting/Gameboy-Emulator
[INFO] tweaked toml for git repo https://github.com/HOddyPropsting/Gameboy-Emulator written to /workspace/builds/worker-5/source/Cargo.toml
[INFO] crate git repo https://github.com/HOddyPropsting/Gameboy-Emulator already has a lockfile, it will not be regenerated
[INFO] running `Command { std: "/workspace/cargo-home/bin/cargo" "+beta-2020-08-29" "fetch" "--locked" "--manifest-path" "Cargo.toml", kill_on_drop: false }`
[INFO] [stderr]     Blocking waiting for file lock on package cache
[INFO] [stderr]     Updating crates.io index
[INFO] [stderr] error: the lock file /workspace/builds/worker-5/source/Cargo.lock needs to be updated but --locked was passed to prevent this
[INFO] [stderr] If you want to try to generate the lock file without accessing the network, use the --offline flag.
[INFO] the lockfile is outdated, regenerating it
[INFO] running `Command { std: "/workspace/cargo-home/bin/cargo" "+beta-2020-08-29" "generate-lockfile" "--manifest-path" "Cargo.toml" "-Zno-index-update", kill_on_drop: false }`
[INFO] [stderr]     Blocking waiting for file lock on package cache
[INFO] running `Command { std: "/workspace/cargo-home/bin/cargo" "+beta-2020-08-29" "fetch" "--locked" "--manifest-path" "Cargo.toml", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-5/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-5/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "rustops/crates-build-env@sha256:d92eaeed33fa75130ca1ee6c8a01d1ffb62bac859dfdfb3450e3e5d1c0146529" "/opt/rustwide/cargo-home/bin/cargo" "+beta-2020-08-29" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }`
[INFO] [stdout] 6d936b6fb62fd223bf4a0e147cddbf291f48ec9abac3abc7a766dada1da381d8
[INFO] [stderr] WARNING: Your kernel does not support swap limit capabilities or the cgroup is not mounted. Memory limited without swap.
[INFO] running `Command { std: "docker" "start" "-a" "6d936b6fb62fd223bf4a0e147cddbf291f48ec9abac3abc7a766dada1da381d8", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "inspect" "6d936b6fb62fd223bf4a0e147cddbf291f48ec9abac3abc7a766dada1da381d8", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "6d936b6fb62fd223bf4a0e147cddbf291f48ec9abac3abc7a766dada1da381d8", kill_on_drop: false }`
[INFO] [stdout] 6d936b6fb62fd223bf4a0e147cddbf291f48ec9abac3abc7a766dada1da381d8
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-5/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-5/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTDOCFLAGS=--cap-lints=warn" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "1610612736" "--user" "0:0" "--network" "none" "rustops/crates-build-env@sha256:d92eaeed33fa75130ca1ee6c8a01d1ffb62bac859dfdfb3450e3e5d1c0146529" "/opt/rustwide/cargo-home/bin/cargo" "+beta-2020-08-29" "doc" "--frozen" "--no-deps" "--document-private-items" "--message-format=json", kill_on_drop: false }`
[INFO] [stdout] 05b029e92da0b3dd2a6c692362fdbae8661b008113437316339877a679840421
[INFO] [stderr] WARNING: Your kernel does not support swap limit capabilities or the cgroup is not mounted. Memory limited without swap.
[INFO] running `Command { std: "docker" "start" "-a" "05b029e92da0b3dd2a6c692362fdbae8661b008113437316339877a679840421", kill_on_drop: false }`
[INFO] [stderr]    Compiling gb v0.1.0 (/opt/rustwide/workdir)
[INFO] [stderr]     Checking sdl2 v0.30.0
[INFO] [stderr]  Documenting gb v0.1.0 (/opt/rustwide/workdir)
[INFO] [stdout] warning: unnecessary trailing semicolon
[INFO] [stdout]    --> src/cpu.rs:721:42
[INFO] [stdout]     |
[INFO] [stdout] 721 |       0x56 => { ld_8!(self,D,HL_address);;
[INFO] [stdout]     |                                          ^ help: remove this semicolon
[INFO] [stdout]     |
[INFO] [stdout]     = note: `#[warn(redundant_semicolons)]` on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1294:12
[INFO] [stdout]      |
[INFO] [stdout] 1294 |       0o000...0o007 => self.rlc(reg_vec[(instruction % 8) as usize]),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout]      |
[INFO] [stdout]      = note: `#[warn(ellipsis_inclusive_range_patterns)]` on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1295:12
[INFO] [stdout]      |
[INFO] [stdout] 1295 |       0o010...0o017 => self.rrc(reg_vec[(instruction % 8) as usize]),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1296:12
[INFO] [stdout]      |
[INFO] [stdout] 1296 |       0o020...0o027 => self.rl(reg_vec[(instruction % 8) as usize]),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1297:12
[INFO] [stdout]      |
[INFO] [stdout] 1297 |       0o030...0o037 => self.rr(reg_vec[(instruction % 8) as usize]),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1298:12
[INFO] [stdout]      |
[INFO] [stdout] 1298 |       0o040...0o047 => self.sla(reg_vec[(instruction % 8) as usize]),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1299:12
[INFO] [stdout]      |
[INFO] [stdout] 1299 |       0o050...0o057 => self.sra(reg_vec[(instruction % 8) as usize]),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1300:12
[INFO] [stdout]      |
[INFO] [stdout] 1300 |       0o060...0o067 => self.swap(reg_vec[(instruction % 8) as usize]),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1301:12
[INFO] [stdout]      |
[INFO] [stdout] 1301 |       0o070...0o077 => self.srl(reg_vec[(instruction % 8) as usize]),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1302:12
[INFO] [stdout]      |
[INFO] [stdout] 1302 |       0o100...0o107 => self.bit(reg_vec[(instruction % 8) as usize], Bit::One),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1303:12
[INFO] [stdout]      |
[INFO] [stdout] 1303 |       0o110...0o117 => self.bit(reg_vec[(instruction % 8) as usize], Bit::Two),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1304:12
[INFO] [stdout]      |
[INFO] [stdout] 1304 |       0o120...0o127 => self.bit(reg_vec[(instruction % 8) as usize], Bit::Three),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1305:12
[INFO] [stdout]      |
[INFO] [stdout] 1305 |       0o130...0o137 => self.bit(reg_vec[(instruction % 8) as usize], Bit::Four),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1306:12
[INFO] [stdout]      |
[INFO] [stdout] 1306 |       0o140...0o147 => self.bit(reg_vec[(instruction % 8) as usize], Bit::Five),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1307:12
[INFO] [stdout]      |
[INFO] [stdout] 1307 |       0o150...0o157 => self.bit(reg_vec[(instruction % 8) as usize], Bit::Six),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1308:12
[INFO] [stdout]      |
[INFO] [stdout] 1308 |       0o160...0o167 => self.bit(reg_vec[(instruction % 8) as usize], Bit::Seven),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1309:12
[INFO] [stdout]      |
[INFO] [stdout] 1309 |       0o170...0o177 => self.bit(reg_vec[(instruction % 8) as usize], Bit::Eight),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1310:12
[INFO] [stdout]      |
[INFO] [stdout] 1310 |       0o200...0o207 => self.res(reg_vec[(instruction % 8) as usize], Bit::One),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1311:12
[INFO] [stdout]      |
[INFO] [stdout] 1311 |       0o210...0o217 => self.res(reg_vec[(instruction % 8) as usize], Bit::Two),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1312:12
[INFO] [stdout]      |
[INFO] [stdout] 1312 |       0o220...0o227 => self.res(reg_vec[(instruction % 8) as usize], Bit::Three),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1313:12
[INFO] [stdout]      |
[INFO] [stdout] 1313 |       0o230...0o237 => self.res(reg_vec[(instruction % 8) as usize], Bit::Four),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1314:12
[INFO] [stdout]      |
[INFO] [stdout] 1314 |       0o240...0o247 => self.res(reg_vec[(instruction % 8) as usize], Bit::Five),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1315:12
[INFO] [stdout]      |
[INFO] [stdout] 1315 |       0o250...0o257 => self.res(reg_vec[(instruction % 8) as usize], Bit::Six),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1316:12
[INFO] [stdout]      |
[INFO] [stdout] 1316 |       0o260...0o267 => self.res(reg_vec[(instruction % 8) as usize], Bit::Seven),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1317:12
[INFO] [stdout]      |
[INFO] [stdout] 1317 |       0o270...0o277 => self.res(reg_vec[(instruction % 8) as usize], Bit::Eight),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1318:12
[INFO] [stdout]      |
[INFO] [stdout] 1318 |       0o300...0o307 => self.set(reg_vec[(instruction % 8) as usize], Bit::One),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1319:12
[INFO] [stdout]      |
[INFO] [stdout] 1319 |       0o310...0o317 => self.set(reg_vec[(instruction % 8) as usize], Bit::Two),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1320:12
[INFO] [stdout]      |
[INFO] [stdout] 1320 |       0o320...0o327 => self.set(reg_vec[(instruction % 8) as usize], Bit::Three),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1321:12
[INFO] [stdout]      |
[INFO] [stdout] 1321 |       0o330...0o337 => self.set(reg_vec[(instruction % 8) as usize], Bit::Four),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1322:12
[INFO] [stdout]      |
[INFO] [stdout] 1322 |       0o340...0o347 => self.set(reg_vec[(instruction % 8) as usize], Bit::Five),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1323:12
[INFO] [stdout]      |
[INFO] [stdout] 1323 |       0o350...0o357 => self.set(reg_vec[(instruction % 8) as usize], Bit::Six),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1324:12
[INFO] [stdout]      |
[INFO] [stdout] 1324 |       0o360...0o367 => self.set(reg_vec[(instruction % 8) as usize], Bit::Seven),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: `...` range patterns are deprecated
[INFO] [stdout]     --> src/cpu.rs:1325:12
[INFO] [stdout]      |
[INFO] [stdout] 1325 |       0o370...0o377 => self.set(reg_vec[(instruction % 8) as usize], Bit::Eight),
[INFO] [stdout]      |            ^^^ help: use `..=` for an inclusive range
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: unnecessary braces around assigned value
[INFO] [stdout]   --> src/lcd.rs:50:37
[INFO] [stdout]    |
[INFO] [stdout] 50 | const BG_COLOR_SHADES : [Color;4] = {[COLOR_WHITE, COLOR_L_GREY, COLOR_GREY, COLOR_BLACK]};
[INFO] [stdout]    |                                     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: remove these braces
[INFO] [stdout]    |
[INFO] [stdout]    = note: `#[warn(unused_braces)]` on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: 34 warnings emitted
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stderr]     Finished dev [unoptimized + debuginfo] target(s) in 5.34s
[INFO] running `Command { std: "docker" "inspect" "05b029e92da0b3dd2a6c692362fdbae8661b008113437316339877a679840421", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "05b029e92da0b3dd2a6c692362fdbae8661b008113437316339877a679840421", kill_on_drop: false }`
[INFO] [stdout] 05b029e92da0b3dd2a6c692362fdbae8661b008113437316339877a679840421